Document Outline

TABLE OF CONTENTS
- List of Figures
- List of Tables
FUNCTIONAL DESCRIPTION
- Functional Overview
  - Bt829A Video Capture Processor for TV/VCR Analog Input
  - Bt827A Composite/S-Video Decoder
  - Bt829A Architecture and Parititioning
  - UltraLock
  - Scaling and Cropping
  - Input Interface
  - Output Interface
  - VBI Data Pass-through
  - Closed Caption Decoding
  - I2C Interface
- Pin Descriptions
- Differences Between Bt829/827 and Bt829A/827A
- UltraLock’
  - The Challenge
  - Operation Principles of UltraLock
- Composite Video Input Formats
- Y/C Separation and Chroma Demodulation
- Video Scaling, Cropping, and Temporal Decimation
  - Horizontal and Vertical Scaling
  - Luminance Scaling
  - Peaking
  - Chrominance Scaling
  - Scaling Registers
  - Image Cropping
  - Cropping Registers
  - Temporal Decimation
- Video Adjustments
  - The Hue Adjust Register (HUE)
  - The Contrast Adjust Register (CONTRAST)
  - The Saturation Adjust Registers (SAT_U, SAT_V)
  - The Brightness Register (BRIGHT)
- Bt829A VBI Data Output Interface
  - Introduction
  - Overview
  - Functional Description
  - VBI Line Output Mode
  - VBI Frame Output Mode
- Closed Captioning and Extended Data Services Decoding
  - Automatic Chrominance Gain Control
  - Low Color Detection and Removal
  - Coring
ELECTRICAL INTERFACES
- Input Interface
  - Analog Signal Selection
  - Multiplexer Considerations
  - Autodetection of NTSC or PAL/SECAM Video
  - Flash A/D Converters
  - A/D Clamping
  - Power-up Operation
  - Automatic Gain Controls
  - Crystal Inputs and Clock Generation
  - 2X Oversampling and Input Filtering
- Output Interface
  - YCrCb Pixel Stream Format, SPI Mode 8- and 16-bit Formats
  - Synchronous Pixel Interface (SPI, Mode 1)
  - Synchronous Pixel Interface (SPI, Mode 2, ByteStream)
  - CCIR601 Compliance
- I2C interface
  - Starting and Stopping
  - Addressing the Bt829A
  - Reading and Writing
  - Software Reset
- JTAG Interface Need for Fuctional Verfication
PC BOARD LAYOUT CONSIDERATIONS
- Ground Planes
- Power Planes
- Supply Decoupling
- Digital Signal Interconnect
- Analog Signal Interconnect
- Latch-up Avoidance
- Sample Schematics
- JTAG Approach to Testability
- Optional Device ID Register
- Veri“cation with the Tap Controller
- Example BSDL Listing
CONTROL REGISTER DEFINITIONS
- 0x00 „ Device Status Register (STATUS)
- 0x01 „ Input Format Register (IFORM)
- 0x02 „ Temporal Decimation Register (TDEC)
- 0x03 „ MSB Cropping Register (CROP)
- 0x04 „ Vertical Delay Register, Lower Byte (VDELAY_LO)
- 0x05 „ Vertical Active Register, Lower Byte (VACTIVE_LO)
- 0x06 „ Horizontal Delay Register, Lower Byte (HDELAY_LO)
- 0x07 „ Horizontal Active Register, Lower Byte (HACTIVE_LO)
- 0x08 „ Horizontal Scaling Register, Upper Byte (HSCALE_HI
- 0x09 „ Horizontal Scaling Register, Lower Byte (HSCALE_LO)
- 0x0A „ Brightness Control Register (BRIGHT)
- 0x0B „ Miscellaneous Control Register (CONTROL)
- 0x0C „ Luma Gain Register, Lower Byte (CONTRAST_LO)
- 0x0D „ Chroma (U) Gain Register, Lower Byte (SAT_U_LO)
- 0x0E „ Chroma (V) Gain Register, Lower Byte (SAT_V_LO)
- 0x0F „ Hue Control Register (HUE)
- 0x10 „ SC Loop Control (SCLOOP)
- 0x11 „ White Crush Up Count Register (WC_UP)
- 0x12 „ Output Format Register (OFORM)
- 0x13 „ Vertical Scaling Register, Upper Byte (VSCALE_HI)
- 0x14 „ Vertical Scaling Register, Lower Byte (VSCALE_LO)
- 0x15 „ Test Control Register (TEST)
- 0x16 „ Video Timing Polarity Register (VPOLE)
- 0x17 „ ID Code Register (IDCODE)
- 0x18 „ AGC Delay Register (ADELAY)
- 0x19 „ Burst Delay Register (BDELAY)
- 0x1A „ ADC Interface Register (ADC)
- 0x1B „ Video Timing Control (VTC)
- 0x1C „ Extended Data Service/Closed Caption Status Register (CC_STATUS)
- 0x1D „ Extended Data Service/Closed Caption Data Register (CC_DATA)
- 0x1E „ White Crush Down Count Register (WC_DN)
- 0x1F „ Software Reset Register (SRESET)
- 0x3F „ Programmable I/O Register (P_IO)
PARAMETRIC INFORMATION
- DC Electrical Parameters
- AC Electrical Parameters
- Package Mechanical Drawings
- Revision History

Distinguishing Features

Single-chip composite/S-Video
NTSC/PAL/SECAM to YCrCb digitizer

On-chip Ultralock

Square pixel and CCIR601 resolution for:

NTSC (M)
NTSC (M) without 7.5IRE pedestal
PAL (B, D, G, H, I, M, N, N

combination)

SECAM

Chroma comb filter

Arbitrary horizontal and 5-tap vertical
filtered scaling

Hardware closed-caption decoder

Vertical Blanking Interval (VBI) data
pass-through

Arbitrary temporal decimation for a
reduced frame-rate video sequence

Programmable hue, brightness, saturation,
and contrast

User-programmable cropping of the video
window

2x oversampling to simplify external
analog filtering

Two-wire Inter-Integrated Circuit (I

bus interface

8- or 16-bit pixel interface

YCrCb (4:2:2) output format

Software selectable four-input analog
MUX

4 fully programmable GPIO bits

Auto NTSC/PAL format detect

Automatic Gain Control (AGC)

Typical power consumption 0.85 W

IEEE 1149.1 Joint Test Action Group
(JTAG) interface

100-Pin PQFP and TQFP packages

Related Products

Bt819A, Bt829, Bt856/857, Bt864/865,
Bt866/867, Bt852

Applications

Multimedia

Image processing

Desktop video

Video phone

Teleconferencing

Interactive video

ADC

UltralockTM

and

Clock

MUX0

MUX1

MUXOUT

SYNCDET

REFOUT

YREF+

YIN

Decimation LPF

Output

Luma-Chroma

Separation

and

Chroma

Output

Video

YREF

Output F

r
matting

Analog

MUX

ADC

CREF+

CIN

CREF

AGC

Timing

Control

Data

JTAG

Demodulation

Spatial and

Temporal

Scaling

Video

Timing

Unit

Generation

XT0

XT1

40 MHz

MUX2

Advance Information

This document contains information on a product under development. The para-
metric information contains target parameters that are subject to change.

MUX3

VideoStream

II Decoders

Bt829A/827A

Bt829A

Video Capture Processor & Scaler for
TV/VCR Analog Input

Bt827A

Composite Video and S-Video Decoder

The Bt829A and Bt827A VideoStreamTM Decoders are a family of single-chip, pin-
and register-compatible, composite NTSC/PAL/SECAM video and S-Video decod-
ers. They are also pin and register backward compatible with the Bt829/827 family
of products. Low operating power consumption and power-down capability make
them ideal low-cost solutions for PC video capture applications on both desktop and
portable system platforms. They support square pixel and CCIR601 resolutions for
NTSC, PAL and SECAM video. They have a flexible pixel port which supports a
variety of system interface configurations, and they are offered in 100-pin PQFP and
100-pin TQFP packages.

Functional Block Diagram

Rockwell reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Rockwell Semiconductor Systems is believed to be accurate and reliable. However, no
responsibility is assumed by Rockwell Semiconductor Systems for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of
Rockwell Semiconductor Systems.

Rockwell products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Rockwell product can reasonably be expected to result in personal injury or death. Rockwell customers using or selling Rockwell
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell for any damages resulting from
such improper use or sale.

Bt is a registered trademark of Rockwell Semiconductor Systems. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.

Specifications are subject to change without notice.

PRINTED IN THE UNITED STATES OF AMERICA

Ordering Information

Model Number

Package

Ambient Temperature Range

Bt829AKRF

100-pin PQFP

0°C to +70°C

Bt827AKRF

100-pin PQFP

0°C to +70°C

Bt829AKTF

100-pin TQFP

0°C to +70°C

iii

L829A_B

ABLE

ONTENTS

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Bt829A Video Capture Processor for TV/VCR Analog Input. . . . . . . . . . . . . . . . . . . . 3

Bt827A Composite/S-Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Bt829A Architecture and Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

UltraLock

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

VBI Data Pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Closed Caption Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Differences Between Bt829/827 and Bt829A/827A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

UltraLockTM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operation Principles of UltraLockTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Composite Video Input Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Y/C Separation and Chroma Demodulation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Video Scaling, Cropping, and Temporal Decimation

. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Horizontal and Vertical Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Cropping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

L829A_B

Bt829A/827A

VideoStream II Decoders

ABLE

ONTENTS

Video Adjustments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

The Hue Adjust Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

The Contrast Adjust Register (CONTRAST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

The Saturation Adjust Registers (SAT_U, SAT_V) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

The Brightness Register (BRIGHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Bt829A VBI Data Output Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

VBI Line Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

VBI Frame Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Closed Captioning and Extended Data Services Decoding

. . . . . . . . . . . . . . . . . . . . 39

Automatic Chrominance Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Low Color Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Coring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Electrical Interfaces

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Input Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Autodetection of NTSC or PAL/SECAM Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Power-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Automatic Gain Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2X Oversampling and Input Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Output Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Output Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

YCrCb Pixel Stream Format, SPI Mode 8- and 16-bit Formats. . . . . . . . . . . . . . . . . 51

Synchronous Pixel Interface (SPI, Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Synchronous Pixel Interface (SPI, Mode 2, ByteStreamTM) . . . . . . . . . . . . . . . . . . . 54

CCIR601 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

C Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Starting and Stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Addressing the Bt829A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Reading and Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

L829A_B

ABLE

ONTENTS

Bt829A/827A

VideoStream II Decoders

JTAG Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Example BSDL Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PC Board Layout Considerations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Latch-up Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Sample Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

L829A_B

Bt829A/827A

VideoStream II Decoders

ABLE

ONTENTS

Control

Register Definitions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

0x00 -- Device Status Register (STATUS)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

0x01 -- Input Format Register (IFORM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

0x02 -- Temporal Decimation Register (TDEC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

0x03 -- MSB Cropping Register (CROP)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

0x04 -- Vertical Delay Register, Lower Byte (VDELAY_LO)

. . . . . . . . . . . . . . . . . . . . . 84

0x05 -- Vertical Active Register, Lower Byte (VACTIVE_LO)

. . . . . . . . . . . . . . . . . . . 85

0x06 -- Horizontal Delay Register, Lower Byte (HDELAY_LO)

. . . . . . . . . . . . . . . . . . 86

0x07 -- Horizontal Active Register, Lower Byte (HACTIVE_LO)

. . . . . . . . . . . . . . . . 87

0x08 -- Horizontal Scaling Register, Upper Byte (HSCALE_HI)

. . . . . . . . . . . . . . . . . 88

0x09 -- Horizontal Scaling Register, Lower Byte (HSCALE_LO)

. . . . . . . . . . . . . . . . 89

0x0A -- Brightness Control Register (BRIGHT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

0x0B -- Miscellaneous Control Register (CONTROL)

. . . . . . . . . . . . . . . . . . . . . . . . . 91

0x0C -- Luma Gain Register, Lower Byte (CONTRAST_LO)

. . . . . . . . . . . . . . . . . . . . 92

0x0D -- Chroma (U) Gain Register, Lower Byte (SAT_U_LO)

. . . . . . . . . . . . . . . . . . . 93

0x0E -- Chroma (V) Gain Register, Lower Byte (SAT_V_LO)

. . . . . . . . . . . . . . . . . . . 94

0x0F -- Hue Control Register (HUE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

0x10 -- SC Loop Control (SCLOOP)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

0x11 -- White Crush Up Count Register (WC_UP)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

0x12 -- Output Format Register (OFORM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

0x13 -- Vertical Scaling Register, Upper Byte (VSCALE_HI)

. . . . . . . . . . . . . . . . . . 101

0x14 -- Vertical Scaling Register, Lower Byte (VSCALE_LO)

. . . . . . . . . . . . . . . . . . 102

0x15 -- Test Control Register (TEST)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

0x16 -- Video Timing Polarity Register (VPOLE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

0x17 -- ID Code Register (IDCODE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

0x18 -- AGC Delay Register (ADELAY)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

0x19 -- Burst Delay Register (BDELAY)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

0x1A -- ADC Interface Register (ADC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

0x1B -- Video Timing Control (VTC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

0x1C -- Extended Data Service/Closed Caption Status Register (CC_STATUS)

. 111

0x1D -- Extended Data Service/Closed Caption Data Register (CC_DATA)

. . . . . 113

0x1E -- White Crush Down Count Register (WC_DN)

. . . . . . . . . . . . . . . . . . . . . . . . 114

0x1F -- Software Reset Register (SRESET)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

0x3F -- Programmable I/O Register (P_IO)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

viii

L829A_B

Bt829A/827A

VideoStream II Decoders

IST

IGURES

List of Figures

Figure 1.

Bt829A/827A Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2.

Bt829A/7A Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

UltraLockTM Behavior for NTSC Square Pixel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4.

Y/C Separation and Chroma Demodulation for Composite Video . . . . . . . . . . . . . . . . . . 16

Figure 5.

Y/C Separation Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6.

Filtering and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7.

Optional Horizontal Luma Low-Pass Filter Responses. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8.

Combined Luma Notch, 2x Oversampling and
Optional Low-Pass Filter Response (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.

Combined Luma Notch, 2x Oversampling and
Optional Low-Pass Filter Response (PAL/SECAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . 20

Figure 11. Combined Luma Notch and 2x Oversampling Filter Response . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Peaking Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch. . . . . . . . . . . . . . . . . 22

Figure 14. Effect of the Cropping and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15. Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 16. Regions of the Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 17. Bt829A YCrCb 4:2:2 Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. Bt829A VBI Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 19. VBI Line Output Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. VBI Sample Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 21. Location of VBI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 22. VBI Sample Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 23. CC/EDS Data Processing Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 24. CC/EDS Incoming Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 25. Closed Captioning/Extended Data Services FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 26. Coring Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 27. Bt829A Typical External Circuitry for Backward Compatibility with Bt829/827 . . . . . . . . . 45

Figure 28. Bt829A Typical External Circuitry (Reduced Passive Components). . . . . . . . . . . . . . . . . 46

Figure 29. Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 30. Luma and Chroma 2x Oversampling Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 31. Output Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 32. YCrCb 4:2:2 Pixel Stream Format (SPI Mode, 8 and 16 Bits) . . . . . . . . . . . . . . . . . . . . . 52

Figure 33. Bt829A/827A Synchronous Pixel Interface, Mode 1 (SPI-1). . . . . . . . . . . . . . . . . . . . . . . 53

Figure 34. Basic Timing Relationships for SPI Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 35. Data Output in SPI Mode 2 (ByteStreamTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

L829A_B

IST

IGURES

Bt829A/827A

VideoStream II Decoders

Figure 36. Video Timing in SPI Modes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 37. Horizontal Timing Signals in the SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 38. The Relationship between SCL and SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 39. I

C Slave Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 40. I

C Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 41. Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 42. Example Ground Plane Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 43. Optional Regulator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 44. Typical Power and Ground Connection Diagram and Parts List . . . . . . . . . . . . . . . . . . . 69

Figure 45. Bt829/Cirrus Logic 544x VGA Interface Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 46a.Bt829/S3 Virge 8-Bit Interface Schematic - Video Input Detail . . . . . . . . . . . . . . . . . . . . 72

Figure 46b.Bt829/S3 Virge 8-Bit Interface Schematic - Bt829 Detail . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 47a.Bt829/Trident VGA Interface Schematic - TV Tuner and Video Input Detail . . . . . . . . . . 74

Figure 47b.Bt829/Trident VGA Interface Schematic - Bt829 Detail . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 47c.Bt829/Trident VGA Interface Schematic - Feature Connector Detail . . . . . . . . . . . . . . . . 76

Figure 48. Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 49. Output Enable Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 50. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 51. 100-pin TQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

L829A_B

Bt829A/827A

VideoStream II Decoders

IST

ABLES

List of Tables

Table 1.

VideoStreamTM II Features Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 2.

Pin Descriptions Grouped By Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3.

Register Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.

Video Input Formats Supported by the Bt829A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5.

Table 6.

Scaling Ratios for Popular Formats Using Frequency Values . . . . . . . . . . . . . . . . . . . . . . 24

Table 7.

Pixel/Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 8.

Description of the Control Codes in the Pixel Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 9.

Data Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 10. Bt829A Address Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 11. Example I

C Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 12. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 13. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 14. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 17. Clock Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 18. Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 19. Output Enable Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 20. JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 21. Decoder Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 22. Bt829A Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

UNCTIONAL

ESCRIPTION

Functional Overview

L829A_B

Bt829A/827A

VideoStream II Decoders

Bt829A

Video Capture

Processor for TV/VCR

Analog Input

The Bt829A Video Capture Processor is a fully integrated single-chip decoding
and scaling solution for analog NTSC/PAL/SECAM input signals from TV tuners,
VCRs, cameras, and other sources of composite or Y/C video. It is the second gen-
eration front-end input solution for low-cost PC video/graphics systems that deliv-
er complete integration and high-performance video synchronization, Y/C
separation, and filtered scaling. The Bt829A has all the mixed signal and DSP cir-
cuitry required to convert an analog composite waveform into a scaled digital vid-
eo stream, supporting a variety of video formats, resolutions, and frame rates.

Bt827A

Composite/S-Video

Decoder

The Bt827A provides full composite and S-Video capability along with filtered
horizontal scaling. Vertical scaling can only be implemented by line-dropping.

The Synchronous Pixel Interface (SPI) is common to both pin-compatible de-

vices, which enables implementation of a single system hardware design. Similar-
ly, a common I

C register set allows a single piece of driver code to be written for

software control of both options. Table 1 compares Bt829A and Bt827A features.

Bt829A Architecture and

Partitioning

The Bt829A has been developed to provide the most cost-effective, high-quality
video input solution for low-cost multimedia subsystems that integrate both graph-
ics display and video capabilities. The feature set of the Bt829A supports a vid-
eo/graphics system partitioning which optimizes the total cost of a system
configured both with and without video capture capabilities. This enables system
vendors to easily offer products with various levels of video support using a single
base-system design.

As graphics chip vendors move from graphics-only to video/graphics coproces-

sors and eventually to single-chip video/graphics processor implementations, the
ability to efficiently use silicon and package pins to support both graphics acceler-
ation, video playback acceleration, and video capture becomes critical. This prob-
lem becomes more acute as the race towards higher performance graphics requires
more and more package pins to be consumed for wide 64-bit memory interfaces
and glueless local bus interfaces.

Table 1. VideoStreamTM II Features Options

Feature Options

Bt829A

Bt827A

Composite Video Decoding

S-Video Decoding

SECAM Video

Hardware Closed Caption Decode

Filtered Vertical Scaling

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Functional Overview

L829A_B

The Bt829A minimizes the cost of video capture function integration in two

ways. First, recognizing that YCrCb to RGB color space conversion is a required
feature of multimedia controllers for acceleration of digital video playback, the
Bt829A avoids redundant functionality and allows the downstream controller to
perform this task. Second, the Bt829A can minimize the number of interface pins
required by a downstream multimedia controller in order to keep package costs to
a minimum.

Controller systems designed to take advantage of these features allow video

capture capability to be added to the base system in a modular fashion using only
a single Integrated Circuit (IC).

The Bt827A is targeted at system configurations using video processors which

typically integrate the scaling function.

UltraLock

The Bt829A and Bt827A employ a proprietary technique known as UltraLockTM to
lock to the incoming analog video signal. It will always generate the required num-
ber of pixels per line from an analog source in which the line length can vary by as
much as a few microseconds. UltraLockTM's digital locking circuitry enables the
VideoStreamTM decoders to quickly and accurately lock on to video signals, re-
gardless of their source. Since the technique is completely digital, UltraLockTM
can recognize unstable signals caused by VCR headswitches or any other deviation
and adapt the locking mechanism to accommodate the source. UltraLockTM uses
nonlinear techniques which are difficult, if not impossible, to implement in gen-
lock systems. And unlike linear techniques, it adapts the locking mechanism auto-
matically.

Scaling and Cropping

The Bt829A can reduce the video image size in both horizontal and vertical direc-
tions independently using arbitrarily selected scaling ratios. The X and Y dimen-
sions can be scaled down to one-sixteenth of the full resolution. Horizontal scaling
is implemented with a 6-tap interpolation filter, while up to 5-tap interpolation is
used for vertical scaling with a line store. The Bt827A supports vertical scaling by
line-dropping.

The video image can be arbitrarily cropped by programming the ACTIVE flag

to reduce the number of active scan lines and active horizontal pixels per line.

The Bt829A and Bt827A also support a temporal decimation feature that reduc-

es video bandwidth by allowing frames or fields to be dropped from a video se-
quence at regular but arbitrarily selected intervals.

Input Interface

Analog video signals are input to the Bt829A/827A via a four-input multiplexer
that can select between four composite source inputs or between three composite
and a single S-Video input source. When an S-Video source is input to the Bt829A,
the luma component is fed through the input analog multiplexer, and the chroma
component is fed directly into the C input pin. An AGC circuit enables the
Bt829A/827A to compensate for reduced amplitude in the analog signal input.

UNCTIONAL

ESCRIPTION

Functional Overview

L829A_B

Bt829A/827A

VideoStream II Decoders

The clock signal interface consists of two pairs of pins for crystal connection

and two clock output pins. One pair of crystal pins is for connection to a
28.64 MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The other
is for PAL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either of the two crys-
tal frequencies can be selected to generate CLKx1 and CLKx2 output signals.
CLKx2 operates at the full crystal frequency (8*Fsc) whereas CLKx1 operates at
half the crystal frequency (4*Fsc). Either fundamental or third harmonic crystals
may be used. Alternatively, CMOS oscillators may be used.

Output Interface

The Bt829A and Bt827A support a Synchronous Pixel Interface (SPI) mode.

The SPI supports a YCrCb 4:2:2 data stream over an 8- or 16-bit-wide path.

When the pixel output port is configured to operate 8 bits wide, 8 bits of chromi-
nance data are output on the first clock cycle followed by 8 bits of luminance data
on the next clock cycle for each pixel. Two clocks are required to output one pixel
in this mode, thus a 2x clock is used to output the data.

The Bt829A/827A outputs all horizontal and vertical blanking pixels in addi-

tion to the active pixels synchronous with CLKX1 (16-bit mode) or CLKX2 (8-bit
mode). It is also possible to insert control codes into the pixel stream using chromi-
nance and luminance values that are outside the allowable chroma and luma rang-
es. These control codes can be used to flag video events such as ACTIVE,
HRESET, and VRESET. Decoding these video events downstream enables the vid-
eo controller to eliminate pins required for the corresponding video control sig-
nals.

VBI Data Pass-through

The Bt829A/827A provides VBI data passthrough capability. The VBI region an-
cillary data is captured by the video decoder and made available to the system for
subsequent software processing. The Bt829A/827A may operate in a VBI Line
Output mode, in which the VBI data is only made available during select lines.
This mode of operation is intended to enable capture of VBI lines containing an-
cillary data as well as processing normal YCrCb video image data. In addition, the
Bt829A/827A supports a VBI Frame Output mode, in which every line in the video
signal is treated as if it was a vertical interval line and no image data is output. This
mode of operation is designed for use in still-frame capture/processing applica-
tions.

Closed Caption

Decoding

The Bt829A and Bt827A provide a Closed Captioning (CC) and Extended Data
Services (EDS) decoder. Data presented to the video decoder on the CC and EDS
lines is decoded and made available to the system through the CC_DATA and
CCSTATUS registers.

C Interface

The Bt829A/827A registers are accessed via a two-wire I

C interface. The

Bt829A/827A operates as a slave device. Serial clock and data lines, SCL and
SDA, transfer data from the bus master at a rate of 100 Kbits/s. Chip select and re-
set signals are also available to select one of two possible Bt829A/827A devices in
the same system and to set the registers to their default values.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Pin Descriptions

L829A_B

Pin Descriptions

Figure 2 details the Bt829A and Bt827A pinout. Table 2 provides pin numbers, names, input and output functions,
and descriptions.

Figure 2. Bt829A/7A Pinout

100

NUMXTAL

VRESET

FIELD

GND

VDD

AGND

CLEVEL

CREF

VAA

AGND

N/C

CIN

AGND

VAA

CREF+

N/C

YREF

AGND

VAA

SYNCDET

AGND

MUX[1]

AGND

MUX[0]

AGND

MUXOUT

YIN

N/C

GND

CLKx2

CLKx1

VDD

GND

QCLK

PWRDN

CBFLAG

CCVALID

VACTIVE

OEPOLE

DVALID

ACTIVE

HRESET

GND

TDO

GND

TCK

TRST

TMS

TDI

VDD

GND

VPOS

AGCCAP

VNEG

REFOUT

VAA

MUX[2]

N/C

AGND

VAA

YREF+

MUX[3]

VDD

VD[15]

VD[14]

VD[13]

VD[12]

VD[11]

VD[10]

VD[9]

VD[8]

VDD

GND

VD[7]

VD[6]

VD[5]

VD[4]

VD[3]

VD[2]

VD[1]

VD[0]

VDD

GND

XT0I

XT0O

RST

XT1I

XT1O

SDA

SCL

I2CCS

VDD

GND

VDD

GND

VDD

Bt829A/827A

UNCTIONAL

ESCRIPTION

Pin Descriptions

L829A_B

Bt829A/827A

VideoStream II Decoders

Table 2. Pin Descriptions Grouped By Pin Function

(1 of 4)

Pin #

I/O

Pin Name

Description

Input Stage Pins

45, 50, 55,
57

MUX[3:0]

Analog composite video inputs to the on-chip input multiplexer. They are used to
select between four composite sources or three composite and one

S-Video

source.

Unused pins should be connected to GND.

MUXOUT

The analog video output of the 4-to-1 multiplexer. Connected to the YIN pin.

YIN

The analog composite or luma input to the Y-ADC.

CIN

The analog chroma input to the C-ADC.

SYNCDET

The sync stripper input generates timing information for the AGC circuit. Can be
optionally connected through a 0.1

F capacitor to the same source as the Y-ADC, to

maintain compatibility with Bt829 board layouts. A 1 M

bleeder resistor can be con-

nected to ground, to maintain compatibility with Bt829 board layouts. For new
Bt829A designs, this pin may be connected to VAA.

AGCCAP

The AGC time constant control capacitor node. Must be connected to a 0.1

capacitor to ground.

REFOUT

Output of the AGC which drives the YREF+ and CREF+ pins.

YREF+

The top of the reference ladder of the Y-ADC. This should be connected to REFOUT.

YREF

The bottom of the reference ladder of the Y-ADC. This should be connected to ana-
log ground (AGND).

CREF+

The top of the reference ladder of the C-ADC. This should be connected to REFOUT.

CREF

The bottom of the reference ladder of the C-ADC. This should be connected to ana-
log ground (AGND).

CLEVEL

An input to provide the DC level reference for the C-ADC. For compatibility with
Bt829 board layouts, the 30 k

divider resistors may be maintained.

Note: This pin should be left to float for new Bt829A designs.

N/C

No connect.

N/C

No connect.

63, 68

N/C

No connect.

N/C

No connect.

N/C

No connect.

C Interface Pins

SCL

The I

C Serial Clock Line.

I/O

SDA

The I

C Serial Data Line.

I2CCS

The I

C Chip Select Input (TTL compatible). This pin selects one of two Bt829A

devices in the same system. This pin is internally pulled to ground with an effective
18 K

resistance.

RST

Reset Control Input (TTL compatible). A logical zero for a minimum of four consecu-
tive clock cycles resets the device to its default state. A logical zero for less than
eight XTAL cycles will leave the device in an undetermined state.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Pin Descriptions

L829A_B

Video Timing Unit Pins

HRESET

Horizontal Reset Output (TTL compatible). This signal indicates the beginning of a
new line of video. This signal is 64 CLKx1 clock cycles wide. The falling edge of this
output indicates the beginning of a new scan line of video. This pin may be defined in
pixels as opposed to CLKx1 cycles. Refer to the HSFMT bit in the VTC register.

Note: The polarity of this pin is programmable through the VPOLE register.

VRESET

Vertical Reset Output (TTL compatible). This signal indicates the beginning of a new
field of video. This signal is output coincident with the rising edge of CLKx1, and is
normally six lines wide. The falling edge of VRESET indicates the beginning of a new
field of video.

Note: The polarity of this pin is programmable through the VPOLE register.

ACTIVE

Active Video Output (TTL compatible). This pin can be programmed to output the
composite active or horizontal active signal via the VTC register. It is a logical high
during the active/viewable periods of the video stream. The active region of the video
stream is programmable.

Note: The polarity of this pin is programmable through the VPOLE register.

QCLK

Qualified Clock Output. This pin provides a rising edge only during valid, active pixel
data. This output is generated from CLKx1 (or CLKx2 in 8-bit mode), DVALID and, if
programmed, ACTIVE. The phase of QCLK is inverted from the CLKx1 (or CLKx2) to
ensure adequate setup and hold time with respect to the data outputs. QCLK is not
output during control codes when using SPI mode 2.

Output Enable Control (TTL compatible). All video timing unit output pins and all
clock interface output pins contain valid data following the rising edge of CLKx2, after
OE has been asserted low. This function is asynchronous. The three-stated pins
include: VD[15:0], HRESET, VRESET, ACTIVE, DVALID, CBFLAG, FIELD, QCLK,
CLKx1, and CLKx2. See the OES bits in the OFORM register to disable subgroups
of output pins.

FIELD

Odd/Even Field Output (TTL compatible). A high state on the FIELD pin indicates
that an odd field is being digitized.

Note: The polarity of this pin is programmable through the VPOLE register.

CBFLAG

Cb Data Identifier (TTL compatible). A high state on this pin indicates that the current
chroma byte contains Cb chroma information.

Note: The polarity of this pin is programmable through the VPOLE register.

VD[15:8]

Digitized Video Data Outputs (TTL compatible). VD[0] is the least significant bit of the
bus in 16-bit mode. VD[8] is the least significant bit of the bus in 8-bit mode. The
information is output with respect to CLKx1 in 16-bit mode, and CLKx2 in 8-bit mode.
In mode 2, this port is configured to output control codes as well as data. When data
is output in 8-bit mode using VD[15:8], VD[7:0] can be used as general purpose I/O
pins. See the P_IO register.

2229

I/O

VD[7:0]

DVALID

Data Valid Output (TTL compatible). This pin indicates when a valid pixel is being
output onto the data bus. The Bt829A digitizes video at eight times the subcarrier
rate, and outputs scaled video. Therefore, there are more clocks than valid data.
DVALID indicates when valid pixel data is being output.

Note: The polarity of this pin is programmable through the VPOLE register.

Table 2. Pin Descriptions Grouped By Pin Function

(2 of 4)

Pin #

I/O

Pin Name

Description

UNCTIONAL

ESCRIPTION

Pin Descriptions

L829A_B

Bt829A/827A

VideoStream II Decoders

CCVALID

A logical low on this pin indicates that the CC FIFO is half full (8 characters). This pin
may be disabled. This open drain output

requires a pullup resistor for proper opera-

tion. However, if closed captioning is not implemented, this pin may be left uncon-
nected.

PWRDN

A logical high on this pin puts the device into power-down mode. This is equivalent to
programming CLK_SLEEP high in the ADC register.

VACTIVE

Vertical Blanking Output (TTL compatible). The falling edge of VACTIVE indicates
the beginning of the active video lines in a field. This occurs VDELAY/2 lines after the
rising edge of VRESET. The rising edge of VACTIVE indicates the end of active video
lines and occurs ACTIVE_LINES/2 lines after the falling edge of VACTIVE. VACTIVE
is output following the rising edge of CLKx1.

Note: The polarity of the pin is programmable through the VPOLE register.

OEPOLE

A logical low on this pin allows the Bt829A/827A to power up in the same manner as
the Bt829/827. A logical high on this pin, followed by a device reset will TRISTATE
the video outputs, sync outputs and clock outputs.

Clock Interface Pins

XT0I

Clock Zero pins. A 28.64 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT0I.
CMOS level inputs must be used. This clock source is selected for NTSC input
sources. When the chip is configured to decode PAL but not NTSC (and therefore
only one clock source is needed), the 35.47 MHz source is connected to this port
(XT0).

XT0O

XT1I

Clock One pins. A 35.47 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT1I.
CMOS level inputs must be used. This clock source is selected for PAL input
sources. If only NTSC or PAL is being decoded, and therefore only XT0I and XT0O
are connected to a crystal, XT1I should be tied either high or low, and XT1O

must be

left floating.

XT1O

CLKx1

1x clock output (TTL compatible). The frequency of this clock is 4*Fsc (14.31818
MHz for NTSC or 17.73447 MHz for PAL).

CLKx2

2x clock output (TTL compatible). The frequency of this clock is 8*Fsc (28.63636
MHz for NTSC, or 35.46895 MHz for PAL).

NUMXTAL

Crystal Format Pin. This pin is set to indicate whether one or two crystals are present
so that the Bt829A can select XT1 or XT0 as the default in auto format mode. A logi-
cal zero on this pin indicates one crystal is present. A logical one indicates two crys-
tals are present. This pin is internally pulled down to ground with an effective 18 K

resistance.

Table 2. Pin Descriptions Grouped By Pin Function

(3 of 4)

Pin #

I/O

Pin Name

Description

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Pin Descriptions

L829A_B

JTAG Pins

TCK

Test Clock (TTL compatible). Used to synchronize all JTAG test structures. When
JTAG operations are not being performed, this pin must be driven to a logical low.

TMS

Test Mode Select (TTL compatible). JTAG input pin whose transitions drive the JTAG
state machine through its sequences. When JTAG operations are not being per-
formed, this pin must be left floating or tied high.

TDI

Test Data Input (TTL compatible). JTAG pin used for loading instruction into the TAP
controller or for loading test vector data for boundary-scan operation. When JTAG
operations are not being performed, this pin must be left floating or tied high.

TDO

Test Data Output (TTL compatible). JTAG pin used for verifying test results of all
JTAG sampling operations. This output pin is active for certain JTAG operations and
will be three-stated at all other times.

TRST

Test Reset (TTL compatible). JTAG pin used to initialize the JTAG controller. This pin
is tied low for normal device operation. When pulled high, the JTAG controller is
ready for device testing.

Power And Ground Pins

1, 10, 20,
30, 38, 76,
88, 92, 96

VDD +5 V

Power supply for digital circuitry. All VDD pins must be connected together as close
to the device as possible. A 0.1

F ceramic capacitor should be connected between

each group of VDD pins and the ground plane as close to the device as possible.

40, 44, 48,
60, 65, 72

VAA +5 V,
VPOS +5
V

Power supply for analog circuitry. All VAA pins and VPOS must be connected
together as close to the device as possible. A 0.1

F ceramic capacitor should be

connected between each group of VAA pins and the ground plane as close to the
device as possible.

11, 21, 31,
33, 39, 77,
81, 90, 93,
95, 100

GND

Ground for digital circuitry. All GND pins must be connected together as close to the
device as possible.

42, 47, 54,
56, 58, 61,
66, 71, 75

AGND,
VNEG

Ground for analog circuitry. All AGND pins and VNEG must be connected together
as close to the device as possible.

I/O Column Legend:

I = Digital Input
O = Digital Output
I/O = Digital Bidirectional
A = Analog
G = Ground
P = Power

Table 2. Pin Descriptions Grouped By Pin Function (4 of 4)

Pin #

I/O

Pin Name

Description

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

UltraLockTM

L829A_B

UltraLockTM

The Challenge

The line length (the interval between the midpoints of the falling edges of succeed-
ing horizontal sync pulses) of analog video sources is not constant. For a stable
source such as a studio grade video source or test signal generators, this variation
is very small:

2 ns. However, for an unstable source such as a VCR, laser disk

player, or TV tuner, line length variation is as much as a few microseconds.

Digital display systems require a fixed number of pixels per line, despite these

variations. The Bt829A employs a technique known as UltraLockTM to implement
locking to the horizontal sync and the subcarrier of the incoming analog video sig-
nal and generating the required number of pixels per line.

Operation Principles of

UltraLockTM

UltraLockTM is based on sampling, using a fixed-frequency stable clock. Because
the video line length will vary, the number of samples generated using a fixed-fre-
quency sample clock will also vary from line to line. If the number of generated
samples per line is always greater than the number of samples per line required by
the particular video format, the number of acquired samples can be reduced to fit
the required number of pixels per line.

The Bt829A requires an 8*Fsc (28.64 MHz for NTSC and 35.47 MHz for PAL)

crystal or oscillator input signal source. The 8*Fsc clock signal, or CLKx2, is di-
vided down to CLKx1 internally (14.32 MHz for NTSC and 17.73 MHz for PAL).
Both CLKx2 and CLKx1 are made available to the system. UltraLockTM operates
at CLKx1 although the input waveform is sampled at CLKx2 then low-pass filtered
and decimated to CLKx1 sample rate.

At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels

for PAL/SECAM within a nominal line time interval (63.5

s for NTSC and 64

for PAL/SECAM). For square pixel NTSC and PAL/SECAM formats there should
only be 780 and 944 pixels per video line, respectively. This is because the square
pixel clock rates are slower than a 4*Fsc clock rate: for example, 12.27 MHz for
NTSC and 14.75 MHz for PAL.

UltraLockTM accommodates line length variations from nominal in the incom-

ing video by always acquiring more samples (at an effective 4*Fsc rate) than are
required by the particular video format. It then outputs the correct number of pixels
per line. UltraLockTM then interpolates the required number of pixels so that it
maintains the stability of the original image, despite variation in the line length of
the incoming analog waveform.

The example illustrated in Figure 3 shows three successive lines of video being

decoded for square pixel NTSC output. The first line is shorter than the nominal
NTSC line time interval of 63.5

s. On this first line, a line time of 63.2

s sampled

at 4*Fsc (14.32 MHz) generates only 905 pixels. The second line matches the
nominal line time of 63.5

s and provides the expected 910 pixels. Finally, the

third line is too long at 63.8

s within which 913 pixels are generated. In all three

cases, UltraLockTM outputs only 780 pixels.

UNCTIONAL

ESCRIPTION

UltraLockTM

L829A_B

Bt829A/827A

VideoStream II Decoders

UltraLockTM can be used to extract any programmable number of pixels from

the original video stream as long as the sum of the nominal pixel line length (910
for NTSC and 1,135 for PAL/SECAM) and the worst case line length variation
from nominal in the active region is greater than or equal to the required number of
output pixels per line, i.e.,

NOTE:

For stable inputs, UltraLockTM guarantees the time between the falling
edges of HRESET only to within one pixel. UltraLockTM does, however,
guarantee the number of active pixels in a line as long as the above rela-
tionship holds.

Figure 3. UltraLockTM Behavior for NTSC Square Pixel Output

Analog

Waveform

63.2

63.5

63.8

905 pixels

910 pixels

913 pixels

Line

Length

Pixels

Per Line

780 pixels

Pixels

Sent to

the FIFO

UltraLockTM

Nom

Var

Desired

where:

Nom

= Nominal number of pixels per line at 4*Fsc sample rate

(910 for NTSC, 1,135 for PAL/SECAM)

Var

= Variation of pixel count from nominal at 4*Fsc (can be a

positive or negative number)

Desired

= Desired number of output pixels per line

UNCTIONAL

ESCRIPTION

Y/C Separation and Chroma Demodulation

L829A_B

Bt829A/827A

VideoStream II Decoders

Figure 6 schematically describes the filtering and scaling operations.
In addition to the Y/C separation and chroma demodulation illustrated in

Figure 4, the Bt829A also supports chrominance comb filtering as an optional fil-
tering stage after chroma demodulation. The chroma demodulation generates
baseband I and Q (NTSC) or U and V (PAL/SECAM) color difference signals.

For S-Video operation, the digitized luma data bypasses the Y/C separation

block completely, and the digitized chrominance is passed directly to the chroma
demodulator.

For monochrome operation, the Y/C separation block is also bypassed, and the

saturation registers (SAT_U and SAT_V) are set to zero.

Figure 6. Filtering and Scaling

Note: Z1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. The coefficients

are determined by UltraLockTM and the scaling algorithm.

Chrominance

1
2

---

1
2

--- Z

Luminance

Vertical Scaler

Luminance

Chrominance

Horizontal Scaler

6-Tap, 32-Phase

Interpolation

On-chip Memory

and

Horizontal

Scaling

2-Tap, 32-Phase

Interpolation

On-chip Memory

and

Horizontal

Scaling

Chroma Comb

Low-Pass

Filter

Optional

Horizontal

Vertical Scaling

Luma Comb

(Chroma Comb)

3 MHz

1
4

--- 1

(

)

1
8

--- 1

(

)

------ 1

(

)

Vertical Filter Options

Vertical Scaling

Vertical Filtering

Luminance

1
2

--- 1

(

)

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Video Scaling, Cropping, and Temporal Decimation

The Bt829A provides three mechanisms to reduce the amount of video pixel data
in its output stream: down-scaling, cropping, and temporal decimation. All three
can be controlled independently.

Horizontal and Vertical

Scaling

The Bt829A provides independent and arbitrary horizontal and vertical down-scal-
ing. The maximum scaling ratio is 16:1 in both X and Y dimensions. The maxi-
mum vertical scaling ratio is reduced from 16:1 when using frames to 8:1 when
using fields. The different methods utilized for scaling luminance and chromi-
nance are described in the following sections.

Luminance Scaling

The first stage in horizontal luminance scaling is an optional pre-filter which pro-
vides the capability to reduce anti-aliasing artifacts. It is generally desirable to lim-
it the bandwidth of the luminance spectrum prior to performing horizontal scaling
because the scaling of high-frequency components may create image artifacts in
the resized image. The optional low-pass filters shown in Figure 7 reduce the hor-
izontal high-frequency spectrum in the luminance signal. Figure 8 and Figure 9
show the combined results of the optional low-pass filters, and the luma notch and
2x oversampling filter.

Figure 7. Optional Horizontal Luma Low-Pass Filter Responses

NTSC

PAL/SECAM

ICON

QCIF

CIF

ICON

QCIF

CIF

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Bt829A/827A

VideoStream II Decoders

The Bt829A implements horizontal scaling through poly-phase interpolation.

The Bt829A uses 32 different phases to accurately interpolate the value of a pixel.
This provides an effective pixel jitter of less than 6 ns.

In simple pixel- and line-dropping algorithms, non-integer scaling ratios intro-

duce a step function in the video signal that effectively introduces high-frequency
spectral components. Poly-phase interpolation accurately interpolates to the cor-
rect pixel and line position providing more accurate information. This results in
more aesthetically pleasing video as well as higher compression ratios in band-
width limited applications.

For vertical scaling, the Bt829A uses a line store to implement four different fil-

tering options. The filter characteristics are shown in Figure 10. The Bt829A pro-
vides up to 5-tap filtering to ensure removal of aliasing artifacts. Figure 11 shows
the combined responses of the luma notch and 2x oversampling filters.

Figure 8. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC)

ICON

QCIF

CIF

ICON

QCIF

CIF

Pass Band

Full Spectrum

Figure 9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM)

ICON

QCIF

CIF

ICON

QCIF

CIF

Pass Band

Full Spectrum

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Bt829A/827A

VideoStream II Decoders

Chrominance Scaling

A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance.
Vertical scaling of chrominance is implemented through chrominance comb filter-
ing using a line store, followed by simple decimation or line dropping.

Scaling Registers

Horizontal Scaling Ratio Register (HSCALE)

HSCALE is programmed with the

horizontal scaling ratio. When outputting unscaled video (in NTSC), the Bt829A
will produce 910 pixels per line. This corresponds to the pixel rate at f

CLKx1

(4*Fsc). This register is the control for scaling the video to the desired size. For ex-
ample, square pixel NTSC requires 780 samples per line, while CCIR601 requires
858 samples per line. HSCALE_HI and HSCALE_LO are two 8-bit registers that,
when concatenated, form the 16-bit HSCALE register.

The method below uses pixel ratios to determine the scaling ratio. The follow-

ing formula should be used to determine the scaling ratio to be entered into the
16-bit register:

For example, to scale PAL/SECAM input to square pixel QCIF, the total number of
horizontal pixels is 236:

An alternative method for determining the HSCALE value uses the ratio of the
scaled active region to the unscaled active region as shown below:

In this equation, the HACTIVE value cannot be cropped; it represents the total ac-
tive region of the video line. This equation produces roughly the same result as us-
ing the full line length ratio shown in the first example. However, due to truncation,
the HSCALE values determined using the active pixel ratio will be slightly differ-
ent than those obtained using the total line length pixel ratio. The values in Table 6
were calculated using the full line length ratio.

NTSC:

HSCALE = [ ( 910/P

desired

) 1] * 4096

PAL/SECAM:

HSCALE = [ ( 1135/P

desired

) 1] * 4096

where:

desired

= Desired number of pixels per line of video, includ-

ing active, sync and blanking.

HSCALE = [ ( 1135/236 ) 1 ] * 4096

= 15602

= 0x3CF2

NTSC:

HSCALE = [ (754 / HACTIVE) 1] * 4096

PAL/SECAM:

HSCALE = [ (922 / HACTIVE) 1] * 4096

where:

HACTIVE = Desired number of pixels per line of video, not in-

cluding sync or blanking.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Vertical Scaling Ratio Register (VSCALE)

VSCALE is programmed with the ver-

tical scaling ratio. It defines the number of vertical lines output by the Bt829A. The
following formula should be used to determine the value to be entered into this
13-bit register. The loaded value is a two's-complement, negative value.

For example, to scale PAL/SECAM input to square pixel QCIF, the total number of
vertical lines for PAL square pixel is 156 (see Table 6).

Table 6. Scaling Ratios for Popular Formats Using Frequency Values

Scaling Ratio

Format

Total
Resolution
(including
sync and
blanking
interval)

Output
Resolution
(Active Pixels)

HSCALE
Register
Values

VSCALE Register Values

Use Both
Fields

Single
Field

Full Resolution
1:1

NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel

780 x 525
858 x 525
864 x 625
944 x 625

640 x 480
720 x 480
720 x 576
768 x 576

0x02AC
0x00F8
0x0504
0x033C

0x0000
0x0000
0x0000
0x0000

N/A
N/A
N/A
N/A

CIF
2:1

NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel

390 x 262
429 x 262
432 x 312
472 x 312

320 x 240
360 x 240
360 x 288
384 x 288

0x1555
0x11F0
0x1A09
0x1679

0x1E00
0x1E00
0x1E00
0x1E00

0x0000
0x0000
0x0000
0x0000

QCIF
4:1

NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel

195 x 131
214 x 131
216 x 156
236 x 156

160 x 120
180 x 120
180 x 144
192 x 144

0x3AAA
0x3409
0x4412
0x3CF2

0x1A00
0x1A00
0x1A00
0x1A00

0x1E00
0x1E00
0x1E00
0x1E00

ICON
8:1

NTSC SQ Pixel
NTSC CCIR601
PAL CCIR601
PAL SQ Pixel

97 x 65
107 x 65
108 x 78
118 x 78

80 x 60
90 x 60
90 x 72
96 x 72

0x861A
0x7813
0x9825
0x89E5

0x1200
0x1200
0x1200
0x1200

0x1A00
0x1A00
0x1A00
0x1A00

Notes: 1. PAL-MHSCALE and VSCALE register values should be the same for NTSC.

2. PAL-N combinationHSCALE register values should be the same as for CCIR resolution NTSC. VSCALE reg-

ister values should be the same as for CCIR resolution PAL.

3. SECAMHSCALE and VSCALE register values should be the same as for PAL.

VSCALE = ( 0x10000 { [ ( scaling_ratio ) 1] * 512 } ) & 0x1FFF

VSCALE = ( 0x10000 { [ ( 4/1 ) 1 ] * 512 } ) & 0x1FFF

= 0x1A00

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Bt829A/827A

VideoStream II Decoders

Note that only the 13 least significant bits of the VSCALE value are used. The

five LSBs of VSCALE_HI and the 8-bit VSCALE_LO register form the 13-bit VS-
CALE register. The three MSBs of VSCALE_HI are used to control other func-
tions. The user must take care not to alter the values of the three most significant
bits when writing a vertical scaling value. The following C-code fragment illus-
trates changing the vertical scaling value:

#define BYTE unsigned char

#define WORD unsigned int

#define VSCALE_HI 0x13

#define VSCALE_LO 0x14

BYTE ReadFromBt829A( BYTE regAddress );

void WriteToBt829A( BYTE regAddress, BYTE regValue );

void SetBt829AVScaling( WORD VSCALE )

{

BYTE oldVscaleMSByte, newVscaleMSByte;

/* get existing VscaleMSByte value from */

/* Bt829A VSCALE_HI register */

oldVscaleMSByte = ReadFromBt829A( VSCALE_HI );

/* create a new VscaleMSByte, preserving top 3 bits */

newVscaleMSByte = (oldVscaleMSByte & 0xE0) | (VSCALE >> 8);

/* send the new VscaleMSByte to the VSCALE_HI reg */

WriteToBt829A( VSCALE_HI, newVscaleMSByte );

/* send the new VscaleLSByte to the VSCALE_LO reg */

WriteToBt829A( VSCALE_LO, (BYTE) VSCALE );

}

If your target machine has sufficient memory to statically store the scaling val-

ues locally, the READ operation can be eliminated.

On vertical scaling (when scaling below CIF resolution) it may be useful to use

a single field as opposed to using both fields. Using a single field will ensure there
are no inter-field motion artifacts on the scaled output. When performing single
field scaling, the vertical scaling ratio will be twice as large as when scaling with
both fields. For example, CIF scaling from one field does not require any vertical
scaling, but when scaling from both fields, the scaling ratio is 50%. Also, the
non-interlaced bit should be reset when scaling from a single field (INT = 0 in the
VSCALE_HI register). Table 6 lists scaling ratios for various video formats, and
the register values required.

where:

= bitwise AND

= bitwise OR

= bit shift, MSB to LSB

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Cropping Registers

Horizontal Delay Register (HDELAY)

HDELAY is programmed with the delay

between the falling edge of HRESET and the rising edge of ACTIVE. The count is
programmed with respect to the scaled frequency clock. Note that HDELAY
should always be an even number.

Horizontal Active Register (HACTIVE)

HACTIVE is programmed with the actual

number of active pixels per line of video. This is equivalent to the number of scaled
pixels that the Bt829A should output on a line. For example, if this register con-
tained 90, and HSCALE was programmed to down-scale by 4:1, then 90 active
pixels would be output. The 90 pixels would be a 4:1 scaled image of the 360 pixels
(at CLKx1) starting at count HDELAY. HACTIVE is restricted in the following
manner:

HACTIVE + HDELAY

Total Number of Scaled Pixels.

For example, in the NTSC square pixel format, there is a total of 780 pixels, in-

cluding blanking, sync and active regions. Therefore:

HACTIVE + HDELAY

780.

When scaled by 2:1 for CIF, the total number of active pixels is 390. Therefore:

HACTIVE +HDELAY

390.

The HDELAY register is programmed with the number of scaled pixels be-

tween HRESET and the first active pixel. Because the front porch is defined as the
distance between the last active pixel and the next horizontal sync, the video line
can be considered in three components: HDELAY, HACTIVE and the front porch.
Figure 15 illustrates the video signal regions.

When cropping is not implemented, the number of clocks at the 4x sample rate

(the CLKx1 rate) in each of these regions is as follows:

Figure 15. Regions of the Video Signal

HDELAY

HACTIVE

Front

Porch

CLKx1

Front Porch

CLKx1

HDELAY

CLKx1

HACTIVE

CLKx1

Total

NTSC

135

754

910

PAL/SECAM

186

922

1135

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Bt829A/827A

VideoStream II Decoders

The value for HDELAY is calculated using the following formula:

HDELAY = [(CLKx1_HDELAY / CLKx1_HACTIVE) * HACTIVE] & 0x3FE

CLKx1_HDELAY and CLKx1_HACTIVE are constant values, so the equation

becomes:

NTSC: HDELAY = [(135 / 754) * HACTIVE] & 0x3FE
PAL/SECAM: HDELAY = [(186 / 922) * HACTIVE] & 0x3FE

In this equation, the HACTIVE value cannot be cropped.

Vertical Delay Register (VDELAY)

VDELAY is programmed with the delay be-

tween the rising edge of VRESET and the start of active video lines. It determines
how many lines to skip before initiating the ACTIVE signal. It is programmed with
the number of lines to skip at the beginning of a frame.

Vertical Active Register (VACTIVE)

VACTIVE is programmed with the number

of lines used in the vertical scaling process. The actual number of vertical lines out-
put from the Bt829A is equal to this register times the vertical scaling ratio. If VS-
CALE is set to 0x1A00 (4:1), then the actual number of lines output is
VACTIVE/4. If VSCALE is set to 0x0000 (1:1), then VACTIVE contains the actu-
al number of vertical lines output.

NOTE:

It is important to note the difference between the implementation of the
horizontal registers (HSCALE, HDELAY, and HACTIVE) and the verti-
cal registers (VSCALE, VDELAY, and VACTIVE). Horizontally, HDE-
LAY and HACTIVE are programmed with respect to the scaled pixels
defined by HSCALE. Vertically, VDELAY and VACTIVE are pro-
grammed with respect to the number of lines before scaling (before VS-
CALE is applied).

Temporal Decimation

Temporal decimation provides a solution for video synchronization during periods
when full frame rate cannot be supported due to bandwidth and system restrictions.

For example, when capturing live video for storage, system limitations such as

hard disk transfer rates or system bus bandwidth may limit the frame capture rate.
If these restrictions limit the frame rate to 15 frames per second, the Bt829A's time
scaling operation will enable the system to capture every other frame instead of al-
lowing the hard disk timing restrictions to dictate which frame to capture. This
maintains an even distribution of captured frames and alleviates the "jerky" effects
caused by systems that simply burst in data when the bandwidth becomes avail-
able.

The Bt829A provides temporal decimation on either a field or frame basis. The

temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC)
or 1 to 50 (PAL/SECAM). This value is the number of fields or frames skipped by
the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM. Skipped fields
and frames are considered inactive, which is indicated by the ACTIVE pin remain-
ing low. Consequently if QCLK is programmed to depend on ACTIVE, QCLK
would become inactive as well.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Video Scaling, Cropping, and Temporal Decimation

L829A_B

Examples:

When changing the programming in the temporal decimation register, 0x00

should be loaded first, and then the decimation value. This will ensure that the dec-
imation counter is reset to zero. If zero is not first loaded, the decimation may start
on any field or frame in the sequence of 60 (or 50 for PAL/SECAM). On power-up,
this preload is not necessary because the counter is internally reset.

When decimating fields, the FLDALIGN bit in the TDEC register can be pro-

grammed to choose whether the decimation starts with an odd field or an even
field. If the FLDALIGN bit is set to logical zero, the first field that is dropped dur-
ing the decimation process will be an odd field. Conversely, setting the
FLDALIGN bit to logical one causes the even field to be dropped first in the dec-
imation process.

TDEC = 0x02

Decimation is performed by frames. Two frames
are skipped per 60 frames of video, assuming
NTSC decoding.

Frames 129 are output normally, then AC-

TIVE remains low for one frame. Frames 3059
are then output followed by another frame of in-
active video.

TDEC = 0x9E

Decimation is performed by fields. Thirty fields
are output per 60 fields of video, assuming
NTSC decoding.

This value outputs every other field (every

odd field) of video starting with field one in
frame one.

TDEC = 0x01

Decimation is performed by frames. One frame
is skipped per 50 frames of video, assuming
PAL/SECAM decoding.

TDEC = 0x00

Decimation is not performed. Full frame rate
video is output by the Bt829A.

UNCTIONAL

ESCRIPTION

Video Adjustments

L829A_B

Bt829A/827A

VideoStream II Decoders

Video Adjustments

The Bt829A provides programmable hue, contrast, saturation, and brightness.

The Hue Adjust Register

(HUE)

The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC,
the hue of the video signal is defined as the phase of the subcarrier with reference
to the burst. The value programmed in this register is added or subtracted from the
phase of the subcarrier, which effectively changes the hue of the video. The hue
can be shifted by plus or minus 90 degrees. Because of the nature of PAL/SECAM
encoding, hue adjustments cannot be made when decoding PAL/SECAM.

The Contrast Adjust

Register (CONTRAST)

The Contrast Adjust Register (also called the luma gain) provides the ability to
change the contrast from approximately 0 percent to 200 percent of the original
value. The decoded luma value is multiplied by the 9-bit coefficient loaded into
this register.

The Saturation Adjust

Registers (SAT_U,

SAT_V)

The Saturation Adjust Registers are additional color adjustment registers. It is a
multiplicative gain of the U and V signals. The value programmed in these regis-
ters are the coefficients for the multiplication. The saturation range is from approx-
imately 0 percent to 200 percent of the original value.

The Brightness Register

(BRIGHT)

The Brightness Register is simply an offset for the decoded luma value. The pro-
grammed value is added or subtracted from the original luma value which changes
the brightness of the video output. The luma output is in the range of 0 to 255.
Brightness adjustment can be made over a range of 128 to +127.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

Bt829A VBI Data Output Interface

Introduction

A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM.
Figure 16 illustrates an NTSC video frame in which there are a number of distinct
regions. The video image or picture data is contained in the ODD and EVEN fields
within lines 21 to 262 and lines 283 to 525, respectively. Each field of video also
contains a region for vertical synchronization (lines 1 through 9 and 263 through
272) as well as a region which can contain non-video ancillary data (lines 10
through 20 and 273 through 282). We will refer to these regions which are between
the vertical synchronization region and the video picture region as the Vertical
Blanking Interval or VBI portion of the video signal.

Overview

In the default configuration of the Bt829A, the VBI region of the video signal is
treated the same way as the video image region of the signal. The Bt829A will de-
code this signal as if it was video, i.e., it will digitize at 8xFsc, decimate/filter to a
4xFsc sample stream, color separate to derive luma and chroma component infor-
mation, and interpolate for video synchronization and horizontal scaling. This pro-
cess is shown in Figure 17.

Figure 16. Regions of the Video Frame

Lines 19

Lines 1020

Lines 21262

Lines 263272
Lines 273282

Lines 283525

Vertical Blanking Interval

Video Image Region

Vertical Blanking Interval

Video Image Region

Odd Field

en Field

Vertical

Synchronization

Region

Vertical

Synchronization

Region

Figure 17. Bt829A YCrCb 4:2:2 Data Path

Decimation

Filter

Y/C

Separation

Filter

Interpolation

Filter

ADC

Composite

Analog

YCrCb

4:2:2

8xFsc

4xFsc

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

The Bt829A can be configured in a mode known as VBI data pass-through to

enable capture of the VBI region ancillary data for later processing by software. In
this mode the VBI region of the video signal is processed as follows:

The analog composite video signal is digitized at 8*Fsc (28.63636 MHz
for NTSC and 35.46895 MHz for PAL/SECAM). This 8-bit value repre-
sents a number range from the bottom of sync tip to peak of the compos-
ite video signal.

The 8-bit data stream bypasses the decimation filter, Y/C separation fil-
ters, and the interpolation filter (see Figure 18).

The Bt829A provides the option to pack the 8*Fsc data stream into a
2-byte-wide stream at 4*Fsc before outputting it to the VD[15:0] data
pins, or it can simply be output as an 8-bit 8*Fsc data stream on pins
VD[15:8]. In the packed format, the first byte of each pair on a 4*Fsc
clock cycle is mapped to VD[15:8] and the second byte to VD[7:0] with
VD[7] and VD[15] being the MSBs. The Bt829A uses the same 16-pin
data port for VBI data and YCrCb 4:2:2 image data. The byte pair order-
ing is programmable.

The VBI datastream is not pipeline delayed to match the YCrCb 4:2:2 im-
age output data with respect to horizontal timing (i.e. valid VBI data will
be output earlier than YCrCb 4:2:2 relative to the Bt829A HRESET sig-
nal).

A larger number of pixels per line are generated in VBI output mode than
in YCrCb 4:2:2 output mode. The downstream video processor must be
capable of dealing with a varying number of pixels per line in order to
capture VBI data as well as YCrCb 4:2:2 data from the same frame.

The following pins may be used to implement this solution: VD[15:0],
VACTIVE, HACTIVE, DVALID, VRESET, HRESET, CLKx1, CLKx2,
QCLK. This should allow the downstream video processor to load the
VBI data and the YCrCb 4:2:2 data correctly.

Because the 8*Fsc data stream does not pass through the interpolation fil-
ter, the sample stream is not locked/synchronized to the horizontal sync
timing. The only implication of this is that the sample locations on each
line are not correlated vertically.

Figure 18. Bt829A VBI Data Path

Decimation

Filter

Y/C

Separation

Filter

Interpolation

Filter

ADC

Composite

Analog

VBI

Data

8xFsc

4xFsc

Pack

Decimation

Filter

Y/C

Separation

Filter

Interpolation

Filter

ADC

Composite

Analog

VBI

Data

8xFsc

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

Functional Description

There are three modes of operation for the Bt829A VBI data pass-through feature:

1. VBI Data Pass-through Disabled. This is the default mode of operation

for the Bt829A during which the device decodes composite video and
generates a YCrCb 4:2:2 data stream.

2. VBI Line Output Mode. The device outputs unfiltered 8*Fsc data only

during the vertical interval which is defined by the VACTIVE output sig-
nal provided by the Bt829A. Data is output between the trailing edge of
the VRESET signal and the leading edge of VACTIVE. When VACTIVE
is high, the Bt829A is outputting standard YCrCb 4:2:2 data. This mode
of operation is intended to be used to enable capture of VBI lines contain-
ing ancillary data in addition to processing normal YCrCb 4:2:2 video
image data.

3. VBI Frame Output Mode. In this mode the Bt829A treats every line in

the video signal as if it were a vertical interval line and outputs only the
unfiltered 8*Fsc data on every line (i.e., it does not output any image
data). This mode of operation is designed for use in still-frame cap-
ture/processing applications.

VBI Line Output Mode

The VBI line output mode is enabled via the VBIEN bit in the VTC Register
(0x1B). When enabled, the VBI data is output during the VBI active period. The
VBI horizontal active period is defined as the interval between consecutive
Bt829A HRESET signals. Specifically, it starts at a point one CLKx1 interval after
the trailing edge of the first HRESET and ends with the leading edge of the follow-
ing HRESET. This interval is coincident with the HACTIVE signal as indicated in
Figure 19.

DVALID is always at a logical one during VBI. Also, QCLK is operating con-

tinuously at CLKx1 or CLKx2 rate during VBI. Valid VBI data is available one
CLKx1 (or QCLK) interval after the trailing edge of HRESET. When the Bt829A
is configured in VBI line output mode, it is generating invalid data outside of the
VBI horizontal active period. In standard YCrCb output mode, the horizontal ac-
tive period starts at a time point delayed from the leading edge of HRESET as de-
fined by the value programmed in the HDELAY register.

Figure 19. VBI Line Output Mode Timing

HRESET

HACTIVE

VD[15:0] VBI Data

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

The VBI data sample stream which is output during the VBI horizontal active

period represents an 8*Fsc sampled version of the analog video signal starting in
the vicinity of the sub-carrier burst and ending after the leading edge of the hori-
zontal synchronization pulse as illustrated in Figure 20.

The number of VBI data samples generated on each line may vary depending on

the stability of the analog composite video signal input to the Bt829A. The Bt829A
will generate 845 16-bit VBI data words for NTSC and 1070 16-bit VBI data words
for PAL/SECAM on each VBI line at a CLKx1 rate assuming a nominal or ideal
video input signal (i.e., the analog video signal has a stable horizontal time base).
This is also equivalent to 1690 8-bit VBI data samples for NTSC and 2140 8-bit
VBI data samples for PAL/SECAM. These values can deviate from the nominal
depending on the actual line length of the analog video signal.

The VBI vertical active period is defined as the period between the trailing edge

of the Bt829A VRESET signal and the leading edge of VACTIVE. Note that the
extent of the VBI vertical active region can be controlled by setting different values
in the VDELAY register. This provides the flexibility to configure the VBI vertical
active region as any group of consecutive lines starting with line 10 and extending
to the line number set by the equivalent line count value in the VDELAY register
(i.e., the VBI vertical active region can be extended into the video image region of
the video signal).

The VBI horizontal active period starts with the trailing edge of an HRESET;

therefore, if a rising edge of VRESET occurs after the horizontal active period has
already started, the VBI active period starts on the following line. The HACTIVE
pin is held at a logical one during the VBI horizontal active period. DVALID is held
high during both the VBI horizontal active and horizontal inactive periods (i.e., it
is held high during the whole VBI scan line.) These relationships are illustrated in
Figure 21.

Figure 20. VBI Sample Region

Extent of Analog Signal Captured in VBI Samples

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

The Bt829A can provide VBI data in all the pixel port output configurations

(i.e., 16-bit SPI, 8-bit SPI, and ByteStreamTM modes). The range of the VBI data
can be controlled with the RANGE bit in the OFORM Register (0x12). It is nec-
essary to limit the range of VBI data for ByteStreamTM output mode.

There must be a video signal present on the Bt829A analog input as defined by

the status of the VPRES bit in the STATUS register in order for the Bt829A to gen-
erate VBI data. If the status of the VPRES bit reflects no analog input, then the
Bt829A generates YCrCb data to create a flat blue field image.

The order in which the VBI data is presented on the output pins is programma-

ble. Setting the VBIFMT bit in the VTC register to a logical zero places the nth data
sample on VD[15:8] and the nth+1 sample on VD[7:0]. Setting VBIFMT to a log-
ical one reverses the above. Similarly, in ByteStreamTM and 8-bit output modes,
setting VBIFMT = 0 generates a VBI sample stream with an ordering sequence of
n+1, n, n+3, n+2, n+5, n+4, etc. Setting VBIFMT = 1 for ByteStreamTM/8-bit out-
put generates an n, n+1, n+2, n+3, etc. sequence as shown in Figure 22.

A video processor/controller should be able to do the following to capture VBI

data output by the Bt829A:

Keep track of the line count in order to select a limited number of specific
lines for processing of VBI data.

Handle data type transitioning on the fly from the vertical interval to the
active video image region. For example, during the vertical interval with
VBI data pass-through enabled, it must grab every byte pair while
HACTIVE is high using the 4*Fsc clock or QCLK. However, when the
data stream transitions into YCrCb 4:2:2 data mode with VACTIVE
going high, the video processor must interpret the DVALID signal (or use
QCLK for the data load clock) from the Bt829A for pixel qualification
and use only valid pixel cycles to load image data (default Bt829A
operation).

Handle a large and varying number of horizontal pixels per line in the
VBI region as compared to the active image region.

Figure 22. VBI Sample Ordering

VD[15:8]

VD[7:0]

CLKx1

VD[15:8]

CLKx2

n+2

n+1

n+3

n+2

n+1

n+3

16-bit SPI Mode (VBIFMT = 0)

8-bit SPI Mode (VBIFMT = 1)

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Bt829A VBI Data Output Interface

L829A_B

VBI Frame Output Mode

In VBI frame output mode, the Bt829A is generating VBI data all the time (i.e.,
there is no VBI active interval). In essence, the Bt829A is acting as an ADC con-
tinuously sampling the entire video signal at 8*Fsc. The Bt829A generates
HRESET,VRESET and FIELD timing signals in addition to the VBI data, but the
DVALID, HACTIVE, and VACTIVE signals are all held high during VBI frame
output operation. The behavior of the HRESET,VRESET, and FIELD timing sig-
nals is the same as normal YCrCb 4:2:2 output operation. The HRESET,VRESET,
and FIELD timing signals can be used by the video processor to detect the begin-
ning of a video frame/field, at which point it can start to capture a full frame/field
of VBI data.

The number of VBI data samples generated on each line may vary depending on

the stability of the analog composite video signal input to the Bt829A. The Bt829A
will generate 910 16-bit VBI data words for NTSC and 1135 16-bit VBI data words
for PAL/SECAM for each line of analog video input at a CLKx1 rate assuming a
nominal or ideal video input signal (i.e., analog video signal has a stable horizontal
time base). This is also equivalent to 1820 8-bit VBI data samples for NTSC and
2270 8-bit VBI data samples for PAL/SECAM for each line of analog video input.
These values can deviate from the nominal depending on the actual line length of
the analog video signal.

VBI frame output mode is enabled via the VBIFRM bit in the OFORM register.

The output byte ordering may be controlled by the VBIFMT bit as described for
VBI line output mode. If both VBI line output and VBI frame output modes are en-
abled at the same time, the VBI frame output mode takes precedence. The VBI data
range in VBI frame output mode can be controlled using the RANGE bit in the
OFORM register, and a video signal must be present on the Bt829A analog input
for this mode to operate as defined by the status of the VPRES bit in the STATUS
register (0x00).

UNCTIONAL

ESCRIPTION

Closed Captioning and Extended Data Services Decoding

L829A_B

Bt829A/827A

VideoStream II Decoders

Closed Captioning and Extended Data Services
Decoding

In a system capable of capturing Closed Captioning (CC) and Extended Data Ser-
vices (EDS) adhering to the EIA-608 standard, two bytes of information are pre-
sented to the video decoder on line 21 (odd field) for CC and an additional two
bytes are presented on line 284 (even field) for EDS.

The data presented to the video decoder is an analog signal on the composite

video input. The signal contains information identifying it as the CC/EDS data and
is followed by a control code and two bytes of digital information transmitted by
the analog signal. For the purposes of CC/EDS, only the luma component of the
video signal is relevant. Therefore, the composite signal goes through the decima-
tion and Y/C separation blocks of the Bt829A before any CC/EDS decoding takes
place. See Figure 23 for a representation of this procedure.

The Bt829A can be programmed to decode CC/EDS data via the corresponding

bits in the Extended Data Services/Closed Caption Status Register
(CC_STATUS;0X1C).

The CC and EDS are independent and the video decoder

may capture one or both in a given frame. The CC/EDS signal is displayed in
Figure 24. In CC/EDS decode mode, once Bt829A has detected that line 21 of the
field is being displayed, the decoder looks for the Clock Run-In signal. If the Clock
Run-In signal is present and the correct start code (001) is recognized by Bt829A,
then the CC/EDS data capture commences. Each of the two bytes of data transmit-
ted to the video decoder per field contains a 7-bit ASCII code and a parity bit. The
convention for CC/EDS data is odd parity.

Figure 23. CC/EDS Data Processing Path

Decimation

Filter

Y/C

Separation

Filter

Interpolation

Filter

ADC

Composite

Analog

YCrCb

4:2:2

CC/EDS
Decoder

CC/EDS

FIFO

CC_Data

CC_Status

Luma

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Closed Captioning and Extended Data Services Decoding

L829A_B

The Bt829A provides a 16 x 10 location FIFO for storing CC/EDS data. Once the
video decoder detects the start signal in the CC/EDS signal, it captures the low byte
of CC/EDS data first and checks to see if the FIFO is full. If the FIFO is not full,
then the data is stored in the FIFO, and is available to the user through the
CC_DATA register (0x1D). The high byte of CC/EDS data is captured next and
placed in the FIFO. Upon being placed in the 10-bit FIFO, two additional bits are
attached to the CC/EDS data byte by Bt829A's CC/EDS decoder. These two bits
indicate whether the given byte stored in the FIFO corresponds to CC or EDS data
and whether it is the high or low byte of CC/EDS. These two bits are available to
the user through the CC_STATUS register bits CC_EDS and LO_HI, respectively.

The parity bit is stored in the FIFO as shown in Figure 25. Additionally, the

Bt829A stores the results of the parity check in the PARITY_ERR bit in the
CC_STATUS register.

Figure 24. CC/EDS Incoming Signal

S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2

Start Bits

Character One

Character Two

Clock Run-in

Color

HSync

Burst

IRE

Figure 25. Closed Captioning/Extended Data Services FIFO

Location 0
Location 1

Location 15

9 8 7 6

MSB

LSB

...

7-bit ASCII code available through CC_DATA Registe

Parity Bit Available Through CC_DATA Register

LO_HI Available Through CC_STATUS Register

CC_EDS Available Through CC_STATUS Register

UNCTIONAL

ESCRIPTION

Closed Captioning and Extended Data Services Decoding

L829A_B

Bt829A/827A

VideoStream II Decoders

The 16-location FIFO can hold eight lines worth of CC/EDS data, at two bytes

per line. Initially when the FIFO is empty, bit DA in the CC_STATUS register
(0x1C) is set low and indicates that no data is available in the FIFO. Subsequently,
when data has been stored in the FIFO, the DA bit is set to logical high. Once the
FIFO is half full, the CC_VALID interrupts pin signals to the system that the FIFO
contents should be read in the near future. The CC_VALID pin is enabled via a bit
in the CC_STATUS register (0x1C). The system controller can then poll the
CC_VALID bit in the STATUS register (0x00) to ensure that it was the Bt829A
that initiated the CC_VALID interrupt. This bit can also be used in applications
where the CC_VALID pin is disabled by the user.

When the first byte of CC/EDS data is decoded and stored in the FIFO, the data

is immediately placed in the CC_DATA and CC_STATUS registers and is avail-
able to be read. Once the data is read from the CC_DATA register, the information
in the next location of the FIFO is placed in the CC_DATA and CC_STATUS reg-
isters.

If the controller in the system ignores the Bt829A CC_VALID interrupts pin for

a sufficiently long period of time, then the CC/EDS FIFO will become full and the
Bt829A will not be able to write additional data to the FIFO. Any incoming bytes
of data will be lost and an overflow condition will occur; bit OR in the
CC_STATUS register will be set to a logical one. The system may clear the over-
flow condition by reading the CC/EDS data and creating space in the FIFO for new
information. As a result, the overflow bit is reset to a logical zero.

There will routinely be asynchronous reads and writes to the CC/EDS FIFO.

The writes will be from the CC/EDS circuitry and the reads will occur as the sys-
tem controller reads the CC/EDS data from Bt829A. These reads and writes will
sometimes occur simultaneously, and the Bt829A is designed to give priority to the
read operations. In the case where the CC_DATA register data is specifically being
read to clear an overflow condition, the simultaneous occurrence of a read and a
write will not cause the overflow bit to be reset, even though the read has priority.
An additional read must be made to the CC_DATA register in order to clear the
overflow condition. As always, the write data will be lost while the FIFO is in over-
flow condition.

The FIFO is reset when both CC and EDS bits are disabled in the CC_STATUS

Automatic Chrominance

Gain Control

The Automatic Chrominance Gain Control compensates for reduced chrominance
and color-burst amplitude. This can be caused by high-frequency loss in cabling.
Here, the color-burst amplitude is calculated and compared to nominal. The col-
or-difference signals are then increased or decreased in amplitude according to the
color-burst amplitude difference from nominal. The maximum amount of chromi-
nance gain is 0.52 times the original amplitude. This compensation coefficient is
then multiplied by the value in the Saturation Adjust Register for a total chromi-
nance gain range of 02 times the original signal. Automatic chrominance gain
control may be disabled by setting the CAGC bit in the SCLOOP register to a log-
ical zero.

Bt829A/827A

VideoStream II Decoders

UNCTIONAL

ESCRIPTION

Closed Captioning and Extended Data Services Decoding

L829A_B

Low Color Detection and

Removal

If a color burst of 25 percent (NTSC) or 35 percent (PAL/SECAM) or less of the
nominal amplitude is detected for 127 consecutive scan lines, the color-difference
signals U and V are set to zero. When the low color detection is active, the reduced
chrominance signal is still separated from the composite signal to generate the lu-
minance portion of the signal. The resulting Cr and Cb values are 128. Output of
the chrominance signal is re-enabled when a color burst of 43 percent (NTSC) or
60 percent (PAL/SECAM) or greater of nominal amplitude is detected for 127 con-
secutive scan lines.

Low color detection and removal may be disabled by setting the CKILL bit in

the SCLOOP register (0x10) to a logical zero.

Coring

The Bt829A video decoder can perform a coring function, in which it forces all
values below a programmed level to be zero. This is useful because the human eye
is more sensitive to variations in black images. By taking near-black images and
turning them into black, the image appears clearer to the eye.

Four coring values can be selected by the Output Format Register (OFORM;

0x12): 0, 8, 16, or 32 above black. If the total luminance level is below the selected
limit, the luminance signal is truncated to the black value. If the luma range is lim-
ited (i.e., black is 16), then the coring circuitry automatically takes this into ac-
count and references the appropriate value for black. This is illustrated in
Figure 26.

Figure 26. Coring Map

Calculated

Luma Value

Output

Luma

alue

L829A_B

LECTRICAL

NTERFACES

Input Interface

Analog Signal Selection

The Bt829A/827A contains an on-chip 4:1 MUX. For the Bt829A and Bt827A,
this multiplexer can be used to switch between four composite sources or three
composite sources and one S-Video source. In the first configuration, connect the
inputs of the multiplexer (MUX[0], MUX[1], MUX[2] and MUX[3]) to the four
composite sources. In the second configuration, connect three inputs to the com-
posite sources and the other input to the luma component of the S-Video connector.
In both configurations the output of the multiplexer (MUXOUT) should be con-
nected to the input to the luma A/D (YIN) and the input to the sync detection cir-
cuitry (SYNCDET) through a optional 0.1

F capacitor (to maintain compatibility

with the Bt829/827). When implementing S-Video, the input to the chroma A/D
(CIN) should be connected to the chroma signal of the S-Video connector.

Use of the multiplexer is not a requirement for operation. If digitization of only

one video source is required, the source may be connected directly to YIN.

Multiplexer

Considerations

The multiplexer is not a break-before-make design. Therefore, during the multi-
plexer switching time it is possible for the input video signals to be momentarily
connected together through the equivalent of 200

The multiplexers cannot be switched on a real-time pixel-by-pixel basis.

Autodetection of NTSC or

PAL/SECAM Video

If the Bt829A is configured to decode both NTSC and PAL/SECAM, the Bt829A
can be programmed to automatically detect which format is being input to the chip.
Autodetection will select the proper clock source for the format detected. If
NTSC/PALM is detected, XTAL0 is selected. If PAL/SECAM is detected,
XTAL1 is selected. For PAL-N combination the user must manually select the
XTAL0 crystal. Full control of the decoding configuration can be programmed by
writing to the Input Format Register (0x01).

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

Input Interface

L829A_B

The Bt829A determines the video source input to the chip by counting the num-

ber of lines in a frame. Bit NUML indicates the result in the STATUS register.
Based on this bit, the format of the video is determined, and XT0 or XT1 is select-
ed for the clock source. Automatic format detection will select the clock source,
but it will not program the required registers. The scaling and cropping registers
(VSCALE, HSCALE, VDELAY, HDELAY, VACTIVE, and HACTIVE) as well as
the burst delay and AGC delay registers (BDELAY and ADELAY) must be pro-
grammed accordingly.

Flash A/D Converters

The Bt829A and Bt827A use two on-chip flash A/D converters to digitize the video
signals. YREF+, CREF+ and YREF, CREF are the respective top and bottom of
the internal resistor ladder.

The input video is always ac-coupled to the decoder. CREF and YREF are

connected to analog ground. The voltage levels for YREF+ and CREF+ are con-
trolled by the gain control circuitry. If the input video momentarily exceeds the
corresponding REF+ voltage it is indicated by LOF and COF in the STATUS reg-
ister.

A/D Clamping

An internally generated clamp control signal is used to clamp the inputs of the A/D
converter for DC restoration of the video signals. Clamping for both the YIN and
CIN analog inputs occurs within the horizontal sync tip. The YIN input is always
restored to ground while the CIN input is always restored to CLEVEL. CLEVEL
can be set with an optional external resistor network so that it is biased to the mid-
point between CREF and CREF+. This insures backward compatibility with
Bt819A/7A/5A but is not required for the Bt829A/827A. External clamping is not
required because internal clamping is automatically performed.

Power-up Operation

Upon power-up, the status of the Bt829A's registers is indeterminate. The RST sig-
nal must be asserted to set the register bits to their default values. The Bt829A de-
vice defaults to NTSC-M format upon reset. If pin 85 (OEPOLE) is a logical high
and the RST signal is asserted then the video pixel bus, sync signals, and output
clocks will be three-stated.

Automatic Gain Controls

The REFOUT, CREF+ and YREF+ pins should be connected together as shown in
Figure 27. In this configuration, the Bt829A controls the voltage for the top of the
reference ladder for each A/D. The automatic gain control adjusts the YREF+ and
CREF+ voltage levels until the back porch of the Y video input generates a digital
code 0x38 from the A/D. If the video being digitized has a non-standard sync
height to video height ratio, the digital code used for AGC may be changed by pro-
gramming the ADC Interface Register (0x1A). Figure 28 illustrates Bt829A exter-
nal circuitry with reduced passive components.

LECTRICAL

NTERFACES

Input Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

Crystal Inputs and Clock

Generation

The Bt829A has two pairs of pins: XT0I/XT0O and XT1I/XT1O. They are used to
input a clock source. If both NTSC and PAL video are being digitized, both clock
inputs must be implemented. The XT0 port is used to decode NTSC video and
must be configured with a 28.63636 MHz source. The XT1 port is used to decode
PAL video and must be configured with a 35.46895 MHz source.

If the Bt829A is configured to decode either NTSC or PAL but not both, then

only one clock source must be provided to the chip and it must be connected to the
XT0I/XT0O port. If a crystal input is not used, the crystal amplifiers are internally
shut down to save power.

Crystals are specified as follows:

28.636363 MHz or 35.468950 MHz

Third overtone

Parallel resonant

30 pF load capacitance

50 ppm

Series resistance 40

or less

The following crystals are recommended for use with the Bt829A:

Standard Crystal
(818) 443-2121
2BAK28M636363GLE30A
2BAK35M468950GLE30A

MMD
(714) 444-1402
A30AA3-28.63636 MHz
A30AA3-35.46895 MHz

GED
(619) 591-4170
PKHC49-28.63636-.030-005-40R, 3rd overtone crystal
PKHC49-35.46895-.030-005-40R, 3rd overtone crystal

M-Tron
(800) 762-8800
MP-1 28.63636, 3rd overtone crystal
MP-1 35.46895, 3rd overtone crystal

Monitor
(619) 433-4510
MM49X3C3A-28.63636, 3rd overtone crystal
MM49X3C3A-35.46895, 3rd overtone crystal

CTS
(815) 786-8411
R3B55A30-28.63636, 3rd overtone crystal
R3B55A30-35.46895, 3rd overtone crystal

Fox
(813) 693-0099
HC49U-28.63636, 3rd overtone crystal
HC49U-35.46895, 3rd overtone crystal

LECTRICAL

NTERFACES

Output Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

Output Interface

Output Interfaces

The Bt829A supports a Synchronous Pixel Interface (SPI). SPI can support 8-bit or
16-bit YCrCb 4:2:2 data streams.

Bt829A outputs all pixel and control data synchronous with CLKx1 (16-bit

mode), or CLKx2 (8-bit mode). Events such as HRESET and VRESET may also
be encoded as control codes in the data stream to enable a reduced pin interface
(ByteStream

Mode selections are controlled by the state of the OFORM register (0x12).

Figure 31 shows a diagram summarizing the different operating modes. Each
mode will be covered in detail individually. On power-up, the Bt829A automati-
cally initializes to SPI mode 1, 16 bits wide.

YCrCb Pixel Stream

Format, SPI Mode 8- and

16-bit Formats

When the output is configured for an 8-bit pixel interface, the data is output on pins
VD[15:8] with eight bits of chrominance data preceding eight bits of luminance
data for each pixel. New pixel data is output on the pixel port after each rising edge
of CLKx2. When the output is configured for the 16-bit pixel interface, the lumi-
nance data is output on VD[15:8], and the chrominance data is output on VD[7:0].
In 16-bit mode, the data is output with respect to CLKx1. See Table 7 for a sum-
mary of output interface configurations. The YCrCb 4:2:2 pixel stream follows the
CCIR recommendation as illustrated in Figure 32.

Figure 31. Output Mode Summary

SPI

8-bit

16-bit

8-bit

16-bit

Parallel Control

(SPI Mode 1)

Coded Control

(SPI Mode 2)

(ByteStreamTM)

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

Output Interface

L829A_B

Synchronous Pixel

Interface (SPI, Mode 2,

ByteStreamTM)

In SPI Mode 2, the Bt829A encodes all video timing control signals onto the pixel
data bus. ByteStreamTM is the 8-bit version of this configuration. Because all tim-
ing data is included on the data bus, a complete interface to a video controller can
be implemented in only nine pins: one for CLKx2 and eight for data.

When using coded control, the RANGE bit and the CODE bit must be pro-

grammed high. When the RANGE bit is high, the chrominance pixels (both Cr and
Cb) are saturated to the range 2 to 253, and the luminance range is limited to the
range 16 to 253. In SPI Mode 2, the chroma values of 255 and 254, and the lumi-
nance values of 0 to 15 are inserted as control codes to indicate video events
(Table 8). A chroma value of 255 is used to indicate that the associated luma pixel
is a control code; a pixel value of 255 also indicates that the CbFlag is high (i.e., the
current pixel is a Cb pixel). Similarly, a pixel value of 254 indicates that the luma
value is a control code, and the CbFlag is low (Cr pixel).

The first pixel of a line is guaranteed to be a Cb flag, however, due to code pre-

cedence relationships, the HRESET code may be delayed by one pixel, so
HRESET can occur on a Cr or a Cb pixel. Also, at the beginning of a new field the
relationship between VRESET and HRESET may be lost, typically with video
from a VCR. As a result, VRESET can occur during either a Cb or a Cr pixel.
Figure 35 demonstrates coded control for SPI mode 2 (ByteStreamTM).

Pixel data output ranges are shown in Table 9. Independent of RANGE, decimal

128 indicates zero color information for Cr and Cb. Black is decimal 16 when
RANGE = 0, and code 0 when RANGE = 1.

Figures 36 and 37 illustrate videotiming for both SPI Modes 1 and 2.

Table 8. Description of the Control Codes in the Pixel Stream

Luma
Value

Chroma
Value

Video Event Description

0x00

0xFF
0xFE

This is an invalid pixel; last valid pixel was a Cb pixel.
This is an invalid pixel; last valid pixel was a Cr pixel.

0x01

0xFF
0xFE

Cb pixel; last pixel was the last active pixel of the line.
Cr pixel; last pixel was the last active pixel of the line.

0x02

0xFF
0xFE

Cb pixel; next pixel is the first active pixel of the line.
Cr pixel; next pixel is the first active pixel of the line.

0x03

0xFF
0xFE

Cb pixel; HRESET of a vertical active line.
Cr pixel; HRESET of a vertical active line.

0x04

0xFF
0xFE

Cb pixel; HRESET of a vertical blank line.
Cr pixel; HRESET of a vertical blank line.

0x05

0xFF
0xFE

Cb pixel; VRESET followed by an even field.
Cr pixel; VRESET followed by an even field.

0x06

0xFF
0xFE

Cb pixel; VRESET followed by an odd field.
Cr pixel; VRESET followed by an odd field.

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

C Interface

L829A_B

C Interface

The Inter-Integrated Circuit bus is a two-wire serial interface. Serial Clock (SCL)
and Data Lines (SDA), are used to transfer data between the bus master and the
slave device. The Bt829A can transfer data at a maximum rate of 100 kbits/s. The
Bt829A operates as a slave device.

Starting and Stopping

The relationship between SCL and SDA is decoded to provide both a start and stop
condition on the bus. To initiate a transfer on the I

C bus, the master must transmit

a start pulse to the slave device. This is accomplished by taking the SDA line low
while the SCL line is held high. The master should only generate a start pulse at the
beginning of the cycle, or after the transfer of a data byte to or from the slave. To
terminate a transfer, the master must take the SDA line high while the SCL line is
held high. The master may issue a stop pulse at any time during an I

C cycle. Since

the I

C bus will interpret any transition on the SDA line during the high phase of

the SCL line as a start or stop pulse, care must be taken to ensure that data is stable
during the high phase of the clock. This is illustrated in Figure 38.

Addressing the Bt829A

An I

C slave address consists of two parts: a 7-bit base address and a single bit

R/W command. The R/W bit is appended to the base address to form the transmit-
ted I

C address, as shown in Figure 39 and Table 10.

Figure 38. The Relationship between SCL and SDA

Start

Stop

SDA

SCL

Figure 39. I

C Slave Address Configuration

A0 R/W

Base Address

R/W Bit

LECTRICAL

NTERFACES

C Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

Reading and Writing

After transmitting a start pulse to initiate a cycle, the master must address the
Bt829A. To do this, the master must transmit one of the four valid Bt829A address-
es, Most Significant Bit (MSB) first. After transmitting the address, the master
must release the SDA line during the low phase of the SCL and wait for an ac-
knowledge. If the transmitted address matches the selected Bt829A address, the
Bt829A will respond by driving the SDA line low, generating an acknowledge to
the master. The master will sample the SDA line at the rising edge of the SCL line,
and proceed with the cycle. If no device responds, including the Bt829A, the mas-
ter transmits a stop pulse and ends the cycle.

If the slave address R/W bit was low (indicating a write) the master will transmit

an 8-bit byte to the Bt829A, MSB first. The Bt829A will acknowledge the transfer
and load the data into its internal address register. The master can now issue a stop
command, a start command, or transfer another 8-bit byte, MSB first, to be loaded
into the register pointed to by the internal address register. The Bt829A will then
acknowledge the transfer and increment the address register in preparation for the
next transfer. As before, the master may now issue a stop command, a start com-
mand, or transfer another 8 bits to be loaded into the next location.

If the slave address R/W bit was high (indicating a read) the Bt829A will trans-

fer the contents of the register pointed to by its internal address register, MSB first.
The master should acknowledge the receipt of the data and pull the SDA line low.
As with the write cycle, the address register will be auto-incremented in prepara-
tion for the next read.

To stop a read transfer, the host must not acknowledge the last read cycle. The

Bt829A will then release the data bus in preparation for a stop command. If an ac-
knowledge is received, the Bt829A will proceed to transfer the next register.

When the master generates a read from the Bt829A, the Bt829A will start its

transfer from whatever location is currently loaded in the address register. Since
the address register might not contain the address of the desired register, the master
should execute a write cycle, setting the address register to the desired location.
After receiving an acknowledge for the transfer of the data into the address register,
the master should initiate a read of the Bt829A by starting a new I

C cycle with an

appropriate read address. The Bt829A now transfers the contents of the desired
register.

Table 10. Bt829A Address Matrix

I2CCS Pin

Bt829A Base

R/W Bit

Action

1000100

Write

1000100

Read

1000101

Write

1000101

Read

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

C Interface

L829A_B

For example, to read register 0x0A, Brightness Control, the master should start

a write cycle with an I

C address of 0x88 or 0x8A. After receiving an acknowledge

from the Bt829A, the master should transmit the desired address, 0x0A. After re-
ceiving an acknowledge, the master should then start a read cycle with an I

C slave

address of 0x89 or 0x8B. The Bt829A will then acknowledge and transfer the con-
tents of register 0x0A. There is no need to issue a stop command after the write cy-
cle. The Bt829A will detect the repeated start command, and start a new I

C cycle.

This process is illustrated in Table 11 and Figure 40.

For detailed information on the I

C bus, refer to "The I

C-Bus Reference

Guide," reprinted by Rockwell.

Table 11. Example I

C Data Transactions

Master

Data
Flow

Bt829A

Comment

Write to Bt829A

C Start

---->

Master sends Bt829A chip address, i.e., 0x88 or 0x8A.

ACK

Bt829A generates ACK on successful receipt of chip address.

Sub-address

---->

Master sends sub-address to Bt829A.

ACK

Bt829A generates ACK on successful receipt of sub-address.

Data(0)

---->

Master sends first data byte to Bt829A.

ACK(0)

Bt829A generates ACK on successful receipt of 1st data byte.

.
.
.

---->
---->
---->

.
.
.

Data(n)

---->

Master sends nth data byte to Bt829A.

ACK(n)

Bt829A generates ACK on successful receipt of nth data byte.

C Stop

Master generates STOP to end transfer.

Read from Bt829A

C Start

---->

Master sends Bt829A chip address, i.e., 0x89 or 0x8B.

ACK

Bt829A generates ACK on successful receipt of chip address.

<----

Data(0)

Bt829A sends first data byte to Master.

ACK(0)

Master generates ACK on successful receipt of 1st data byte.

.
.
.

<----
<----
<----

.
.
.

<----

Data(n-1)

Bt829A sends (n-1)th data byte to Master.

ACK(n-1)

Master generates ACK on successful receipt of (n-1)th data byte.

<----

Data(n)

Bt829A sends nth data byte to Master.

NO ACK

Master does not acknowledge nth data byte.

C Stop

Master generates STOP to end transfer.

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

JTAG Interface

L829A_B

JTAG Interface

Need for Functional

Verification

As the complexity of imaging chips increases, the need to easily access individual
chips for functional verification is becoming vital. The Bt829A has incorporated
special circuitry that allows it to be accessed in full compliance with standards set
by the Joint Test Action Group. Conforming to IEEE P1149.1 "Standard Test Ac-
cess Port and Boundary Scan Architecture," the Bt829A has dedicated pins that are
used for testability purposes only.

JTAG Approach to

Testability

JTAG's approach to testability utilizes boundary scan cells placed at each digital
pin and digital interface (a digital interface is the boundary between an analog
block and a digital block within the Bt829A). All cells are interconnected into a
boundary scan register that applies or captures test data to verify functionality of
the integrated circuit. JTAG is particularly useful for board testers using functional
testing methods.

JTAG consists of five dedicated pins comprising the Test Access Port (TAP).

These pins are Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI),
Test Data Out (TDO) and Test Reset (TRST). The TRST pin will reset the JTAG
controller when pulled low at any time. Verification of the integrated circuit and its
connection to other modules on the printed circuit board can be achieved through
these five TAP pins. With boundary scan cells at each digital interface and pin, the
Bt829A has the capability to apply and capture the respective logic levels. Because
all of the digital pins are interconnected as a long shift register, the TAP logic has
access and control of all the necessary pins to verify functionality. The TAP con-
troller can shift in any number of test vectors through the TDI input and apply them
to the internal circuitry. The output result is scanned out on the TDO pin and ex-
ternally checked. While isolating the Bt829A from other components on the board,
the user has easy access to all Bt829A digital pins and digital interfaces through the
TAP and can perform complete functionality tests without using expensive
bed-of-nails testers.

Optional Device ID

Register

The Bt829A has the optional device identification register defined by the JTAG
specification. This register contains information concerning the revision, actual
part number, and manufacturers identification code specific to Rockwell. This reg-
ister can be accessed through the TAP controller via an optional JTAG instruction.
Refer to Table 12.

LECTRICAL

NTERFACES

JTAG Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

Verification with the Tap

Controller

A variety of verification procedures can be performed through the TAP controller.
Using a set of four instructions, the Bt829A can verify board connectivity at all
digital interfaces and pins. The instructions can be accessed by using a state ma-
chine standard to all JTAG controllers and are Sample/Preload, Extest, ID Code,
and Bypass (see Figure 41). Refer to the IEEE P1149.1 specification for details
concerning the Instruction Register and JTAG state machine.

Rockwell has created a BSDL with the AT&T BSD Editor. Should JTAG testing

be implemented, a disk with an ASCII version of the complete BSDL file can be
obtained by contacting your local Rockwell sales office.

Table 12. Device Identification Register

Version

Part Number

Manufacturer ID

X X X X 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1

0829, 0x033D

0x0D6

4 Bits

16 Bits

11 Bits

Note: The part number remains the same for both parts: Bt829A and Bt827A.

Figure 41. Instruction Register

TDI

TDO

EXTEST

Sample/Preload

ID Code

Bypass

Bt829A/827A

VideoStream II Decoders

LECTRICAL

NTERFACES

JTAG Interface

L829A_B

Example BSDL Listing

attribute BOUNDARY_REGISTER of Bt829A : entity is

" 0 (BC_1, *, control, 1)," &

" 1 (BC_1, *, internal, 1)," &

" 2 (BC_1, *, control, 1)," &

" 3 (BC_1, *, internal, X)," &

" 4 (BC_1, *, internal, X)," &

" 5 (BC_1, *, internal, X)," &

" 6 (BC_1, *, internal, X)," &

" 7 (BC_1, *, internal, X)," &

" 8 (BC_1, *, internal, X)," &

" 9 (BC_1, *, internal, X)," &

" 10 (BC_1, *, internal, X)," &

" 11 (BC_1, *, internal, X)," &

" 12 (BC_1, *, internal, X)," &

" 13 (BC_1, *, internal, 0)," &

" 14 (BC_1, *, internal, 0)," &

" 15 (BC_1, *, internal, 0)," &

" 16 (BC_1, *, internal, 0)," &

" 17 (BC_1, *, internal, 0)," &

" 18 (BC_1, *, internal, 0)," &

" 19 (BC_1, *, internal, 0)," &

" 20 (BC_1, *, internal, 0)," &

" 21 (BC_1, *, internal, 0)," &

" 22 (BC_1, *, internal, 0)," &

" 23 (BC_1, *, internal, 0)," &

" 24 (BC_1, *, internal, 0)," &

" 25 (BC_1, *, internal, 0)," &

" 26 (BC_1, *, internal, 0)," &

" 27 (BC_1, *, internal, 0)," &

" 28 (BC_1, *, control, 0)," &

" 29 (BC_1, FIELD, output3, X, 28, 0, Z)," &

" 30 (BC_1, NVRESET, output3, X, 28, 0, Z)," &

" 31 (BC_1, XTFMT, input, X)," &

" 32 (BC_1, NHRESET, output3, X, 28, 0, Z)," &

" 33 (BC_1, ACTIVE, output3, X, 28, 0, Z)," &

" 34 (BC_1, DVALID, output3, X, 28, 0, Z)," &

" 35 (BC_1, VACTIVE, output3, X, 28, 0, Z)," &

" 36 (BC_1, TST, output2, 0, 36, 0, Weak1)," &

" 37 (BC_1, *, internal, X)," &

" 38 (BC_1, CBFLAG, output3, X, 28, 0, Z)," &

" 39 (BC_3, NVSEN, input, X)," &

" 40 (BC_1, PWRDN, input, X)," &

" 41 (BC_1, QCLK, output3, X, 28, 0, Z)," &

" 42 (BC_1, CLKX1, output3, X, 28, 0, Z)," &

" 43 (BC_1, NOE, input, 1)," &

" 44 (BC_1, CLKX2, output3, X, 28, 0, Z)," &

" 45 (BC_1, VDB(13), output3, X, 28, 0, Z)," &

LECTRICAL

NTERFACES

JTAG Interface

L829A_B

Bt829A/827A

VideoStream II Decoders

" 46 (BC_1, VDB(14), output3, X, 28, 0, Z)," &

" 47 (BC_1, VDB(15), output3, X, 28, 0, Z)," &

" 48 (BC_1, VDB(8), output3, X, 28, 0, Z)," &

" 49 (BC_1, VDB(9), output3, X, 28, 0, Z)," &

" 50 (BC_1, VDB(10), output3, X, 28, 0, Z)," &

" 51 (BC_1, VDB(11), output3, X, 28, 0, Z)," &

" 52 (BC_1, VDB(12), output3, X, 28, 0, Z)," &

" 53 (BC_1, *, internal, X)," &

" 54 (BC_1, XT0I, input, X)," &

" 55 (BC_1, I2CCS, input, X)," &

" 56 (BC_1, NRST, input, X)," &

" 57 (BC_1, *, internal, X)," &

" 58 (BC_1, XT1I, input, X)," &

" 59 (BC_1, SDA, output2, 0, 59, 1, Pull1)," &

" 60 (BC_1, SDA, input, X)," &

" 61 (BC_1, SCL, input, X)," &

" 62 (BC_1, VDA(3), output3, X, 0, 1, Z)," &

" 63 (BC_1, VDA(3), input, X)," &

" 64 (BC_1, VDA(4), output3, X, 2, 1, Z)," &

" 65 (BC_1, VDA(4), input, X)," &

" 66 (BC_1, VDA(5), output3, X, 2, 1, Z)," &

" 67 (BC_1, VDA(5), input, X)," &

" 68 (BC_1, VDA(6), output3, X, 2, 1, Z)," &

" 69 (BC_1, VDA(6), input, X)," &

" 70 (BC_1, VDA(7), output3, X, 2, 1, Z)," &

" 71 (BC_1, VDA(7), input, X)," &

" 72 (BC_1, VDA(0), output3, X, 0, 1, Z)," &

" 73 (BC_1, VDA(0), input, X)," &

" 74 (BC_1, VDA(1), output3, X, 0, 1, Z)," &

" 75 (BC_1, VDA(1), input, X)," &

" 76 (BC_1, VDA(2), output3, X, 0, 1, Z)," &

" 77 (BC_1, VDA(2), input, X)," &

" 78 (BC_1, TWREN, input, X)," &

" 79 (BC_0, *, internal, 0)," &

" 80 (BC_0, *, internal, 0)";

end Bt829A;

Bt829A/827A

VideoStream II Decoders

PC B

OARD

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ONSIDERATIONS

Power Planes

L829A_B

Power Planes

The power plane area should encompass all Bt829A power pins, voltage reference
circuitry, power supply bypass circuitry for the Bt829A, the analog input traces,
any input amplifiers, and all the digital signal traces leading to the Bt829A.

The Bt829A has digital power (VDD) and analog power (VAA and VPOS). The

layout for the power plane should be such that the two planes are at the same elec-
trical potential, but they should be isolated from each other in the areas surround-
ing the chip. Also, the return path for the current should be through the digital
plane. This is the same layout as shown for the ground plane (Figure 42). When us-
ing a regulator, circuitry must be included to ensure proper power sequencing. The
circuitry shown in Figure 43 illustrates this circuitry layout.

Supply Decoupling

The bypass capacitors should be installed with the shortest leads possible (consis-
tent with reliable operation) to reduce the lead inductance. These capacitors should
also be placed as close as possible to the device.

Each group of VAA and VDD pins should have a 0.1

F ceramic bypass capac-

itor to ground, located as close as possible to the device.

Additionally, 10

F capacitors should be connected between the analog power

and ground planes, as well as between the digital power and ground planes. These
capacitors are at the same electrical potential, but provide additional decoupling by
being physically close to the Bt829A power and ground planes. See Figure 44 for
additional information about power supply decoupling.

Figure 43. Optional Regulator Circuitry

System Power

VAA, VDD

Out

Ground

GND

Suggested Part Numbers:
Regulator

Texas Instruments

A78 MO5M

(+5 V)

System Power

(+5 V)

(+12 V)

Diodes Must Handle

of the Bt829A and the
Peripheral Circuitry

the Current Requirements

Bt829A/827A

VideoStream II Decoders

PC B

OARD

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ONSIDERATIONS

Digital Signal Interconnect

L829A_B

Digital Signal

Interconnect

The digital signals of the Bt829A should be isolated as much as possible from the
analog signals and other analog circuitry. Also, the digital signals should not over-
lay the analog power plane.

Any termination resistors for the digital signals should be connected to the reg-

ular PCB power and ground planes.

Analog Signal

Interconnect

Long lengths of closely spaced parallel video signals should be avoided to mini-
mize crosstalk. Ideally, there should be a ground line between the video signal trac-
es driving the YIN and CIN inputs.

Also, high-speed TTL signals should not be routed close to the analog signals to

minimize noise coupling.

Latch-up Avoidance

Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by
static or impulse voltages on any signal input pin exceeding the voltage on the
power pins by more than 0.5 V, or falling below the GND pins by more than 0.5 V.
Latch-up can also occur if the voltage on any power pin exceeds the voltage on any
other power pin by more than 0.5 V.

In some cases, devices with mixed signal interfaces, such as the Bt829A, can

appear more sensitive to latch-up. In reality, this is not the case. However, mixed
signal devices tend to interact with peripheral devices such as video monitors or
cameras that are referenced to different ground potentials, or apply voltages to the
device prior to the time that its power system is stable. This interaction sometimes
creates conditions amenable to the onset of latch-up.

To maintain a robust design with the Bt829A, the following precautions should

be taken:

Apply power to the device before or at the same time as the interface cir-
cuitry.

Do not apply voltages below GND0.5 V, or higher than VAA+0.5 V to
any pin on the device. Do not use negative supply op-amps or any other
negative voltage interface circuitry. All logic inputs should be held low
until power to the device has settled to the specified tolerance.

Connect all VDD, VAA and VPOS pins together through a low imped-
ance plane.

Connect all GND, AGND and VNEG pins together through a low imped-
ance plane.

Sample Schematics

Figures 45 through 47c are example schematics which detail the interface of the
Bt829A to Cirrus Logic, S3, and Trident VGA controllers. For interfacing to ATI
VGA controllers, please contact ATI Technologies. For interfacing to all other
VGA controllers, please contact your local Rockwell Semiconductor sales office.

PC B

OARD

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ONSIDERATIONS

Sample Schematics

L829A_B

Bt829A/827A

VideoStream II Decoders

Figure 45. Bt829/Cirrus Logic 544x VGA Interface Schematic

I2C ADDR

ESS

0x8

8 WITHOUT SHUNT

x8A WITH SHUNT

INSTALL RESISTOR IF

BOTH CRYSTALS PRESENT

B A X

YOUT

0 XY0

1 XY1

0 XY2

1 XY3

MUTE T

UNER

MUTE

LINE

SELECT TUN

SELECT L

INE

ANTENNA INPU

I2C ADDR

ESS

8A WITHOUT SHUNT

0x80 WITH SHUN

Ground

s are sperated by

air g

aps in the plane.

Tuesday, October 01, 1996

DECODE3.SCH

544X TV TUNER PCI BOARD

Pixel Semiconductor

5068 W. Plano Pkwy Suite 350

Plano, Tx. 75093

Title

Size

Document Number

Rev

Date:

Shee

t of

VSET

VOUT

VT
VT

+9V

AVDD
AVDD

ISWC

LOUT

+12V CONV

ROUT

AudioSel

RSC

AudioMute

AuxOutL
AuxOutL

MAL

AuxInL
AuxInL

+5 TUNER
+5 TUNER

CTA

AuxOutR
AuxOutR

MAR

TVideo

AuxInR
AuxInR

TAudio

AUDIO_IN_R
AUDIO_IN_R

AUDIO_IN_L
AUDIO_IN_L

AUDIO_OUT_R
AUDIO_OUT_R

AUDIO_OUT_L
AUDIO_OUT_L

CAUDIOL

CompV
CompV

CAUDIOR

ChromV
ChromV

Chromin
Chromin

LumV
LumV

Lumin
Lumin

Compos

VAct

Valid

Active

HRef
HRef

VactEna*

VRef
VRef

QVAct

ClkX2

BtEna*
BtEna*

AudioSel

AudioMute

P[0..7]
P[0..7]

12VL

VCC

+12V

VDD

VAA

VCC

+12V

AGND

VCC

2.2uF

33uH

43FS

R12

56K

805

C29

560pF

805

MC34063

8 SO

COMP

PWR

IPK

GND

TCAP

ISWE

ISWC

I D C

22K

805

L13

33uH

43FS

C25

10uF

35V

TUNER2

FI1236

VIDEO IN

+33V

+5V

SCL

SDA

VIDEO OUT

+5V IF

AUDIO

C62

2.2uF

16V

L11

33uH

43FS

1N4003

DO-41

R22

805

C31

33pF

805

C50

.1uF

805

C56

22pF

805

C61

.1uF

805

C69

22pF

805

C57

33pF

805

30K

805

30K

805

R17

805

C66

.1uF

805

C18

.1uF

805

C55

.1uF

805

C16

.1uF

805

BT829

100qfp

YIN

SYNCDET

MUX0

MUX1

MUX2

MUXOUT

CIN

AGCCAP

REFOUT

YREF+

YREF-

CREF+

CREF-

CLEVEL

YABIAS

YCBIAS

YDBIAS

CABIAS

CCBIAS

CDBIAS

VD15

VD14

VD13

VD12

VD11

VD10

VD9

VD8

VD7

VD6

VD5

VD4

VD3

VD2

VD1

VD0

CLKX1

CLKX2

DVALID

HRESET

VRESET

ACTIVE

QCLK

FIELD

CBFLAG

CCVALID

VACTIVE

PWRDN

NUMXTAL

XT0

XT1

RST

SCL

SDA

I2CCS

TRST

TMS

TDO

TDI

TCK

.01uF

805

C65

10uF

C53

10uF

R15

2.2K

805

R25

805

R18

805

R21

1.6K

805

3.3mH

8RB

3.3uH

805

R16

805

R13

805

C13

330pF

805

C27

330pF

805

C30

.1uF

805

C54

.1uF

805

L10

2.7uH

805

2.2uH

805

U10

FCT253

SO16

1C0

1C1

1C2

1C3

2C0

2C1

2C2

2C3

R51

6.8K

R50

805

JP3

MINIDIN 9

mdin9

U11

PCF8574

SO16W

SDA

SCL

L12

3.3uH

805

C58

330pF

805

C60

330pF

805

R23

805

C59

.1uF

805

3.3uH

805

C47

.1uF

805

C26

330pF

805

C48

330pF

805

C49

.1uF

805

330

805

C14

.1uF

805

C15

.1uF

805

.1uF

805

C17

.1uF

805

FB3

60 OHM

1210

FB4

60 OHM

1210

FB6

60 OHM

1210

FB5

60 OHM

1210

FB9

60 OHM

1210

FB7

60 OHM

1210

FB8

60 OHM

1210

33uH

43FS

C81

100uF

C098

16V

C76

.1uF

805

50V

U12

78L09

to-92

R E F

OUT

C72

1uF

16V

C84

.47uF-T

35V

R54

2.2K

805

C96

.33uF

1206

50V

R14

43K

805

C21

1uF

16V

3.9K

805

C41

3.3uF

25V

C42

.047uF

1206

50V

805

C23

2700pF

805

R10

3.3K

805

R11

200K

805

R19

10K

805

50V

R20

10K

805

50V

R26 10K

805

50V

R27

10K

805

50V

MC14052B

16soic

INH

V D D

V S S

V E E

JP4

HEADER 4

4x1hdr

FB1

60 OHM

SM121

FB2

60 OHM

SM1210

CXA1734S

30sdip

SDA

SCL

D G N D

A G N D

1 7

V C C

SAD

VGR

IREF

MAININ

MAINOUT

PLINT

STFIL

COMPIN

SAPTC

SUBOUT

STIN

NOISETC

SAPOUT

SAPIN

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

ITIME

ROUT

LOUT

C71

10uF

RadialA

50V

C77

10uF

RadialA

50V

C78

10uF

RadialA

50V

C73

.22uF-T

35V

C79

4.7uF

RadialA

50V

C75

10uF

RadialA

50V

C80

10uF

RadialA

50V

C44

4.7uF

RadialA

50V

C43

10uF

RadialA

50V

C24

10uF

RadialA

50V

C22

10uF

RadialA

50V

C40

10uF

RadialA

50V

C39

10uF

RadialA

50V

C52

4.7uF

RadialA

50V

C70

4.7uF

RadialA

50V

C10

4.7uF

RadialA

50V

C11

4.7uF

RadialA

50V

C74

4.7uF

RadialA

50V

C12

100pF

805

50V

100pF

805

50V

10pF

805

50V

10pF

805

50V

R24

805

R48

Option 1K

805

NOT INSTALLED

R55

330

805

C46

100pF

805

50V

C45

100pF

805

50V

C38

10uF

RadialA

50V

C51

.1uF

805

50V

33uH

43FS

R56

4.7K

805

R28

62K

805

TP3

HDR1X1

TP1

HDR1X1

TP2

HDR1X1

35.46895

HC49

28.63636

HC49

R52 10K

805

50V

R53 10K

805

50V

R84

VAOpt 33

805

C83

4.7uF

RadialA

50V

EVIDEO*

BLANK*

DCLK

P[0..7]

RST*

I2CDAT

VIDEO1

VIDEO2

I2CCLK

VREF

I2CDAT

I2CCLK

I2CDAT

PC B

OARD

AYOUT

ONSIDERATIONS

Sample Schematics

L829A_B

Bt829A/827A

VideoStream II Decoders

Figure 46b.Bt829/S3 Virge 8-Bit Interface Schematic - Bt829 Detail

DECODER

Wednesday, October 04, 1995

85-000114-00-0

Bt829 - S3 8BIT

Wednesday, October 16, 1996

Title

Size

Document Number

Rev

Date:

Sheet

VS (

204)

LLC (148)

SPD

(206)

MUX1

SPC

LK (205)

MUX2

SET

(203)

LD7 (202)

LD6 (184)

LD5 (175)

LD4 (174)

LD3 (155)

LD2 (154)

LD1 (147)

LD0 (146)

VCC

0.1u

0805

30K

0805

080

0.1u

080

1M 0805

0.1u

080

0.1

080

0.1

080

2.2

0805

28.63

636

e spec

0.1u

0805

0.1

0805

22pf

080

2.7uH

10%

0805

080

0805

2.2

0805

.46895 MHZ

e spec

0.1

0805

22pf

080

2.2uH

10%

0805

0PQFP

Bt829

Bt827

RST

VAA

AGND

VD15

VD14

VD13

VD12

VD11

VD10

VD9

VD8

VD7

VD6

VD5

VD4

VD3

VD2

VD1

VD0

FIELD

VAA

TDO

CIN

MUX1

MUX0

SYN

CDET

YRE

F+

EF-

TDI

TMS

TCK

XT0I

XT0

XT1I

XT1

GND

VAA

AGND

VAA

AGND

MUXOUT

REFO

CBFLAG

HRESET

VRESET

ACTIVE

DVALID

CLKX1

CLKX2

VDD

NUMXTAL

VDD

TRST

SDA

SCL

I2CCS

YIN

YABIAS

YDBIAS

YCBIAS

MUX2

VPOS

VNEG

AGCC

GND

CCVALID

VACTIVE

GND

P W R D N

QCLK

CRE

F+

CLEVE

CABIAS

CCBIAS

CDBIAS

EF-

AGND

VAA

AGND

VDD

GND

VDD

GND

100

GND

Bt829A/827A

VideoStream II Decoders

PC B

OARD

AYOUT

ONSIDERATIONS

Sample Schematics

L829A_B

Figure 47a.Bt829/Trident VGA Interface Schematic - TV Tuner and Video Input Detail

VAFC

STANDARD FEATURE

CONNECTOR

EXTENDED FEATURE

CONNECTOR

VIDEO

INTERFACE

Wednesday, October 04, 1995

85-000112-00-0

Bt TRIDENT2

Tuesday, July 01, 1997

Title

Size

Document Number

Rev

Date:

Sheet

PX[0:15]

YSCL

YSDA

YVS

YHS

YCLK

XSD

SDA

YSDA

PX11

PX1

PX15

PX12

XSC

SCL

YSCL

XSC

XSD

XHS

XVS

PX13

PX15

PX14

PX12

PX11

PX10

XCL

PX1

PX9

PX1

SDA

SCL

ESET

VRE

SET

VRE

SET

ESET

QCLK

+12

VCC

+12

CON10

CON2

CH_80

N10

N11

N12

N13

N29

M10

M11

M12

M13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

N27

N28

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

M31

M32

M33

M34

M35

M36

M37

M38

M39

M40

N30

N31

N32

N33

N34

N35

N36

N37

N38

N39

N40

CON

IOCH_26

Y10

Y11

Y12

Y13

10uF

6032

0.1u

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0.1

080

0805

080

0805

CON

IOCH_20

Y10

0805

10u

603

10uF

603

10uF

603

C57

10uF

6032

10uF

603

C50

10uF

6032

C84

10uF

6032

0.1u

0805

CON10B

PC B

OARD

AYOUT

ONSIDERATIONS

Sample Schematics

L829A_B

Bt829A/827A

VideoStream II Decoders

Figure 47b.Bt829/Trident VGA Interface Schematic - Bt829 Detail

33 Oh

m 16 places 0805 R49 - R64

DECODER

Wednesday, October 04, 1995

85-000112-00-0

Bt TRIDENT2

Tuesday, July 01, 1997

Title

Size

Document Number

Rev

Date:

Sheet

RST

PX1

PX4

PX1

PX7

PX8

PX1

PX9

PX3

PX5

PX1

PX0

PX6

PX1

PX2

ESET

QCLK

NER_VIDEO

COMP

OSITE_VIDEO

VRE

SET

VCC

0.1u

0805

080

0.1u

080

1M 0805

0.1

080

28.63

636

e spec

22pf

080

2.7uH

10%

0805

C58

0.1u

0805

080

2.2

0805

080

0.1

080

30K

0805

0.1

0805

2.2

080

0.1u

080

0PQFP

Bt829

RST

VAA

AGND

VD15

VD14

VD13

VD12

VD11

VD10

VD9

VD8

VD7

VD6

VD5

VD4

VD3

VD2

VD1

VD0

FIELD

VAA

TDO

CIN

MUX1

MUX0

SYN

CDET

YRE

F+

EF-

TDI

TMS

TCK

XT0I

XT0

XT1I

XT1

GND

VAA

AGND

VAA

AGND

MUXOUT

REFO

CBFLAG

HRESET

VRESET

ACTIVE

DVALID

CLKX1

CLKX2

VDD

NUMXTAL

VDD

TRST

SDA

SCL

I2CCS

YIN

YABIAS

YDBIAS

YCBIAS

MUX2

VPOS

VNEG

AGCC

RDEN

AEF

AFF

GND

CLKIN

QCLK

CRE

F+

CLEVE

CABIAS

CCBIAS

CDBIAS

EF-

AGND

VAA

AGND

FRST

GND

VDD

GND

100

GND

Bt829A/827A

VideoStream II Decoders

PC B

OARD

AYOUT

ONSIDERATIONS

Sample Schematics

L829A_B

Figure 47c.Bt829/Trident VGA Interface Schematic - Feature Connector Detail

COMPOSITE VIDEO CONNECTOR

TUNER

33 VOLT DC - DC CONVERTER

Wednesday, October 04, 1995

85-000112-00-0

Bt TRIDENT2

Tuesday, July 01, 1997

Title

Size

Document Number

Rev

Date:

Sheet

AIN

TUNER_VIDEO

COMP

OSITE_VIDEO

SDA

ESET

SDA

VCC

+12

-12V

10K

22u

734

FB2

2.2

3528

C70

0.1u

0805

.68uf 1

321

330 o

hms

080

RCA

JACK

080

TDA8

425

IN2L

IN2R

AGN

BASR

BSS

OUTR

DGND

SDA

SCL

OUTL

TREL

BASL

BSSL

PSU2

IN1L

PSU1

IN1R

PHONEJACK STERE

R21

100

OHM

0805

1uf

16V

321

22K

080

MMBZ52

57BT1

SOT

-23

10uf

25V

7343

0805

BAV99L

SOT

-23

MMBT3904L

T-23

DEO_TUNER

G_TUNER

TEMI

+5VB

SCL

SDA

IFSOUN

VIDE

O_OUT

+5V

AUDI

O_OUT

GND1

GND2

GND3

GND4

10uf

25V

734

6800p

080

C25

22uF

7343

22uF

7343

22uF

7343

2.2

352

C24

0.1u

0805

0.0

15uf

0805

0.0

33uf

0805

5600p

080

C37

5600p

080

C36

033uf

080

0.0

15uf

0805

L829A_B

ONTROL

EGISTER

EFINITIONS

This section describes the function of the various control registers. Table 13 summarizes of the register functions and
follows with details of each register.

Table 13. Register Map

(1 of 2)

Register Name

Mnemonic

Register Ad

dress

640 x 480

Square Pix

el NTSC

(Default)

768 x 576

Square Pix

el P

AL/SECAM

720 x 480

CCIR NTSC

720 x 576

CCIR P

AL/SECAM

320 x 240 2:1 NTSC

(Square Pix

el,

CIF)

320 x 288 2:1 P

AL/SECAM

(Square Pix

el,

CIF)

Device Status

STATUS

0x00

Input Format

IFORM

0x01

0x58

0x78

0x58

0x78

0x58

0x78

Temporal Decimation

TDEC

0x02

0x00

MSB Cropping

CROP

0x03

0x12

0x23

0x12

0x23

0x11

0x21

Vertical Delay, Lower Byte

VDELAY_LO

0x04

0x16

Vertical Active, Lower Byte

VACTIVE_LO

0x05

0xE0

0x40

0xE0

0x40

0xE0

0x40

Horizontal Delay, Lower Byte

HDELAY_LO

0x06

0x78

0x9A

0x80

0x90

0x40

0x48

Horizontal Active, Lower Byte

HACTIVE_LO

0x07

0x80

0x00

0xD0

0x40

0x80

Horizontal Scaling, Upper Byte

HSCALE_HI

0x08

0x02

0x03

0x00

0x05

0x11

0x1A

Horizontal Scaling, Lower Byte

HSCALE_LO

0x09

0xAC

0x3C

0xF8

0x04

0xF0

0x09

Brightness Control

BRIGHT

0x0A

0x00

Miscellaneous Control

CONTROL

0x0B

0x20

(1)

0x20

(1)

0x20

Luma Gain, Lower Byte
(Contrast)

CONTRAST_LO

0x0C

0xD8

Chroma (U) Gain, Lower Byte
(Saturation)

SAT_U_LO

0x0D

0xFE

Chroma (V) Gain, Upper Byte
(Saturation)

SAT_V_LO

0x0E

0xB4

Hue Control

HUE

0x0F

0x00

SC Loop Control

SCLOOP

0x10

0x00

(1)

0x00

(1)

0x00

Bt829A/827A

VideoStream II Decoders

ONTROL

EGISTER

EFINITIONS

L829A_B

White Crush Up Count

WC_UP

0x11

0xCF

Output Format

OFORM

0x12

0x06

Vertical Scaling, Upper Byte

VSCALE_HI

0x13

0x60

0x40

(2)

0x40

(2)

Vertical Scaling, Lower Byte

VSCALE_LO

0x14

0x00

Test Control

TEST

0x15

0x01

Video Timing Polarity Register

VPOLE

0x16

0x00

ID Code

IDCODE

0x17

0x70

AGC Delay

ADELAY

0x18

0x68

0x7F

0x68

0x7F

0x68

0x7F

Burst Gate Delay

BDELAY

0x19

0x5D

0x72

(1)

0x5D

0x72

(1)

0x5D

0x72

ADC Interface

ADC

0x1A

0x82

Video Timing Control

VTC

0x1B

0x00

Extended Data Services/Closed
Caption Status

CC_STATUS

0x1C

0x00

Extended Data Services/Closed
Caption Data

CC_DATA

0x1D

0x00

White Crush Down Count

WC_DN

0x1E

0x7F

Software Reset

SRESET

0x1F

Programmable I/O

P_IO

0x3F

SECAM Video Register Differences

Miscellaneous Control

CONTROL

0x00

SC Loop Control

SCLOOP

0x10

Burst Gate Delay

BDELAY

0xA0

Notes: (1). SECAM Video Register differences to PAL video.

(2). When using one field, no additional vertical scaling is necessary for CIF resolutions. The INT bit in register

0xB(VSCALE_HI) should be set to a logical zero when scaling from only one field.

Table 13. Register Map

(2 of 2)

Register Name

Mnemonic

Register Ad

dress

640 x 480

Square Pix

el NTSC

(Default)

768 x 576

Square Pix

el P

AL/SECAM

720 x 480

CCIR NTSC

720 x 576

CCIR P

AL/SECAM

320 x 240 2:1 NTSC

(Square Pix

el,

CIF)

320 x 288 2:1 P

AL/SECAM

(Square Pix

el,

CIF)

ONTROL

EGISTER

EFINITIONS

0x00 -- Device Status Register (STATUS)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x00 -- Device Status Register (STATUS)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. COF is
the least significant bit. The COF and LOF status bits hold their values until reset to their default values by writing to
them. The other six bits do not hold their values, but continually output the status. An asterisk indicates the default op-
tion.

PRES

Video Present Status. Video is determined as not present when an input sync is not
detected in 31 consecutive line periods.

= Video not present

= Video present

HLOC

Device in H-lock. If HSYNC is found within

1 clock cycle of the expected posi-

tion of HSYNC for 32 consecutive lines, this bit is set to a logical 1. Once set, if
HSYNC is not found within

1 clock cycle of the expected position of HSYNC for

32 consecutive lines, this bit is set to a logical 0. MPU writes to this bit are ignored.
This bit indicates the stability of the incoming video. While it is an indicator of
horizontal locking, some video sources will characteristically vary from line to line
by more than one clock cycle so that this bit will never be set. Consumer VCRs are
examples of sources that will tend to never set this bit.

= Device not in H-lock

= Device in H-lock

FIELD

Field Status. This bit reflects whether an odd or even field is being decoded. The
FIELD bit is determined by the relationship between HRESET and VRESET.

= Odd field

= Even field

NUML

Number of Lines. This bit identifies the number of lines found in the video stream.
This bit is used to determine the type of video input to the Bt829A. Thirty-two con-
secutive fields with the same number of lines is required before this status bit will
change.

= 525 line format (NTSC/PAL-M)

= 625 line format (PAL/SECAM)

PRES

HLOC

FIELD

NUML

CSEL

CCVALID

LOF

COF

Bt829A/827A

VideoStream II Decoders

ONTROL

EGISTER

EFINITIONS

0x00 -- Device Status Register (STATUS)

L829A_B

CSEL

Crystal Select. This bit identifies which crystal port is selected. When automatic
format detection is enabled, this bit will be the same as NUML.

= XTAL0 input selected

= XTAL1 input selected

CCVALID

Valid Closed Caption Data. This bit indicates that valid closed caption or extended
data services (EDS) sample pairs have been stored in the closed caption data reg-
isters. This bit indicates that the closed caption data FIFO is half full. It is reset af-
ter being written into or a chip reset occurs.

LOF

Luma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow occurs,
the bit is set to a logical 1. It is reset after being written to or a chip reset occurs.
The state of this bit is not valid and should be ignored when the ADC is in pow-
er-down mode (Y_SLEEP = 1). When the luma A/D is in sleep mode, LOF is set
to 1.

COF

Chroma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow oc-
curs, the bit is set to a logical 1. It is reset after being written to or a chip reset oc-
curs. The state of this bit is not valid and should be ignored when the ADC is in
power-down mode (C_SLEEP = 1). When the chroma A/D is in sleep mode, COF
is set to 1.

ONTROL

EGISTER

EFINITIONS

0x01 -- Input Format Register (IFORM)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x01 -- Input Format Register (IFORM)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x58. FOR-
MAT(0) is the least significant bit. An asterisk indicates the default option.

HACTIVE

When using the Bt829A with a packed memory architecture, for example, with
field memories, this bit should be programmed with a logical 1. When implement-
ing a VRAM based architecture, program with a logical 0.

= Reset HACTIVE with HRESET

= Extend HACTIVE beyond HRESET

MUXSEL

Used for software control of video input selection. The Bt829A can select between
four composite video sources, or three composite and one S-Video source.

= Select MUX3 input to MUXOUT

= Select MUX2 input to MUXOUT

10* = Select MUX0 input to MUXOUT
11

= Select MUX1 input to MUXOUT

XTSEL

If automatic format detection is required, logical 11 must be loaded. Logical 01
and 10 are used if software format selection is desired.

= Reserved

= Select XT0 input (only XT0 present)

= Select XT1 input (both XTs present)

11* = Auto XT select enabled (both XTs present)

FORMAT

Automatic format detection may be enabled or disabled. The NUML bit is used to
determine the input format when automatic format detection is enabled.

000*= Auto format detect enabled
001 = NTSC (M) input format
010 = NTSC with no pedestal format
011 = PAL (B, D, G, H, I) input format
100 = PAL (M) input format
101 = PAL (N) input format
110 = SECAM input format
111 = PAL (Ncombination) input format

HACTIVE

MUXSEL

XTSEL

FORMAT

Bt829A/827A

VideoStream II Decoders

ONTROL

EGISTER

EFINITIONS

0x02 -- Temporal Decimation Register (TDEC)

L829A_B

0x02 -- Temporal Decimation Register (TDEC)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00.
DEC_RAT(0) is the least significant bit. This register enables temporal decimation by discarding a finite number of
fields or frames from the incoming video. An asterisk indicates the default option.

DEC_FIELD

Defines whether decimation is by fields or frames.

= Decimate frames

= Decimate fields

FLDALIGN

This bit aligns the start of decimation with an even or odd field.

= Start decimation on the odd field (an odd field is the first field

dropped).

= Start decimation on the even field (an even field is the first field

dropped).

DEC_RAT

DEC_RAT is the number of fields or frames dropped out of 60 NTSC or 50
PAL/SECAM fields or frames. 0x00 value disables decimation (all video frames
and fields are output).

NOTE:

Use caution when changing the programming in the TDEC register. 0x00
must be loaded before the decimation value. This will ensure decimation
does not start on the wrong field or frame. The register should not be load-
ed with greater than 60 (0x3C) for NTSC, or 50 (0x34) for PAL/SECAM.

xx00 0000xx11 1111 = Number of fields/frames dropped.

DEC_FIELD

FLDALIGN

DEC_RAT

ONTROL

EGISTER

EFINITIONS

0x0B -- Miscellaneous Control Register (CONTROL)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x0B -- Miscellaneous Control Register (CONTROL)

This control register may be written to or read by the MPU at any time, and upon reset it is initialized to 0x20.
SAT_V_MSB is the least significant bit. An asterisk indicates the default option.

LNOTCH

This bit is used to include the luma notch filter. For monochrome video, the notch
should not be used. This will output full bandwidth luminance.

= Enable the luma notch filter

= Disable the luma notch filter

COMP

When COMP is set to logical one, the luma notch is disabled. When COMP is set
to logical zero, the C ADC is disabled.

= Composite Video

= Y/C Component Video

LDEC

The luma decimation filter is used to reduce the high-frequency component of the
luma signal. Useful when scaling to CIF resolutions or lower.

= Enable luma decimation using selectable H filter

= Disable luma decimation

CBSENSE

This bit controls whether the first pixel of a line is a Cb pixel or a Cr pixel. For ex-
ample, if CBSENSE is low and HDELAY is an even number, the first active pixel
output is a Cb pixel. If HDELAY is odd, CBSENSE may be programmed high to
produce a Cb pixel as the first active pixel output.

= Normal Cb, Cr order

= Invert Cb, Cr order

Reserved

This bit should only be written with a logical zero.

CON_MSB

The most significant bit of the luma gain (contrast) value.

SAT_U_MSB

The most significant bit of the chroma (u) gain value.

SAT_V_MSB

The most significant bit of the chroma (v) gain value.

LNOTCH

COMP

LDEC

CBSENSE

Reserved

CON_MSB

SAT_U_MSB

SAT_V_MSB

ONTROL

EGISTER

EFINITIONS

0x0D -- Chroma (U) Gain Register, Lower Byte (SAT_U_LO)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x0D -- Chroma (U) Gain Register, Lower Byte (SAT_U_LO)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xFE.
SAT_U_LO(0) is the least significant bit. SAT_U_MSB in the CONTROL register, and SAT_U_LO concatenate to
give a 9-bit register (SAT_U). This register is used to add a gain adjustment to the U component of the video signal.
By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For
normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the
value in the U gain register and the value in the V gain register should be kept constant at the default power-up ratio).
When changing the saturation, if the SAT_U_MSB bit is altered, care must be taken to ensure that the other bits in the
CONTROL register are not affected.

SAT_U_LO

SAT_U_LO

Decimal Value

Hex Value

% of Original Signal

511

0x1FF

201.18%

510

0x1FE

200.79%

.
.

255

0x0FF

100.39%

254

0x0FE

100.00%

.
.

128

0x080

50.39%

.
.

0x001

0.39%

0x000

0.00%

Bt829A/827A

VideoStream II Decoders

ONTROL

EGISTER

EFINITIONS

0x0E -- Chroma (V) Gain Register, Lower Byte (SAT_V_LO)

L829A_B

0x0E -- Chroma (V) Gain Register, Lower Byte (SAT_V_LO)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xB4.
SAT_V_LO(0) is the least significant bit. SAT_V_MSB in the CONTROL register and SAT_V_LO concatenate to
give a 9-bit register (SAT_V). This register is used to add a gain adjustment to the V component of the video signal.
By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For
normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the
value in the U gain register and the value in the V gain register should be kept constant at the default power-up ratio).
When changing the saturation, if the SAT_V_MSB bit is altered, care must be taken to ensure that the other bits in the
CONTROL register are not affected.

SAT_V_LO

SAT_V_LO

Decimal Value

Hex Value

% of Original Signal

511

0x1FF

283.89%

510

0x1FE

283.33%

.
.

181

0x0B5

100.56%

180

0x0B4

100.00%

.
.

128

0x080

71.11%

.
.

0x001

0.56%

0x000

0.00%

Bt829A/827A

VideoStream II Decoders

ONTROL

EGISTER

EFINITIONS

0x10 -- SC Loop Control (SCLOOP)

L829A_B

0x10 -- SC Loop Control (SCLOOP)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. ACCEL
is the least significant bit. An asterisk indicates the default option.

PEAK

This bit determines if the normal luma low pass filters are implemented via the
HFILT bits or if the peaking filters are implemented. The LDEC bit in the control
register must be programmed to zero to use these filters.

= Normal luma low pass filtering

= Use luma peaking filters

CAGC

This bit controls the Chroma AGC function. When enabled, Chroma AGC will
compensate for non-standard chroma levels. The compensation is achieved by
multiplying the incoming chroma signal by a value in the range of 0.5 to 2.0.

= Chroma AGC Disabled

= Chroma AGC Enabled

CKILL

This bit determines whether the low color detector and removal circuitry is en-
abled.

= Low Color Detection and Removal Disabled

= Low Color Detection and Removal Enabled

PEAK

CAGC

CKILL

HFILT

Reserved

ONTROL

EGISTER

EFINITIONS

0x12 -- Output Format Register (OFORM)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x12 -- Output Format Register (OFORM)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x06. OES(0)
is the least significant bit. An asterisk indicates the default option.

RANGE

Luma Output Range: This bit determines the range for the luminance output on the
Bt829A. The range must be limited when using the control codes as video timing.

= Normal operation (Luma range 16253, chroma range 2253).

Y=16 is black (pedestal)
Cr, Cb=128 is zero color information

= Full-range Output (Luma range 0255, chroma range 2253)

Y=0 is black (pedestal)
Cr, Cb=128 is zero color information

CORE

Luma Coring: These bits control the coring value used by the Bt829A. When cor-
ing is active and the total luminance level is below the limit programmed into these
bits, the luminance signal is truncated to zero.

00* = 0x00 no coring
01

= 8

= 16

= 32

VBI_FRAME

This bit enables the VBI Frame output mode. In the VBI Frame output mode, every
line consists of unfiltered 8*Fsc non-image data. This bit supersedes bit VBIEN in
the VTC register. VBIFMT (also in VTC) works in both VBI Frame and Line out-
put modes.

= VBI Frame output mode disabled

= VBI Frame output mode enabled

CODE

Code Control Disable: This bit determines if control codes are output with the vid-
eo data. SPI Mode 2 requires this bit to be programmed with a logical 1. When con-
trol codes are inserted into the data stream, the external control signals are still
available.

= Disable control code insertion

= Enable control code insertion

RANGE

CORE

VBI_FRAME

CODE

LEN

OES

101

ONTROL

EGISTER

EFINITIONS

0x13 -- Vertical Scaling Register, Upper Byte (VSCALE_HI)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x13 -- Vertical Scaling Register, Upper Byte (VSCALE_HI)

This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x60. An asterisk
indicates the default option.

YCOMB

Luma Comb Enable: When enabled, the luma comb filter performs a weighted av-
erage on 2, 3, 4, or 5 lines of luminance data. The coefficients used for the average
are fixed and no interpolation is performed. The number of lines used for the luma
comb filter is determined by the VFILT bits in the VTC register. When disabled by
a logical zero, filtering and full vertical interpolation is performed based upon the
value programmed into the VSCALE register. The LUMA comb filter cannot be
enabled on the Bt827A.

= Vertical low-pass filtering and vertical interpolation

= Vertical low-pass filtering only

COMB

Chroma Comb Enable: This bit determines if the chroma comb is included in the
data path. If enabled, a full line store is used to average adjacent lines of color in-
formation, reducing cross-color artifacts.

= Chroma comb disabled

= Chroma comb enabled

INT

Interlace: This bit is programmed to indicate if the incoming video is interlaced or
non-interlaced. For example, if using the full frame as input for vertical scaling,
this bit should be programmed high. If using a single field for vertical scaling, this
bit should be programmed low. Single field scaling is normally used when scaling
below CIF resolution and outputting to a non-interlaced monitor. Using a single
field will reduce motion artifacts.

= Non-interlace VS

= Interlace VS

VSCALE_HI

Vertical Scaling Ratio: These five bits represent the most significant portion of the
13-bit vertical scaling ratio register. The system must take care not to alter the con-
tents of the LINE, COMB and INT bits while adjusting the scaling ratio.

YCOMB

COMB

INT

VSCALE_HI

Bt829A/827A

VideoStream II Decoders

104

ONTROL

EGISTER

EFINITIONS

0x16 -- Video Timing Polarity Register (VPOLE)

L829A_B

0x16 -- Video Timing Polarity Register (VPOLE)

This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. An asterisk
indicates the default option.

OUTEN

Three-states the pins defined by OES in the OFORM register. The affected pins
are: VD[15:0], HRESET, VRESET, ACTIVE, VACTIVE, DVALID, CBFLAG,
FIELD, QCLK, CLKx1, and CLKx2.

When Pin 85 is a logical zero

= Enable outputs

= Three-state outputs

When Pin 85 is a logical one

= Three-state outputs

= Enable outputs

DVALID

= DVALID Pin: Active high

= DVALID Pin: Active low

VACTIVE

= VACTIVE Pin: Active high

= VACTIVE Pin: Active low

CBFLAG

= CBFLAG Pin: Active high

= CBFLAG Pin: Active low

FIELD

= FIELD Pin: High indicates odd field

= FIELD Pin: High indicates even field

ACTIVE

= ACTIVE Pin: Active high

= ACTIVE Pin: Active low

HRESET

= HRESET Pin: Active low

= HRESET Pin: Active high

VRESET

= VRESET Pin: Active low

= VRESET Pin: Active high

OUT_EN

DVALID

VACTIVE

CBFLAG

FIELD

ACTIVE

HRESET

VRESET

Bt829A/827A

VideoStream II Decoders

108

ONTROL

EGISTER

EFINITIONS

0x1A -- ADC Interface Register (ADC)

L829A_B

0x1A -- ADC Interface Register (ADC)

This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x82. Reserved
is the least significant bit. An asterisk indicates the default option.

Reserved

These bits should only be written with bit 7 a logical one and bit 6 a logical zero.

SYNC_T

This bit defines the voltage level below which the SYNC signal can be detected.

= Analog SYNCDET threshold high (~125 mV)

= Analog SYNCDET threshold low (~75 mV)

AGC_EN

This bit controls the AGC function. If disabled, REFOUT is not driven and an ex-
ternal reference voltage must be provided. If enabled, REFOUT is driven to control
the A/D reference voltage.

= AGC Enabled

= AGC Disabled

CLK_SLEEP

When this bit is at a logical one, the system clock is powered down, but the output
clocks (CLKx1 and CLKx2) are still running, and the I

C registers are still acces-

sible. Recovery time is approximately one second.

= Normal Clock Operation

= Shut down the System Clock (Power Down)

Y_SLEEP

This bit enables putting the luma ADC in sleep mode.

= Normal Y ADC operation

= Sleep Y ADC operation

C_SLEEP

This bit enables putting the chroma ADC in sleep mode.

= Normal C ADC operation

= Sleep C ADC operation

CRUSH

This bit enables white crush mode, and must be written with a logical zero.

= Normal SYNC level to white level

= Enable white CRUSH mode to compensate for nonstandard

SYNC to white video relationship

Reserved

SYNC_T

AGC_EN

CLK_SLEEP

Y_SLEEP

C_SLEEP

CRUSH

109

ONTROL

EGISTER

EFINITIONS

0x1B -- Video Timing Control (VTC)

L829A_B

Bt829A/827A

VideoStream II Decoders

0x1B -- Video Timing Control (VTC)

This register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. VFILT(0) is the
least significant bit. An asterisk indicates the default option.

HSFMT

This bit selects between a single-pixel-wide HRESET and the standard
64-clock-wide HRESET.

= HRESET is 64 CLKx1 cycles wide

= HRESET is 1 pixel wide

ACTFMT

This bit selects whether composite ACTIVE (HACTIVE and VACTIVE) or HAC-
TIVE only is output on the ACTIVE pin.

= ACTIVE is composite active

= ACTIVE is horizontal active

CLKGATE

This bit selects the signals that are gated with CLK to create QCLK. If logical zero
is selected, the ACTIVE pin (composite ACTIVE or HACTIVE) is used in gating
CLK.

= CLKx1 and CLKx2 are gated with DVALID and ACTIVE to

create QCLK.

= CLKx1 and CLKx2 are gated with DVALID to create QCLK.

VBIEN

This bit enables VBI data to be captured.

= Do not capture VBI

= Capture VBI

VBIFMT

This bit determines the byte ordering for VBI data.

= Pixel N on the VD[15:8] data bus, pixel N+1 on the VD[7:0] data

bus.

= Pixel N+1 on the VD[15:8] data bus, Pixel N on the VD[7:0] data

bus (Pixel N refers to the 1st, 3rd, 5th..., while pixel N+1 refers to
the 2nd, 4th, 6th in a horizontal line of video.)

HSFMT

ACTFMT

CLKGATE

VBIEN

VBIFMT

VALIDFMT

VFILT

Bt829A/827A

VideoStream II Decoders

110

ONTROL

EGISTER

EFINITIONS

0x1B -- Video Timing Control (VTC)

L829A_B

VALIDFMT

= Normal DVALID timing

= DVALID is the logical AND of VALID and ACTIVE, where

ACTIVE is controlled by the ACTFMT bit. Also, the QCLK
signal will free turn and is an inverted version of CLKx1 or
CLKx2, depending upon whether 8- or 16-bit pixel output format
is selected.

VFILT

These bits control the number of taps in the Vertical Scaling Filter. The number of
taps must be chosen in conjunction with the horizontal scale factor to ensure the
needed data does not overflow the internal FIFO.

If the YCOMB bit in the VSCALE_HI register is a logical one, the following

settings and equations apply:

00* = 2-tap

Available at all resolutions.

= 3-tap

Only available if scaling to less than 385

horizontal active pixels for PAL or 361 for NTSC (CIF or
smaller).

= 4-tap

Only available if scaling to less

than 193 horizontal active pixels for PAL or 181 for NTSC
(QCIF or smaller)

= 5-tap

Only available if scaling to

less than 193 horizontal active pixels for PAL or 181 for NTSC
(QCIF or smaller).

If the YCOMB bit in the VSCALE_HI register is a logical zero, the following

settings and equations apply:

00* = 2-tap interpolation only. Available at all resolutions.

= 2-tap

and 2-tap interpolation. Only available if scaling

to less than 385 horizontal active pixels for PAL or 361 for NTSC
(CIF or smaller).

= 3-tap

and 2-tap interpolation. Only available if

scaling to less than 193 horizontal active pixels for PAL or 181
for NTSC (QCIF or smaller).

= 4-tap

and 2-tap interpolation. Only

available if scaling to less than 193 horizontal active pixels for
PAL or 181 for NTSC (QCIF or smaller).

NOTE:

The Bt827A can only be used with a VFILT value of 00, as it does not
have a vertical scaling filter.

1
2

--- 1

(

)

1
4

--- 1

(

)

1
8

--- 1

(

)

------ 1

(

)

1
2

--- 1

(

)

1
4

--- 1

(

)

1
8

--- 1

(

)

111

ONTROL

EGISTER

EFINITIONS

0x1C -- Extended Data Service/Closed Caption Status Register

L829A_B

Bt829A/827A

VideoStream II Decoders

0x1C -- Extended Data Service/Closed Caption Status Register
(CC_STATUS)

This register may be written or read by the MPU at any time. Upon reset, the value of register bits 7, 1, and 0 are in-
determinate because their status depends on the incoming CC/EDS data. Having register bits 6, 5 and 4 at their reset
value causes the CC/EDS circuitry to be powered down. LO_HI is the least significant bit. An asterisk indicates the
default option.

PARITY_ERR

This bit corresponds to the current word in CC_DATA.

= No error

= Odd parity error

NOTE:

Closed caption data is transmitted using odd parity.

CCVALID_EN

This bit serves as a mask for the CCVALID interrupts pin.

= Disabled CCVALID interrupts pin

= Enabled CCVALID interrupts pin

EDS

This bit determines if EDS data is written into the CC_DATA FIFO.

= EDS data is not written into the CC_DATA FIFO

= EDS data is written into the CC_DATA FIFO

This bit determines if CC data is written into the CC_DATA FIFO.

= CC data is not written into the CC_DATA FIFO

= CC data is written into the CC_DATA FIFO

This bit indicates the CC_DATA FIFO is full and EDS or CC data has been lost.
This bit is read only. On reset or read of CC_DATA this bid is set to zero.

= An overflow has not occurred since this bit was last reset

= An overflow has occurred

CC/EDS data available. This bit indicates if there is valid data in the CC_DATA
FIFO. This bit is read only. On reset, this bit is set to zero.

= FIFO is empty

= One or more bytes available

PARITY_ERR CCVALID_EN

EDS

CC_EDS

LO_HI

Bt829A/827A

VideoStream II Decoders

116

ONTROL

EGISTER

EFINITIONS

0x3F -- Programmable I/O Register (P_IO)

L829A_B

0x3F -- Programmable I/O Register (P_IO)

This control register may be written to or read by the MPU at any time, and upon reset is initialized to 0x00. OUT_0
is the least significant bit. While in 8-bit output mode (SPI-8), the VD[7:0] pins are completely asynchronous. IN[3:0]
represent the digital levels input on VD[7:4], while the values programmed into OUT[3:0] are output onto VD[3:0]

IN[3:0]

These input bits can be used to monitor external signals from VD[7:4]. The Pro-
grammable I/O register is only accessible in the 8-bit 4:2:2 YCrCb output mode
(LEN=0). If not in the 8-bit output mode, the values returned by the IN[3:0] bits are
not valid.

OUT[3:0]

These output bits can be programmed to output miscellaneous additional signals
from the video decoder on VD[3:0]. The Programmable I/O register is only acces-
sible in the 8-bit 4:2:2 YCrCb output mode. If not in the 8-bit output mode, the
OUT[3:0] bits will be set to logical zero.

IN_3

IN_2

IN_1

IN_0

OUT_3

OUT_2

OUT_1

OUT_0

117

L829A_B

ARAMETRIC

NFORMATION

DC Electrical Parameters

Table 14. Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Units

Power Supply -- Analog

4.75

5.00

5.25

Power Supply -- Digital

4.75

5.00

5.25

Maximum

0.5

MUX0, MUX1 and MUX2 Input Range
(AC coupling required)

0.5

1.00

2.00

VIN Amplitude Range (ac coupling required)

0.5

1.00

2.00

Ambient Operating Temperature

+70

°C

Table 15. Absolute Maximum Ratings

Parameter

Symbol

Min

Typ

Max

Units

(measured to AGND)

7.00

(measured to DGND)

7.00

Voltage on any signal pin (See the note below)

DGND 0.5

+ 0.5

Analog Input Voltage

AGND 0.5

+ 0.5

Storage Temperature

+150

°C

Junction Temperature

+125

°C

Vapor Phase Soldering
(15 Seconds)

VSOL

+220

°C

Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and func-

tional operation at these or any other conditions above those listed in the operational section of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD-sensi-

tive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V or drops below
ground by more than 0.5 V can induce destructive latch-up.

Bt829A/827A

VideoStream II Decoders

120

ARAMETRIC

NFORMATION

AC Electrical Parameters

L829A_B

CLKx1 Duty Cycle
CLKx2 Duty Cycle
CLKx2 to CLKx1 Delay
CLKx1 to Data Delay
CLKx2 to Data Delay
CLKx1 (Falling Edge) to QCLK (Rising Edge)
CLKx2 (Falling Edge) to QCLK (Rising Edge)
8-bit Mode

(1)

Data to QCLK (Rising Edge) Delay
QCLK (Rising Edge) to Data Delay

16-bit Mode

(1)

Data to QCLK (Rising Edge) Delay
QCLK (Rising Edge) to Data Delay

4
5
6
41
42

7b
8b

7a
8a

45
40
0
3
3
0
0

5
15

14
25

55
60
2
11
11
8
8

%
%
ns
ns
ns
ns
ns

ns
ns

Notes: (1). Because QCLK is generated with a gated version of CLKx1 or CLKx2, the timing in symbols 7 and 8 are sub-

ject to changes in the duty cycle of CLKx1 and CLKx2. If crystals are used as clock sources for the Bt829A,
the duty cycle is symmetric. This assumption is used to generate the timing numbers shown in 7 and 8. For
non-symmetric clock sources, use the following equations:

Table 17. Clock Timing Parameters (2 of 2)

Parameter

Symbol

Min

Typ

Max

Units

Data to QCLK (setup) (16-bit
mode)

xtal period + clkx1 to qclk (max) - clkx1 to data (max)
or
symbol 1 + symbol 41 (max) - symbol 5 (max)

NTSC: 34.9 nS + 8 nS - 11 nS = 31.9 nS
PAL: 28.2 nS + 8 nS -11 nS = 25.2 nS

QCLK to Data (hold) (16-bit mode)

xtal period - clkx1 to qclk (min) + clkx1 to data (min)
or
symbol 1 - symbol 41 (min) + symbol 5 (min)

NTSC: 34.9 nS - 0 nS + 3 nS = 37.9 nS
PAL: 28.3 nS - 0 nS + 3 nS = 31.3 nS

Data to QCLK (setup) (8-bit mode)

(xtal period)/2 + clkx2 to qclk (max) - clkx2 to data (max)
or
(symbol 1)/2 + symbol 42 (max) - symbol 6 (max)

NTSC: 17.5 nS + 8nS - 11 nS = 14.5 nS
PAL: 14.1 nS + 8 nS - 11 nS = 11.1 nS

QCLK to data (hold) (8-bit mode)

(xtal period)/2 - clkx2 to qclk (min) + clkx2 to data (min)
or
(symbol 1)/2 - symbol 42 (min) + symbol 6 (min)

NTSC: 17.5 nS - 0 nS + 3 nS = 20.5 nS
PAL: 14.1 nS - 0 nS + 3 nS = 17.1 nS

Bt829A/827A

VideoStream II Decoders

122

ARAMETRIC

NFORMATION

AC Electrical Parameters

L829A_B

Figure 49. Output Enable Timing Diagram

Pixel, Clock

and

Control Data

Table 20. JTAG Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units

TMS, TDI Setup Time
TMS, TDI Hold Time
TCK Asserted to TDO Valid
TCK Asserted to TDO Driven
TCK Negated to TDO Three-stated
TCK Low Time
TCK High TIme

12
13
14
15
16
17
18

25
25

10
10
60
5
80

ns
ns
ns
ns
ns
ns
ns

Figure 50. JTAG Timing Diagram

TDI, TMS

TCK

TDO

Table 21. Decoder Performance Parameters

Parameter

Symbol

Min

Typ

Max

Units

Horizontal Lock Range

% of Line Length

Fsc, Lock-in Range

800

Gain Range

Note: Test conditions (unless otherwise specified): "Recommended Operating Conditions." TTL input values are 03 V,

with input rise/fall times

3 ns, measured between the 10% and 90% points. Timing reference points at 50% for

digital inputs and outputs. Pixel and control data loads

30 pF and

10 pF. CLKx1 and CLKx2 loads

50 pF. Con-

trol data includes CBFLAG, DVALID, ACTIVE, VACTIVE, HRESET, VRESET and FIELD.

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For more information:
Call 1-800-854-8099

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L829A_B
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