32K x 8
Radiation Hardened Programmable
Read Only Memory (PROM) 5 V
197A807
BAE SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Product Description
Radiation
Fabricated with Bulk CMOS 0.8 m Process
Total Dose Hardness through 2x10
5
rad(Si)
Neutron Hardness through 1x10
12
N/cm
2
SEU Immune (No Latches)
Latchup Free
Features
Other
Read/Write Cycle Times
45 ns (-55 C to 125C)
SMD Number 5962R96891
Asynchronous Operation
CMOS or TTL Compatible I/O
Single 5 V 10% Power Supply
Low Operating Power
Packaging Options
28-Lead Flat Pack (0.500" x 0.720")
General Description
The 32K x 8 radiation hardened PROM is
pinout, function and package compatible with
commercial 28C256 series 32K x EEPROMs,
such as SEEQ 28C256 and Atmel AT28C256.
The PROM is fabricated with BAE SYSTEMS'
QML-qualified radiation hardened technology,
and is designed for use in systems operating in
radiation environments.
The radiation hardened
Oxide-Nitride-Oxide (ONO) anti-fuse technology
features 0.8 micron, 5 V transistors in the data
path, and 1.0 micron, high voltage N and PFETs
in the programming path circuitry. The PROM
operates over the full military temperature
range, requires a single 5 V 10% power
supply, and is available with either TTL or
CMOS compatible I/O. Power consumption is
typically 15 mW/MHz in operation and is less
than 10 mW/MHz in the low power disabled
mode. The PROM operation is fully
asynchronous, with an associated typical
access time of 27 nanoseconds. Synchronous
operation is also possible using CE as a clock.
BAE SYSTEMS' enhanced bulk CMOS
technology is radiation hardened through the
use of advanced and proprietary design, layout,
and process hardening techniques.
2
Functional Diagram
Signal Definitions
A: 0-14
DQ: 0-7
OE
Address input pins that select a particular
eight-bit word within the memory array.
Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
Negative output enable, when at a high level,
holds the data output drivers in a high
impedance state. In programming mode, with
OE high and CE low, data driver state is in
"Data-In" to enable programming.
Chip enable, when at a low level with OE at low
level, allows normal operation. When at a high
level, CE forces the data output drivers in a high
impedance state.
CE
Truth Table
*PROM Programming Voltage
Column Decoders
Section Select
Control Logic
Row Decoders
I/O Buffers
Memory Array
Column Muxing
and
Sense Amps
A0 - A4
DQ0 - 7
A12 - A14
OE
CE
VPP*
A5 - A11
Mode
Inputs
(1),(2)
Power
(3)
Active
Active
Standby1
Standby2
High
CE
Low
Low
V
DD
Low
OE
Low
High
X
X
High
VPP
V
DD
V
DD
V
DD
V
DD
17V 0.5V
I/O
Data-Out
High-Z
High-Z
High-Z
Data-In
Programming
Standby
Read
Tristate
Standby
Program
Notes:
1) V
IN
for don't care (X) inputs = V
IL
or V
IH
.
2) High: V
IN
2.2 V for TTL inputs. V
IN
3.5 V for CMOS inputs.
Low: V
IN
0.8 V for TTL inputs. V
IN
1.5 V for CMOS inputs.
3) Minimum I
DD
is drawn when standby mode is implemented with
CE = V
DD
(standby1 power).
3
Notes:
Notes:
1) All voltages referenced to GND.
2) V
PP
= V
DD
during non-programming mode.
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
Power-Up Sequence: GND, V
DD
, Inputs
Power-Down Sequence: Inputs, V
DD
, GND
Absolute Maximum Ratings
Recommended Operating Conditions
Power Sequencing
Minimum
-65C
-55C
-0.5 V
-0.5 V
-0.5 V
(Class I)
Storage Temperature Range (Ambient)
Applied Conditions
(1)
Operating Temperature Range (T
CASE
)
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Maximum
+150C
+125C
+7.0 V
V
DD
+ 0.5 V
1.5 W
+250C
V
DD
+ 0.5 V
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +7.0 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
Minimum
0.0
-55
0.0
0.0
+2.2
+3.5
Units
Volt
Celsius
Volt
Volt
Parameters
(1)
Supply Voltage Reference
Case Temperature
Input Logic "Low" - CMOS
Input Logic "Low" - TTL
Input Logic "High" - TTL
Input Logic "High" - CMOS
Symbol
GND
T
C
V
IL
V
IH
Maximum
+4.5
Volt
Supply Voltage
V
DD
+5.5
0.0
+125
+1.5
+0.8
V
DD
V
DD
V
DD
(2)
Volt
Programming Voltage
V
PP
V
DD
(2)
4
1) -55 C
T
case
+125C; 4.5 V
V
DD
5.5 V; unless otherwise
specified.
Test conditions for AC measurements:
300 10%
2.8V
50 pF 10%
Output Load Circuit
DC Electrical Characteristics
Note:
Symbol
Test Conditions
(1)
Limits
Minimum
Maximum
Units
I
DD1
V
OH
0 V
V
IN
5.5 V
(3)
-5
-10
5
10
7
10
150
mA
A
A
pF
pF
V
V
Test
Supply Current
(Cycling Selected)
Supply Current
(Standby)
Input Leakage
Output Leakage
C
in
C
out
High Level Output Voltage
Low Level Output Voltage
0.4
0.1
I
OH
= -200 A
I
OH
= -2 mA
I
OL
= 200 A
I
OL
= 4 mA
4.2
V
DD
- 0.1 V
I
DD2
V
OL
I
ILK
I
OLK
F = F
MAX
= 1/t
AVAV(min)
CE = V
PP
= V
IH
= V
DD
0 V
V
OUT
5.5 V
2.2
0.8
V
V
High Level Input Voltage
TTL Inputs
Low Level Input Voltage
TTL Inputs
V
IH
V
IL
2.0
mA
3.5
1.5
V
V
High Level Input Voltage
CMOS Inputs
Low Level Input Voltage
CMOS Inputs
V
IH
V
IL
F = F
MAX
= 1/t
AVAV(min)
No Output Load
CMOS Input
Device
Type
(2)
All
All
All
All
All
All
All
All
xxxT
xxxT
xxxC
xxxC
(3)
Group A
Subgroups
1, 2, 3
1, 2, 3
4
4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2) The delineation in this table is by input device type (TTL or
CMOS). xxxT represents a device with TTL inputs; xxxC
represents a device with CMOS inputs.
3) Measured during initial device characterization.
0 V to V
DD
2.0 ns/Volt
2.5 V
V
OL
= 0.5 V;
V
OH
= V
DD
- 0.5 V
50%
See Output Load Circuit
Diagram
See Read Cycle Timing
Input Levels
Input Rise and Fall Time
Input and Output Timing
Reference Levels (Except
for Tristate Parameters)
Input and Output Timing
Reference Levels or
Tristate Parameters
Programmed Array Mix of
`1's and `0's
Output Load
Read Cycle
Note:
1) Test Conditions: -55C
T
case
+125C; 4.5 V
V
DD
5.5 V; unless otherwise specified.
5
Read Cycle AC Timing Characteristics
(1)
Read Cycle Timing Diagram
Device Type
Limits
Minimum
Maximum
Units
0
0
0
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output Active
Output Enable to Output Active
Output Hold After Address Change
Chip Enable to Output Disable
Output Enable to Output Disable
Symbol
t
EHQZ
t
AVAV
t
AVQV
t
GHQZ
t
GLQV
t
ELQV
t
ELQX
t
GLQX
t
AXQX
t
AVAV
Valid Address
Valid Data
High Impedance
Address
t
AVQV
t
ELQV
t
ELQX
t
GLQV
t
GLQX
CE
OE
Data
Out
t
GHQZ
t
EHQZ
t
AXQX
45
X4XX
60
X6XX
X4XX
X6XX
45
60
X4XX
X6XX
45
60
X4XX
X6XX
45
60
6
Dynamic Electrical Characteristics
Radiation Characteristics
Total Ionizing Radiation Dose
The PROM will meet all stated functional and electrical
specifications over the entire operating temperature range
after a total ionizing radiation dose of 2x10
5
rad(Si). All
electrical and timing performance parameters will remain
within specifications after rebound at V
DD
= 5.5 V and T =
125C extrapolated to ten years of operation. Total dose
hardness is assured by wafer level testing of process monitor
transistors and PROM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations
have been made between 10 keV X-rays applied at a dose
rate of 1x10
5
rad(Si)/min at T = 25C and gamma rays (Cobalt
60 source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test environments.
Neutron Radiation
The PROM will meet any functional or timing specification after
a total neutron fluence of up to 1x10
12
cm
2
applied under
recommended operating or storage conditions. This assumes
an equivalent neutron energy of 1 MeV.
Single Event Effects
The PROM has demonstrated no data upset when exposed
to ion LETs
124 MeV/mg/cm
2
. Given that the design uses
an anti-fuse for data storage and programmability, Single
Event Device Rupture (SEDR) testing was also performed.
No SEDR was detected to an effective LET of 88
MeV/mg/cm
2
.
Latchup
The PROM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions.
Read Cycle
The PROM is asynchronous in operation, allowing the read
cycle to be controlled by address or chip enable (CE) (refer to
Read Cycle Timing diagram). To perform a valid read operation,
both chip enable (CE) and output enable (OE) must be low. The
output drivers can be controlled independently by the OE
signal. Consecutive read cycles can be executed with CE held
continuously low, and with OE held continuously low, and
toggling the addresses.
For an address-activated read cycle, CE and OE must be valid
prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between address
edge transitions is permissible; however, data outputs will
become valid t
AVQV
time following the latest occurring address
edge transition. The minimum address activated read cycle time
is t
AVAV
. When the PROM is operated at the minimum address-
activated read cycle time, the data outputs will remain valid on
the PROM I/O until t
AXQX
time following the next sequential
address transition.
To control a read cycle with CE, all addresses and OE
must be valid prior to or coincident with the enabling CE
edge transition. Address or OE edge transitions can occur
later than the specified setup times to CE, however, the
valid data access time will be delayed. Any address edge
transition that occurs during the time when CE is low will
initiate a new read access, and data outputs will not
become valid until t
AVQV
time following the address edge
transition. Data outputs will enter a high impedance state
t
EHQZ
time following a disabling CE edge transition.
To control a read cycle with OE, all addresses and CE
must be valid prior to or coincident with the enabling OE
edge transition. Address or CE edge transitions can occur
later than the specified setup times to OE; however, the
valid data access time will be delayed. Any address edge
transition that occurs during the time when OE is high will
initiate a new read access, and data outputs will not
become valid until t
AVQV
time following the address edge
transition. Data outputs will enter a high impedance state
t
GHQZ
time following a disabling OE edge transition.
7
Radiation Hardness Ratings
(1),(2), (3)
Notes:
1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan.
2) Device electrical characteristics are guaranteed for post irradiation levels at 25C,
per MIL-STD-883, Test
Method 1019.5, Condition A.
3)
There are no storage elements on this device.
4) Tested with ions having perpendicular incidence at LET of 60 MeV/mg/cm
2
, 90% worst case particle
environment, geosynchronous orbit, 0.025" of aluminum shielding.
Conditions
Units
rad(Si)
Upsets/Bit-Day
N/cm
2
Maximum
Symbol
RTD
SEL
SEDR
(4)
SEU
(1)
RNF
Minimum
200K
1E + 12
Characteristics
Total Dose
Single Event Latchup
Single Event Dielectric Rupture (anti-fuse)
Single Event Upset
Neutron Fluence
-55C
T
case
125C
-55C
T
case
125C
Fails/Device-Day
Immune
-55C
T
case
125C
0
0
Upsets/Fuse-Day
*Input rise and fall times <5 ns
Tester AC Timing Characteristics
TTL I/O Configuration
CMOS I/O Configuration
3 V
V
DD
- 0.4 V
3.4 V
0.4 V
2.4 V
1.5 V
High Z
High Z
High Z = 2.9 V
0 V
1.5 V
. . . . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . . . . .
. . . . . . . .
. . . .
. . . .
. . . .
. . . .
0.5 V
Input
Levels*
Output
Sense
Levels
3.4 V
0.4 V
2.4 V
High Z
High Z
High Z = 2.9 V
V
DD
/2
V
DD
- 0.4 V
V
DD
/2
V
DD
- 0.5 V
8
Radiation Hardness Assurance
Reliability
BAE SYSTEMS' reliability starts with an overall product
assurance system that utilizes a quality system involving all
employees including operators, process engineers and
product assurance personnel. An extensive wafer lot
acceptance methodology, using in-line electrical data as well
as physical data, assures product quality prior to assembly. A
continuous reliability monitoring program evaluates every lot
at the wafer level, utilizing test structures as well as product
testing. Test structures are placed on every wafer, allowing
correlation and checks within-wafer, wafer-to-wafer, and from
lot-to-lot.
Reliability attributes of the CMOS process are characterized
by testing both irradiated and non-irradiated test structures.
The evaluations allow design model and process changes to
be incorporated for specific failure mechanisms, i.e., hot
carriers, electromigration, and time dependent dielectric
breakdown. These enhancements to the operation create a
more reliable product.
The process reliability is further enhanced by accelerated
dynamic life tests of both irradiated and non-irradiated test
structures. Screening and testing procedures from the
customer are followed to qualify the product.
A final periodic verification of the quality and reliability of the
product is validated by a TCI (Technology Conformance
Inspection).
BAE SYSTEMS has two QML screen levels (Q and V) to meet
full compliant space applications. For limited performance and
evaluation situations, BAE SYSTEMS offers an engineering
screen level.
Screening Levels
BAE SYSTEMS provides a superior quality level of radiation
hardness assurance for our products. The excellent product
quality is sustained via the use of our qualified QML operation
which requires process control with statistical process control,
radiation hardness assurance procedures and a rigid
computer controlled manufacturing operation monitoring and
tracking system.
The BAE SYSTEMS technology is built with resistance to
radiation effects. Our product is designed to exhibit < 1e
-11
fails/bit-day in a 90% worst case geosynchronous orbit under
worst case operating conditions. Total dose hardness is
assured by irradiating test structures on every lot and total
dose exposure with Cobalt 60 testing performed quarterly on
TCI lots to assure the product is meeting the QML radiation
hardness requirements.
Standard Screening Procedure
X
X
Sample
X
X
X
X
X
X
X
X
X
X
X
X
Sample
X
X
X
X
X
X
X
X
X
X
X
X
X
Alternate Method Used
Die Traceability
MIL-STD-883, TM 2010
Meets Group A
< 5% Fallout
MIL-STD-883, TM 2009
Wafer Lot Acceptance
Serialization
Destructive Bond Pull
Internal Visual
Temperature Cycle
Constant Acceleration
PIND
Radiography
Electrical Test
Blank Array Dynamic Burn-In
Electrical Test
Test Row Dynamic Burn-In
Final Electrical
PDA
Fine and Gross Leak
External Visual
Comments
Q
V
Flow
QML Level
X
X
All I/O pins specified in the burn-in pin lists are driven through
individual series resistors (1.6K
10%). Burn-in voltages
are defined using the following notation:
Voltage Levels
V1: +5.5V (-0% /+10%)
V
DD
pin is tied to this level.
Vin(0): 0.0 V to +0.4 V
Low level for all programmed signals.
Vin(1): +5.5 V (-0% /+10%)
High level for all programmed signals.
GND Pins:
All module GND pins shall be tied to ground.
Fuse Stress Methodology
Burn-In Methodology
There are two main areas of fuse-related failure concerns in
programmable devices. The first area of concern is
unprogrammed fuses becoming mistakenly programmed over
time. The second concern is programmed fuses becoming
unprogrammed.
With the ONO anti-fuse technology, it has been shown that the
programmed anti-fuse actually becomes more reliable over time
that the repeated flow of current strengthens the programmed
electrical connection and that the anti-fuse lifetime is greater
than other forms of standard CMOS electromigration failure
mechanisms.
In addition to the normal burn-in cycles, an electrical stress
methodology has been implemented that allows screening at
wafer test for unprogrammed anti-fuse infant mortality failures
and weaker anti-fuses that could diminish programming yield.
This is accomplished by applying a higher than normal voltage
across all unprogrammed anti-fuses.
Specifically, there are two levels of high voltage (9V) stresses
applied to unprogrammed anti-fuses at wafer test prior to burn-
in, and a third cycle of unprogrammed fuse stress applied
during the final programmer box personalization. Parts that fail
any of these tests are rejected. After personalization, the
PROM is operated at 4.5 - 5.5 V, and will not experience
subsequent stressing, and does not require additional post-
programmed electrical or temperature stressing. Because anti-
fuse infant mortality failures can be detected and effectively
screened, the PROM has as high a level of reliability as
standard CMOS processed products. Additional justification for
not performing post-programming burn-in will be provided on
request.
There are two methods of burn-in defined: Blank Array Wordline
burn-in and Test Row "Raster" Bitline burn-in.
The Blank Array Wordline burn-in is designed to exercise the
array cells in a sequence which will activate any latent defects
in the array area. This sequence also creates alternate biasing
of adjacent lines to detect defects in the wiring levels of the
chip.
The Test Row "Raster' Bitline burn-in is designed to exercise
the device through a series of logic level shifts which simulate
the active mode of operation of the device, i.e., exercises
decode, sense amps, datapath, and peripheral circuitry. This
mode is used to detect defects at the device level of the chip.
Through the use of these two burn-in modes, the chip is
subjected to an equivalent Q/V level burn-in.
Blank Array Wordline Burn-In Pin Listing
(1)
Input
A0
A1
A2
A3
A4
Signal
F
F/4
F/8
F/16
F
DQ0-7
A11
A12
A13
A14
A10
V
PP
Input
A6
A7
A8
A5
Signal
F/16
F/2
F/4
F/8
F/2
A9
F/128
F/256
F/512
F/64
F/32
CE
OE
V
DD
F/1024
Low
Low
Test Row "Raster" Burn-In Pin Listing
(1)
Input
A0
A1
A2
A3
A4
Signal
F/2
F/8
F/16
F/32
F
DQ0-7
A11
A12
A13
A14
A10
V
PP
Input
A6
A7
A8
A5
Signal
High
F/4
High
High
High
A9
F/64
F/128
F/256
High
High
CE
OE
GND
F/512
Low
Low
1) F = square wave, 100 KHz to 1.0 MHz.
Note:
9
10
Burn-In Circuit
V1
C1
C1 = 0.1 F (10%)
R = 1.6K
(10%)
OE
DQ0
DIN
DQ7
A0
A14
R
R
R
R
R
R
32K x 8
PROM
CE
Device Programming
PROM programming is accomplished using the UnisiteTM
Universal Programmer made by Data I/O corporation.
Unisite is a tool for programming device technologies and
packaging. The Data I/O family of universal programs and
corresponding software releases and updates are available
direct from Data I/O Corporation (800) 3-DATAIO,
Technical Support). A PPI adapter #1007 must also be
purchased from Data I/O to interface the PROM flatpack to the
Data I/O Programmer Box Unit. The PROM device ID number
and programming algorithm information is contained in an
internal silicon signature which is read by the programmer box
and is transparent to the user.
The PROM array is built with all "1's" and an anti-fuse
technology is implemented to program "0's." All
unused locations should remain unprogrammed as
"1's" to save programming time and allow for
additional program locations.
Programming Hints
Post Programming Hints
The Data I/O Programmer uses slow I/O timings to both
program and verify programming of PROM devices. After
programming, it is recommended that users test devices at
speed over application temperature range to ensure that
programmed devices meet the application requirements.
Definition
Minimum System Requirements for Device Programming
Function
Data I/O Programmer Box
Program the PROMs
Adapter Card for the BAE SYSTEMS 32K x 8 PROM
Interface with the Unisite Programmer
Host
PC
A Minicomputer, i.e., Sun, DEC or Apollo Workstation
A DOS-Based Personal Computer i.e., IBM PC or Compatible
Control the Programmer and
Remote Storage of Data Files
A Stand-Alone Terminal, i.e., DEC VT 200, Qume VT-101,
and the Wyse WY-30/40/70 Family of Terminals
Programming
Unisite
Hardware
PPI Adapter #1007
Host or PC
Terminal
11
Packaging
28-Lead Flat Pack Pinout
28-Lead Flat Pack
The 32K x 8 PROM is offered in a custom 28-lead FP.
The package is constructed of multilayer ceramic
(AI
2
O
3
) and feature internal power and ground planes.
It also features a non-conductive ceramic tie bar on the
lead frame. The purpose of the tie bar is to allow
electrical testing of the device, while preserving the lead
integrity during shipping and handling, up to the point of
lead forming and insertion.
Optional capacitors can be mounted to the package to
maximize supply noise decoupling and increase board
packing density. These capacitors attach directly to the
internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire
and package, both of which are critical in a transient
radiation environment. All NC pins must be connected to
either V
DD
, GND or an active driver to prevent charge
build up in the radiation environment. (NC = no connect.)
Notes:
1) Part mark per device specification.
2) "QML" may not be required per device
specification.
3) Dimensions are in inches.
4) Lead width: .008 .002.
5) Lead height: .006 .002.
6) Unless otherwise specified, all
tolerances are .005".
A=.017 .002
B=.050 .003
C=.035 .014
D=.400 .020
E=.175 .010
F=.760 .008
G=.500 .008
H=1.650
J=.650
K=.109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
Top
View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A13
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
V
PP
OE
CE
V
DD
Index Marks
No. 1
Index
H
G
J
F
E
D
(2)
A
(Width)
B
(Pitch)
QML (USA)
Date Code
(1)
C
K
Cleared for Public Domain Release
2001 BAE SYSTEMS, All Rights Reserved
BAE SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
BAE SYSTEMS
An ISO 9001, AS9000, ISO 14001,
and SEI CMM Level 4 Company
9300 Wellington Road, Manassas, VA 20110-4122
866-530-8104
http://www.baesystems-iews.com/space/
0040_32K_8_PROM.ppt
BAE SYSTEMS reserves the right to make changes to
any products herein to improve reliability, function or
design. BAE SYSTEMS does not assume liability
arising out of the application or use of any product or
circuit described herein, neither does it convey any
license under its patent rights nor the rights of others.
Ordering Information
32K x 8 PROM Memory Device
Part Number 197A807-WXYZ
X
Y
Z
W
Z
Screen
Designation
1=QML VV
3=Engineering
4=QML VQ
5=QML QQ
7=Customer Specific
Y
Speed
Designation
4 = 45 ns
6 = 60 ns
X
Input
Type
C = CMOS
T = TTL
Package
Type
1 = 28 Pin
Flatpack
W
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