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Электронный компонент: 18CV8

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1
04-02-004H
International
CMOS
Technology
Commercial/
Industrial
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT's JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 2 Block Diagram
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
Figure 1 Pin Configuration
PLCC
DIP
SOIC
1
2
3
4
5
6
7
8
9
10
I/CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
20
19
18
17
16
15
14
13
12
11
TSSOP
PEELTM 18CV8 -5/-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s
s
s
s
Multiple Speed Power, Temperature Options
- V
CC
= 5 Volts 10%
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
s
s
s
s
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
s
s
s
s
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
- PLD-to-PEEL JEDEC file translator
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
s
s
s
s
Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
2
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
Figure 3 PEEL18CV8 Logic Array Diagram
3
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
Function Description
The PEEL18CV8 implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User-
configurable output structures in the form of I/O macrocells
further increase logic flexibility.
Architecture Overview
The PEEL18CV8 architecture is illustrated in the block dia-
gram of Figure 2. Ten dedicated inputs and 8 I/Os provide
up to 18 inputs and 8 outputs for creation of logic functions.
At the core of the device is a programmable electrically-
erasable AND array which drives a fixed OR array. With
this structure, the PEEL18CV8 can implement up to 8 sum-
of-products logic expressions.
Associated with each of the 8 OR functions is an I/O mac-
rocell which can be independently programmed to one of
12 different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions of active-high or active-low polarity, while provid-
ing three different feedback paths into the AND array.
AND/OR LOGIC ARRAY
The programmable AND array of the PEEL18CV8 (shown
in Figure 3) is formed by input lines intersecting product
terms. The input lines and product terms are used as fol-
lows:
s
s
s
s
36 Input Lines:
- 20 input lines carry the true and complement of the
signals applied to the 10 input pins
- 16 additional lines carry the true and complement val-
ues of feedback or input signals from the 8 I/Os
s
s
s
s
74 product terms:
- 64 product terms (arranged in groups of 8) are used
to form sum of product functions
- 8 output enable terms (one for each I/O)
- 1 global synchronous preset term
- 1 global asynchronous clear term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 36-input AND gate. A product term
that is connected to both the true and complement of an
input signal will always be FALSE and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a "don't care" state exists and
that term will always be TRUE.
When programming the PEEL18CV8, the device program-
mer first performs a bulk erase to remove the previous pat-
tern. The erase cycle opens every logical connection in the
array. The device is configured to perform the user-defined
function by programming selected connections in the AND
array. (Note that PEEL device programmers automatically
program all of the connections on unused product terms so
that they will have no effect on the output function).
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently permits
users to tailor the configuration of the PEEL18CV8 to the
precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of each macrocell is determined by the four
EEPROM bits controlling these multiplexers. These bits
determine output polarity, output type (registered or non-
registered) and input-feedback path (bidirectional I/O, com-
binatorial feedback). Refer to Table 1 for details.
Equivalent circuits for the twelve macrocell configurations
are illustrated in Figure 5. In addition to emulating the four
PAL-type output structures (configurations 3,4,9, and 10),
the macrocell provides eight additional configurations.
When creating a PEEL device design, the desired macro-
cell configuration generally is specified explicitly in the
design file. When the design is assembled or compiled, the
macrocell configuration bits are defined in the last lines of
the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register will be set
HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
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04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18CV8 macrocell also provides control over the
feedback path. The input/feedback signal associated with
each I/O macrocell may be obtained from three different
locations; from the I/O input pin, from the Q output of the
flip-flop (registered feedback), or directly from the OR gate
(combinatorial feedback).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output func-
tion with a bi-directional I/O.)
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability
to feedback the output of the OR gate, bypassing the out-
put buffer, regardless of whether the output function is reg-
istered or combinatorial. This feature allows the creation of
asynchronous latches, even when the output must be dis-
abled. (Refer to configurations 5,6,7 and 8 in Figure 5.)
Figure 4 Block Diagram of the PEEL18CV8
I/O Macrocell
Registered Feedback
Feedback also can be taken from the register, regardless of
whether the output function is to be combinatorial or regis-
tered. When implementing a combinatorial output function,
registered feedback allows for the internal latching of states
without giving up the use of the external output.
Design Security
The PEEL18CV8 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set it is impossible to
verify (read) or program the PEEL until the entire device
has first been erased with the bulk-erase function.
Programming Support
ICT's JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL18CV8, without the
need for redesign. ICT supports a broad range of popular
third party design entry systems, including Data I/O Synario
and Abel, Logical Devices CUPL and others. ICT also
offers (for free) its proprietary PLACE software, an easy-to-
use entry level PC-based software development system.
Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
mer system, the PDS-3.
5
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
Configuration
Input/Feedback Select
Output Select
#
A
B
C
D
1
1
1
1
1
Bi-directional I/O
Register
Active Low
2
0
1
1
1
Bi-directional I/O
Register
Active High
3
1
0
1
1
Bi-directional I/O
Combinatorial
Active Low
4
0
0
1
1
Bi-directional I/O
Combinatorial
Active High
5
1
1
1
0
Combinatorial Feedback
Register
Active Low
6
0
1
1
0
Combinatorial Feedback
Register
Active High
7
1
0
1
0
Combinatorial Feedback
Combinatorial
Active Low
8
0
0
1
0
Combinatorial Feedback
Combinatorial
Active High
9
1
1
0
0
Register Feedback
Register
Active Low
10
0
1
0
0
Register Feedback
Register
Active High
11
1
0
0
0
Register Feedback
Combinatorial
Active Low
12
0
0
0
0
Register Feedback
Combinatorial
Active High
6
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
Absolute Maximum Ratings
Operating Range
Symbol
Parameter
Conditions
Rating
Unit
V
CC
Supply Voltage
Relative to Ground
-0.5 to + 6.0
V
V
I
, V
O
Voltage Applied to Any Pin
2
Relative to Ground
1
-0.5 to V
CC
+ 0.6
V
I
O
Output Current
Per Pin (I
OL
, I
OH
)
25
mA
T
ST
Storage Temperature
-65 to +150
C
T
LT
Lead Temperature
Soldering 10 Seconds
+300
C
Symbol
Parameter
Conditions
Min
Max
Unit
Vcc
Supply Voltage
Commercial
4.75
5.25
V
Industrial
4.5
5.5
V
T
A
Ambient Temperature
Commercial
0
+70
C
Industrial
-40
+85
C
T
R
Clock Rise Time
See Note 3.
20
ns
T
F
Clock Fall TIme
See Note 3.
20
ns
T
RVCC
V
CC
Rise Time
See Note 3.
250
ms
Symbol
Parameter
Conditions
Min
Max
Unit
V
OH
Output HIGH Voltage - TTL
V
CC
= Min, I
OH
= -4.0 mA
2.4
V
V
OHC
Output HIGH Voltage - CMOS
12
V
CC
= Min, I
OH
= -10 A
VCC - 0.3
V
V
OL
Output LOW Voltage - TTL
V
CC
= Min, I
OL
= 16mA/24mA
13
0.5
V
V
OLC
Output LOW Voltage - CMOS
12
V
CC
= Min, I
OL
= 10 A
0.15
V
V
IH
Input HIGH level
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
-0.3
0.8
V
I
IL
Input, I/O Leakage Current LOW
Input and I/O pull-ups disabled
VCC = Max, VIN = GND, I/O = High Z
-10
A
I
IP
Input, I/O Leakage Current LOW
Input and I/O pull-ups enabled
VCC = Max, VIN = GND, I/O = High Z
-100
A
I
IH
Input, I/O Leakage Current HIGH
VCC = Max, VIN = V
CC
, I/O = High Z
0 (Typical)
40
A
I
SC
9
Output Short Circuit Current
V
CC
= 5V, V
O
= 0.5V, TA = 25C
-30
-135
mA
I
CC
10
V
CC
Current, f=1MHz
VIN = 0V or V
CC
,
f = 25 MHz
All Outputs disabled
4
-5
90
mA
-7
90
-10
110/115
-15
45/55
-25
37/50
C
IN
7
Input Capacitance
TA = 25C, VCC = 5.0V
@ f = 1 MHz
6
pF
C
OUT
7
Output Capacitance
12
pF
D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)
This device has been designed and tested for the specified
operating ranges. Proper operation outside of these levels
is not guaranteed. Exposure to absolute maximum ratings
may cause permanent damage.
7
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (Unless otherwise
specified).
9. Test one output at a time for a duration of less than 1 second.
10. I
CC
for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design process modification that
might affect operational frequency.
12. Available only for 18CV8 -15/I-15/-25/I-25 grades
13. 24mA available for 18CV8-5/-7. All other speeds are 16mA.
A.C. Electrical Characteristics
Over the operating range
8
Switching Waveforms
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V
for periods less than 20 ns.
2. V
I
and V
O
are not specified for program/verify operation.
3. Test Points for Clock and VCC in t
R
and t
F
are referenced at the 10%
and 90% levels.
4. I/O pins are 0V and V
CC
.
5. "Input" refers to an input pin signal.
6. t
OE
is measured from input transition to V
REF
0.1V, T
OD
is measured
from input transition to V
OH
-0.1V or V
OL
+0.1V; V
REF
=V
L.
7. Capacitances are tested on a sample basis.
Symbol
Parameter
-5
-7
-10/I-10
-15/I-15
-25/I-25
Units
Min Max Min Max Min Max Min Max Min
Max
t
PD
Input
5
to non-registered output
5
7.5
10
15
25
ns
t
OE
Input
5
to output enable
6
5
7.5
10
15
25
ns
t
OD
Input
5
to output disable
6
5
7.5
10
15
25
ns
t
CO1
Clock to Output
4
7
7
12
15
ns
t
CO2
Clock to comb. output delay
via internal registered feedback
7.5
10
12
25
35
ns
t
CF
Clock to Feedback
2.5
3.5
4
8
15
ns
t
SC
Input
5
or feedback setup to clock
3.5
5
5
12
20
ns
t
HC
Input
5
hold after clock
0
0
0
0
0
ns
t
CL
, t
CH
Clock low time, clock high time
8
3
3.5
5
10
15
ns
t
CP
Min clock period Ext (t
SC
+ t
CO1
)
7
12
12
24
35
ns
f
MAX1
Internal feedback (1/t
SC
+t
CF
)
11
166.7
117.6
111
50
28.5
MHz
f
MAX2
External Feedback (1/t
CP
)
11
133
83.3
83.3
41.6
28.5
MHz
f
MAX3
No Feedback (1/t
CL
+t
CH
)
11
166.7
142.8
100
50
33.3
MHz
t
AW
Asynchronous Reset Pulse Width
5
7.5
10
15
25
ns
t
AP
Input
5
to Asynchronous Reset
5
7.5
10
15
25
ns
t
AR
Asynchronous Reset recovery time
5
7.5
10
15
25
ns
t
RESET
Power-on reset time for registers
in clear state
5
5
5
5
5
s
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
8
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
PEEL Device and Array Test Loads
Ordering Information
Technology
R1
R2
R
L
V
L
C
L
CMOS
12
480k
480k
228k
2.375V
33 pF
TTL -10/-15/-25
235
159
95
2.02V
33 pF
TTL -5/-7
159
118
68
2.129V
33 pF
Part Number
Speed
Temperature
Package
PEEL18CV8J-5
5 ns
Commercial
20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8P-7
7.5 ns
Commercial
20-pin Plastic 300 mil DIP
PEEL18CV8J-7
7.5 ns
Commercial
20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8S-7
7.5 ns
Commercial
20-pin SOIC
PEEL18CV8P-10
10 ns
Commercial
20-pin Plastic 300 mil DIP
PEEL18CV8PI-10
Industrial
PEEL18CV8J-10
10 ns
Commercial
20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-10
Industrial
PEEL18CV8S-10
10 ns
Commercial
20-pin SOIC
PEEL18CV8SI-10
Industrial
PEEL18CV8T-10
10 ns
Commercial
20-pin TSSOP 170 mil
PEEL18CV8TI-10
Industrial
PEEL18CV8P-15
15 ns
Commercial
20-pin Plastic 300 mil DIP
PEEL18CV8PI-15
Industrial
PEEL18CV8J-15
15 ns
Commercial
20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-15
Industrial
PEEL18CV8S-15
15 ns
Commercial
20-pin SOIC
PEEL18CV8SI-15
Industrial
PEEL18CV8T-15
15 ns
Commercial
20-pin TSSOP 170 mil
PEEL18CV8TI-15
Industrial
PEEL18CV8P-25
25 ns
Commercial
20-pin Plastic 300 mil DIP
PEEL18CV8PI-25
Industrial
PEEL18CV8J-25
25 ns
Commercial
20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-25
Industrial
PEEL18CV8S-25
25 ns
Commercial
20-pin SOIC
PEEL18CV8SI-25
Industrial
PEEL18CV8T-25
25 ns
Commercial
20-pin TSSOP 170 mil
PEEL18CV8TI-25
Industrial
Output
C
L
R2
R1
5 V
Standard
Load
Output
C
L
R
L
V
L
Thevenin
Equivalent
9
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
Part Number
Device
PEEL18CV8
Suffix
PI-25
Package
P = 20-pin Plastic 300mil DIP
J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
S = 20-pin SOIC 300 mil Gullwing
T = 20-pin TSSOP 170 mil
Speed
5 = 5ns t
PD
7 = 7.5ns t
PD
10 = 10ns t
PD
15 = 15ns t
PD
25 = 25ns t
PD
Temperature Range
(Blank) = Commercial 0 to +70C
I = Industrial
-40 to +85 C
10
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8