1
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
A max.
Separate input and display voltages
Wide power supply range:
V
(logic) 2 to 8 V, V
(display) V
to 12 V
On-chip latches separate control and display sections
Drives up to 40 LCD segments in direct drive
Crossfree cascadable
Schmitt Trigger on the inputs
30 ns (typ.) glitch filter on every input
High noise immunity
Segment outputs short circuit protected
LCD blanking function
- 40 to +85 C temperature range
On request extended temperature range,
- 40 to +125 C
QFP52 and TAB packages
DD
LCD
DD
O
O
Serial data input / output
Low dynamic current, 5 A max.
Low standby current, 1
Description
The V 6108 is a CMOS integrated circuit that drives LCD.
The circuit drives up to 40 LCD segments from a serial clocked
input. It has a serial output for cascading to further drives. The
serially clocked data is parallel loaded into 40 latches under
control of the strobe pin. The latched data determines which
segments are ON or OFF. Any segment output can be used to
drive a backplane. A blank function is provided to clear the
display.
Applications
n
n
n
n
n
n
n
Balances and scales
Automotive displays
Utility meters
Large displays
Pagers
Portable, battery operated products
Telephones
40 Segment Static LCD Driver
Typical Operating Configuration
V6108
QFP52
1
V6108
V6108
SEG 41- 80
STR
EM MICROELECTRONIC-MARIN SA
V6108
2
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond specified
operating conditions may affect device reliability or cause
malfunction.
Handling Procedures
This device has built-in protection against high static voltages
or electric fields; however, anti-static precautions must be taken
as for any other CMOS component. Unless otherwise specified,
proper operation can only occur when all terminal voltages are
kept within the supply voltage range. Unused inputs must
always be tied to a defined logic voltage level.
Absolute Maximum Ratings
Table 1
V
DD
V
LCD
V
LOGIC
V
DISP
T
STO
P
MAX
V
T
Smax
S
-0.3V to +10V
-0.3V to +14V
-0.3V to V +0.3V
DD
V to V
+ 0.3V
DD
LCD
- 65 to +150 C
o
100 mW
1000V
250 C x 10 s
o
1)
V
has to be higher or equal to V
LCD
DD
Operating Conditions
Table 2
T
A
-40
2.0
+125
O
C
V
8
V
DD
Parameter
Symbol Min. Typ. Max. Units
Operating temperature
1)
Logic supply voltage
LCD supply voltage
V
DD
12
V
1)
The maximum operating temperature is confirmed
by sampling at initial device qualification. In
production, all devices are tested at +85 C. On
request devices tested at+125 C can be supplied.
o
o
Electrical Characteristics
1)
2)
3)
Tested with V = V , V = V
Table 3
Tested with f = 100 kHz, F = 50 kHz, 50 pF on each segment
Tested with f = 64 Hz, f = 0 Hz, 50 pF on each segment
IL
SS
IH
DD
CL
DI
FL
CL
Timing Characteristics
V
= 5V 10%, V
= 12 V and T = -40 to +85 C, unless otherwise specified
DD
LCD
A
o
1)
2)
Recommended frame frequency.
Maximum test frequency.
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Units
Clock high pulse width
Clock low pulse width
Clock and FR rise time
Clock and FR fall time
Data input setup time
Data input hold time
Data output propagation
CLK falling to STR rising
STR falling to CLK falling
FR frequency
t
CH
t
CL
t
CR
t
CF
t
DS
t
DH
t
PD
t
P
t
D
f
FR
C
= 50 pF
LOAD
500
500
250
0
50
250
200
800
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Table 4
Delay S1 - S40 fall time
Delay S1 - S40 rise time
t
SF
t
SR
500
500
s
s
600
64 Hz
1)
0.5
2.9
1
2)
1
5
STR pulse width
t
STR
I
DD
I
LCD
I
DD
I
LCD
I
IL
V
IL
V
IH
V
SH
V
SL
See note
1)
See note
1)
See note
1)2)
See note
1)3)
V =V
V =V
IN
SS
IN
DD
or
I = 100 A V
= V
= 4.5 V
H
DD
LCD
3.8
V
- 100
DD
0.1
0.1
55
0.6
3.5
1
1
75
5
1
0.8
A
A
A
A
A
V
mV
mV
V
I = 100 A V
= V
= 4.5 V
L
DD
LCD
V + 100
SS
I
SC
I = 20 A, V
= V
= 4.5 V
H
DD
LCD
I = 20 A, V
= V
= 4.5 V
L
DD
LCD
mV
mV
mA
V + 100
SS
V
- 100
LCD
V
OL
V
OH
V6108
Functional Description
Supply Voltages V
Data Input / Output (DI / DO)
LCD
V
V
The data input pin (Dl) accepts serial data from the data source.
The data is clocked in a rate determined by the clock input
frequency (CLK). A logic "1" on Dl corresponds to a visible
segment when the backplane is driven by a signal
corresponding to logic "0". The data at DO is equal to
the data at Dl
delayed
by 40 clock periods.
In
LCD
LCD
, V , V
DD
SS
V
is the positive supply line for the logic and
for the
display signals.
has to be equal or higher than V
All
voltages are specified relative to V .
DD
DD
SS
.
5
V
DD
Shift Register
40 Bits
40 Latches
STR
AC
FR
LS
2)
LS
2)
V
SS
SEG
SEG 40
1)
2)
F = Noise Filter
LS = Voltage Level Shifter
DI
Fig. 8
DO
CLK
100
90
20
30
40
50
60
70
80
10
0
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
Table 5
S1...S40
V
LCD
V
DD
FR
DI
DO
CLK
STR
R
V
SS
V6108
PDF 
ZIP
