CONFIDENTIAL
EUREKA
EK7411
- 1 -
Rev 1.3 Feb.25.2002
384-Channel 8-bit Source Driver for color TFT LCDs
DESCRIPTION
The EK7411 is a 8-bit source driver ICs dedicated for SXGA and UXGA TFT-LCD panels. The
digital input is a 8-bit word by 6 dots digital display data, where each word can generate 256-
grayscale levels. By using R/G/B filters 3 dots can be combined to generate a 16.77 Millions
colors pixel. Each output can drive alternately 256 positive-polarity or 256 negative-polarity
grayscale levels with respect to the opposite polarity of adjacent odd and even output pins. These
256 positive and negative grayscale levels are generated with 2x8 external reference voltages
(V
0
-V
7
, V
8
-V
15
) feeding a built-in RDAC that implements a gamma correction for the panel. With
positive and negative output voltage, these circuits feature a dot-dot inversion, n-lines-dot
inversion and frame-dot inversion schemes.
FEATURES
CMOS input level (2.5V to 3.6V)
High-speed data transfer: F
MAX
= 80 MHz (internal data transfer speed when operating at
V
DD1
= 3.0V)
48 data bits (8-bit grayscales code x 3 RGB dot x 2 pixels)
Logic power supply voltage (V
DD1
): 2.5V to 3.6V
Driver power supply voltage (V
DD2
): 8.5V to 13.5V
Output dynamic range: V
SS2
+ 0.1V to V
DD2
0.1V
384 outputs
256 positive and negative output voltage levels by means of 2x8 external reference voltages
and a built in D/A converter (R-DAC)
Applies for dot-dot inversion, n-line-dot inversion and frame-dot inversion
Output voltage polarity inversion function (LPOL)
Bi-directional shift (R/L)
Chip-enable signal generation circuit
Display data inversion function (POL1, POL2)
Low power mode function (LPC)
CONFIDENTIAL
EUREKA
EK7411
- 2 -
Rev 1.3 Feb.25.2002
1. INTERNAL BLOCK DIAGRAM
Data
inversion
circuit
Control
logic
64 bit bidirectional shift register
384 latch circuit (1)
384 latch circuit (2)
384 decoders
384 output Buffers
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
Gr
a
ysc
a
l
e
vo
lt
a
g
e
g
e
ner
a
t
i
o
n
V0-V7
V8-V15
LPC
VDD1
VDD2
VSS1
VSS2
S1S2S3S4
S384
POL1
POL2
D -D , D -D
00
07
10
17
D -D , D -D
D -D , D -D
20
27
30
37
40
47
50
57
STB
EIO1
EIO2
LPOL
R/L
CLK
256 positive-polartiy
Grayscales
256 negative-polartiy
Grayscales
8 planes
8 planes
Figure 1: Block diagram
1. Control logic unit
Generates the chip-enable signal EIO1 and EIO2 and the internal control signals.
2. Data inversion unit
Uses the POL1-POL2 signals to invert or not the 6 x 8-bit input data.
3. 64 bits bi-directional shift register
Generates the enable signals for sequential latching of 64 groups of 48-bit input data.
4. Latch circuit (1)
384x8-bit latch circuits that latch sequentially 6 outputs x 8-bit (2 pixels) from the data bus.
5. Latch circuit (2)
Stores on the rising edge of STB signal the 384x8-bit line data from the first latch stage to
the output buffers.
6. Decoders
Select one of the 256-grayscale levels as a function of the 8-bit code word.
7. Grayscale
voltage
generation
unit
Performs a voltage division of the 16 external input reference voltages, and generates
256 positive-polarity and 256 negative-polarity grayscale levels.
8. Buffers
Drive the selected grayscale voltage level to the panel.
CONFIDENTIAL
EUREKA
EK7411
- 3 -
Rev 1.3 Feb.25.2002
2. PIN CONFIGURATION (TCP PACKAGE)
Copper
Foil
Surface
VSS
VDD
GMA
GMA
GMA
GMA
GMA
GMA
GMA
GMA
R/L
D
D
D
D
POL
POL
LPOL
STB
EIO
VDD
CLK
VSS
LPC
EIO
D
D
D
D
D
D
GMA
GMA
GMA
GMA
GMA
GMA
GMA
GMA
VDD
VSS
2
2
14
12
10
8
6
4
2
0
40
47
30
37
1
2
2
1
1
1
20
27
10
17
00
07
1
3
5
7
9
11
13
15
2
2
D
D
50
57
S
384
S
S
S
S
S
383
382
3
2
1
Figure 2: Pin Arrangement
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