Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52E649E12-A6B/B6B
512 MB Registered SDRAM DIMM
64-Mword
72-bit, 100 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M
4 Components)
PC100 SDRAM
E0020H20 (Ver. 2.0)
Aug. 20, 2001 (K)
Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed
as an optimized main memory solution for 8-byte processor applications. The HB52E649E12 is a 64M
72
1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM
(HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1
piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin
socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible
without surface mount technology. The HB52E649E12 provides common data inputs and outputs.
Decoupling capacitors are mounted beside each TSOP on the module board.
Features
Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev.1.2)
168-pin socket type package (dual lead out)
Outline: 133.37 mm (Length)
43.18 mm (Height)
4.00 mm (Thickness)
Lead pitch: 1.27 mm
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Data bus width:
72 ECC
Single pulsed
RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential
HB52E649E12-A6B/B6B
Data Sheet E0020H20
2
Interleave
Programmable
CE latency
: 3/4 (HB52E649E12-A6B)
: 4 (HB52E649E12-B6B)
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
Frequency
CE
latency
Package
Contact pad
HB52E649E12-A6B
100 MHz
3/4
168-pin dual lead out socket type
Gold
HB52E649E12-B6B
100 MHz
4
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
HB52E649E12-A6B/B6B
Data Sheet E0020H20
3
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
V
SS
43
V
SS
85
V
SS
127
V
SS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
NC
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
V
CC
48
NC
90
V
CC
132
NC
7
DQ4
49
V
CC
91
DQ36
133
V
CC
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
V
SS
54
V
SS
96
V
SS
138
V
SS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
V
CC
101
DQ45
143
V
CC
18
V
CC
60
DQ20
102
V
CC
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
V
SS
106
CB5
148
V
SS
23
V
SS
65
DQ21
107
V
SS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
V
CC
68
V
SS
110
V
CC
152
V
SS
27
W
69
DQ24
111
CE
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0
72
DQ27
114
NC
156
DQ59
31
NC
73
V
CC
115
RE
157
V
CC
32
V
SS
74
DQ28
116
V
SS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
HB52E649E12-A6B/B6B
Data Sheet E0020H20
4
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
36
A6
78
V
SS
120
A7
162
V
SS
37
A8
79
CK2
121
A9
163
CK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
V
CC
82
SDA
124
V
CC
166
SA1
41
V
CC
83
SCL
125
CK1
167
SA2
42
CK0
84
V
CC
126
A12
168
V
CC
Pin Description
Pin name
Function
A0 to A12
Address input
Row address
A0 to A12
Column address
A0 to A9, A11
BA0/BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
S0
,
S2
Chip select input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Write enable input
DQMB0 to DQMB7
Byte data mask
CK0 to CK3
Clock input
CKE0
Clock enable input
WP
Write protect for serial PD
REGE*
1
Register/Buffer enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
Serial address input
V
CC
Primary positive power supply
V
SS
Ground
NC
No connection
Note:
1. REGE
V
IH
: Register mode.
REGE
V
IL
: Buffer mode.
HB52E649E12-A6B/B6B
Data Sheet E0020H20
5
Serial PD Matrix*
1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
1
0D
13
4
Number of column addresses
bits
0
0
0
0
1
0
1
1
0B
11
5
Number of banks
0
0
0
0
0
0
0
1
01
1
6
Module data width
0
1
0
0
1
0
0
0
48
72 bit
7
Module data width (continued)
0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels
0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest
CE
latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest
CE
latency)
6 ns
0
1
1
0
0
0
0
0
60
*
7
11
Module configuration type
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
Normal
(7.8125 s)
Self refresh
13
SDRAM width
0
0
0
0
0
1
0
0
04
64M
4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04
4
15
SDRAM device attributes:
minimum clock delay for back-to-
back random column addresses
0
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
0
0
0
0
1
1
1
1
0F
1, 2, 4, 8
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE
latency
(-A6B)
0
0
0
0
0
1
1
0
06
2/3
(-B6B)
0
0
0
0
0
1
0
0
04
3
19
SDRAM device attributes:
S
latency
0
0
0
0
0
0
0
1
01
0
20
SDRAM device attributes:
W
latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM device attributes
0
0
0
1
1
1
1
1
1F
Registered
HB52E649E12-A6B/B6B
Data Sheet E0020H20
6
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
V
CC
10%
23
SDRAM cycle time
(2nd highest
CE
latency)
(-A6B) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
*
7
(-B6B) Undefined
0
0
0
0
0
0
0
0
00
24
SDRAM access from Clock
(2nd highest
CE
latency)
(-A6B) 6 ns
0
1
1
0
0
0
0
0
60
(-B6B) Undefined
0
0
0
0
0
0
0
0
00
25
SDRAM cycle time
(3rd highest
CE
latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest
CE
latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE
to
CE
delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum
RE
pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on module 1
0
0
0
0
0
0
0
80
1 bank
512M byte
32
Address and command signal
input setup time
0
0
1
0
0
0
0
0
20
2 ns*
7
33
Address and command signal
input hold time
0
0
0
1
0
0
0
0
10
1 ns*
7
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns*
7
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns*
7
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6B)
0
0
1
0
0
0
1
1
23
35
(-B6B)
0
0
1
0
0
0
0
1
21
33
64
Manufacturer's JEDEC ID code
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manufacturer's JEDEC ID code
0
0
0
0
0
0
0
0
00
72
Manufacturing location
*
3
(ASCII-
8bit code)
73
Manufacturer's part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer's part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer's part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer's part number
0
0
1
1
0
0
1
0
32
2
HB52E649E12-A6B/B6B
Data Sheet E0020H20
7
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
77
Manufacturer's part number
0
1
0
0
0
1
0
1
45
E
78
Manufacturer's part number
0
0
1
1
0
1
1
0
36
6
79
Manufacturer's part
0
0
1
1
0
1
0
0
34
4
80
Manufacturer's part number
0
0
1
1
1
0
0
1
39
9
81
Manufacturer's part number
0
1
0
0
0
1
0
1
45
E
82
Manufacturer's part number
0
0
1
1
0
0
0
1
31
1
83
Manufacturer's part number
0
0
1
1
0
0
1
0
32
2
84
Manufacturer's part number
0
0
1
0
1
1
0
1
2D
--
85
Manufacturer's part number
(-A6B)
0
1
0
0
0
0
0
1
41
A
(-B6B)
0
1
0
0
0
0
1
0
42
B
86
Manufacturer's part number
0
0
1
1
0
1
1
0
36
6
87
Manufacturer's part number
0
1
0
0
0
0
1
0
42
B
88
Manufacturer's part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer's part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer's part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
Year code
(BCD)*
4
94
Manufacturing date
Week code
(BCD)*
4
95 to 98 Assembly serial number
*
6
99 to 125 Manufacturer specific data
--
--
--
--
--
--
--
--
--
*
5
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification
CE
#
latency support
(-A6B)
1
0
0
0
0
1
1
1
87
CL = 2/3
(-B6B)
1
0
0
0
0
1
0
1
85
CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High"
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is "Binary
Coded Decimal".
5. All bits of 99 through 125 are not defined ("1" or "0").
6. Bytes 95 through 98 are assembly serial number.
7. These specifications are defined based on component specification, not module.
HB52E649E12-A6B/B6B
Data Sheet E0020H20
8
Block Diagram
I/O0
to I/O3
DQMB
DQ0 to DQ3
* D0 to D17: HM5225405
PLL: 2509
Register: 16835
U0: EEPROM
C0 to C18: 0.22
F
C19 to C44: 2200 pF
C100 to C102: 10pF
R200 to R203: 10
R100: 47 k
R101: 10 k
C200 to C201: 2.2
F
N0 to N17: Network registor 10
V
CC
(D0 to D17, U0)
V
SS
(D0 to D17, U0)
Serial PD
SDA
WP
R100
A0
A1
A2
SA0 SA1 SA2
V
SS
V
SS
V
CC
SCL
U0
SDA
SCL
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
4
N0
C19 to C44
C200 to C201
C0 to C18
RS0
CS
D0
RDQMB0
"high" state.
I/O0
to I/O3
DQMB
DQ4 to DQ7
4
N1
CS
D1
I/O0
to I/O3
DQMB
DQ8 to DQ11
4
N2
CS
D2
RDQMB1
I/O0
to I/O3
DQMB
DQ12 to DQ15
4
N3
CS
D3
I/O0
to I/O3
DQMB
CB0 to CB3
4
N4
CS
D4
I/O0
to I/O3
DQMB
DQ32 to DQ35
4
N9
CS
D9
RDQMB4
I/O0
to I/O3
DQMB
DQ36 to DQ39
4
N10
CS
D10
I/O0
to I/O3
DQMB
DQ40 to DQ43
4
N11
CS
D11
RDQMB5
I/O0
to I/O3
DQMB
DQ44 to DQ47
4
N12
CS
D12
I/O0
to I/O3
DQMB
CB4 to CB7
4
N13
CS
D13
I/O0
to I/O3
DQMB
DQ16 to DQ19
4
N5
RS2
CS
D5
RDQMB2
I/O0
to I/O3
DQMB
DQ20 to DQ23
4
N6
CS
D6
I/O0
to I/O3
DQMB
DQ24 to DQ27
4
N7
CS
D7
RDQMB3
I/O0
to I/O3
DQMB
DQ28 to DQ31
4
N8
CS
D8
I/O0
to I/O3
DQMB
DQ48 to DQ51
4
N14
CS
D14
RDQMB6
I/O0
to I/O3
DQMB
DQ52 to DQ55
4
N15
CS
D15
I/O0
to I/O3
DQMB
DQ56 to DQ59
4
N16
CS
D16
RDQMB7
I/O0
to I/O3
DQMB
DQ60 to DQ63
4
N17
CS
D17
S0
,
S2
DQMB0 to DQMB7
BA0 to BA1
A0 to A12
RE
CE
CKE0
W
RS0
,
RS2
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17
RRAS
->
RAS
: SDRAMs D0 to D17
CCAS
->
CAS
: SDRAMs D0 to D17
RCKE0 -> CKE: SDRAMs D0 to D17
RW
->
WE
: SDRAMs D0 to D17
R101
V
CC
R
E
G
I
S
T
E
R
REGE
PLL CK
R200
PLL
CK0
R201 to R203
C100 to C102
V
SS
CK1 to CK3
HB52E649E12-A6B/B6B
Data Sheet E0020H20
9
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V
SS
V
T
0.5 to V
CC
+ 0.5
(
4.6 (max))
V
1
Supply voltage relative to V
SS
V
CC
0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
P
T
18.0
W
Operating temperature
Topr
0 to +55
C
Storage temperature
Tstg
50 to +100
C
Note:
1. Respect to V
SS
DC Operating Conditions (Ta = 0 to +55C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
V
CC
3.0
3.6
V
1, 2
V
SS
0
0
V
3
Input high voltage
V
IH
2.0
V
CC
V
1, 4
Input low voltage
V
IL
0
0.8
V
1, 5
Notes: 1. All voltage referred to V
SS
2. The supply voltage with all V
CC
pins must be on the same level.
3. The supply voltage with all V
SS
pins must be on the same level.
4. V
IH
(max) = V
CC
+ 2.0 V for pulse width
3 ns at V
CC
.
5. V
IL
(min) = V
SS
2.0 V for pulse width
3 ns at V
SS
.
HB52E649E12-A6B/B6B
Data Sheet E0020H20
10
DC Characteristics (Ta = 0 to 55C, V
CC
= 3.3 V 0.3 V, V
SS
= 0 V)
HB52E649E12
-A6B
-B6B
Parameter
Symbol
Min
Max
Min
Max
Unit
Test conditions
Notes
Operating current
(
CE
latency = 3)
I
CC1
--
2220
--
--
mA
Burst length = 1
t
RC
= min
1, 2, 3
(
CE
latency = 4)
I
CC1
--
2220
--
2220
mA
Standby current in power
down
I
CC2P
--
564
--
564
mA
CKE = V
IL
, t
CK
= 12
ns
6
Standby current in power
down (input signal stable)
I
CC2PS
--
546
--
546
mA
CKE = V
IL
, t
CK
=
7
Standby current in non
power down
I
CC2N
--
870
--
870
mA
CKE,
S
= V
IH
,
t
CK
= 12 ns
4
Active standby current in
power down
I
CC3P
--
582
--
582
mA
CKE = V
IL
, t
CK
= 12
ns
1, 2, 6
Active standby current in
non power down
I
CC3N
--
1050
--
1050
mA
CKE,
S
= V
IH
,
t
CK
= 12 ns
1, 2, 4
Burst operating current
(
CE
latency = 3)
I
CC4
--
2220
--
--
mA
t
CK
= min, BL = 4
1, 2, 5
(
CE
latency = 4)
I
CC4
--
2220
--
2220
mA
Refresh current
I
CC5
--
4470
--
4470
mA
Self refresh current
I
CC6
--
564
--
564
mA
V
IH
V
CC
0.2 V
V
IL
0.2 V
8
Input leakage current
I
LI
10
10
10
10
A
0
Vin
V
CC
Output leakage current
I
LO
10
10
10
10
A
0
Vout
V
CC
DQ = disable
Output high voltage
V
OH
2.4
--
2.4
--
V
I
OH
= 4 mA
Output low voltage
V
OL
--
0.4
--
0.4
V
I
OL
= 4 mA
Notes: 1. I
CC
depends on output load condition when the device is selected. I
CC
(max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
HB52E649E12-A6B/B6B
Data Sheet E0020H20
11
Capacitance (Ta = 25C, V
CC
= 3.3 V 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
C
I1
15
pF
1, 2, 4
Input capacitance (
RE
,
CE
,
W
)
C
I2
15
pF
1, 2, 4
Input capacitance (CKE)
C
I3
23
pF
1, 2, 4
Input capacitance (
S
)
C
I4
15
pF
1, 2, 4
Input capacitance (CK)
C
I5
40
pF
1, 2, 4
Input capacitance (DQMB)
C
I6
15
pF
1, 2, 4
Input/Output capacitance (DQ)
C
I/O1
15
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V
IH
to disable Data-out.
4. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55C, V
CC
= 3.3 V 0.3 V, V
SS
= 0 V)
HB52E649E12
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Notes
System clock cycle time
(
CE
latency = 3)
t
CK
Tclk
10
--
ns
1
(
CE
latency = 4)
t
CK
Tclk
10
--
ns
CK high pulse width
t
CKH
Tch
4
--
ns
1
CK low pulse width
t
CKL
Tcl
4
--
ns
1
Access time from CK
(
CE
latency = 3)
t
AC
Tac
--
6.9
ns
1, 2
(
CE
latency = 4)
t
AC
Tac
--
6.9
ns
Data-out hold time
t
OH
Toh
2.1
--
ns
1, 2
CK to Data-out low impedance
t
LZ
1.1
--
ns
1, 2, 3
CK to Data-out high impedance
t
HZ
--
6.9
ns
1, 4
Data-in setup time
t
DS
Tsi
2.9
--
ns
1
Data in hold time
t
DH
Thi
1.9
--
ns
1
Address setup time
t
AS
Tsi
2.6
--
ns
1
Address hold time
t
AH
Thi
1.6
--
ns
1, 5
CKE setup time
t
CES
Tsi
2.6
--
ns
1, 5
CKE setup time for power down exit
t
CESP
Tpde
2.6
--
ns
1
CKE hold time
t
CEH
Thi
1.6
--
ns
1
HB52E649E12-A6B/B6B
Data Sheet E0020H20
12
AC Characteristics (Ta = 0 to 55C, V
CC
= 3.3 V 0.3 V, V
SS
= 0 V) (cont)
HB52E649E12
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Notes
Command setup time
t
CS
Tsi
2.6
--
ns
1
Command hold time
t
CH
Thi
1.6
--
ns
1
Ref/Active to Ref/Active command period t
RC
Trc
70
--
ns
1
Active to precharge command period
t
RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t
RCD
Trcd
20
--
ns
1
Precharge to active command period
t
RP
Trp
20
--
ns
1
Write recovery or data-in to precharge
lead time
t
DPL
Tdpl
10
--
ns
1
Active (a) to Active (b) command period
t
RRD
Trrd
20
--
ns
1
Transition time (rise to fall)
t
T
1
5
ns
Refresh period
t
REF
--
64
ms
Notes: 1. AC measurement assumes t
T
= 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C
L
= 50 pF.
3. t
LZ
(min) defines the time at which the outputs achieves the low impedance state.
4. t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5. t
CES
defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
t
T
2.4 V
0.4 V
0.8 V
2.0 V
input
t
T
DQ
CL
HB52E649E12-A6B/B6B
Data Sheet E0020H20
13
Relationship Between Frequency and Minimum Latency
Parameter
HB52E649E12
Frequency (MHz)
-A6B/B6B
t
CK
(ns)
Symbol
PC100
Symbol 10
Notes
Active command to column command (same bank)
I
RCD
2
1
Active command to active command (same bank)
I
RC
7
= [I
RAS
+ I
RP
]
1
Active command to precharge command (same bank)
I
RAS
5
1
Precharge command to active command (same bank)
I
RP
2
1
Write recovery or data-in to precharge command
(same bank)
I
DPL
Tdpl
1
1
Active command to active command (different bank)
I
RRD
2
1
Self refresh exit time
I
SREX
Tsrx
2
2
Last data in to active command
(Auto precharge, same bank)
I
APW
Tdal
3
= [I
DPL
+ I
RP
]
Self refresh exit to command input
I
SEC
7
= [I
RC
]
3
Precharge command to high impedance
(
CE
latency = 3)
I
HZP
Troh
3
(
CE
latency = 4)
I
HZP
Troh
4
Last data out to active command (auto precharge)
(same bank)
I
APR
0
Last data out to precharge (early precharge)
(
CE
latency = 3)
I
EP
2
(
CE
latency = 4)
I
EP
3
Column command to column command
I
CCD
Tccd
1
Write command to data in latency
I
WCD
Tdwd
1
DQMB to data in
I
DID
Tdqm
1
DQMB to data out
I
DOD
Tdqz
3
CKE to CK disable
I
CLE
Tcke
2
Register set to active command
I
RSA
Tmrd
1
S
to command disable
I
CDD
0
Power down exit to command input
I
PEC
1
Notes: 1. I
RCD
to I
RRD
are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
HB52E649E12-A6B/B6B
Data Sheet E0020H20
14
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0, S2 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level
at the read or write command cycle CK rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
BA0/BA1 (BA) is precharged.
BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is
Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and
clock suspend modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.
V
CC
(power supply pins): 3.3 V is applied.
V
SS
(power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).
HB52E649E12-A6B/B6B
Data Sheet E0020H20
15
Physical Outline
6.35
6.35
1.00
Detail B
Detail C
Detail A
0.20
0.15
2.50
0.20
3.125
0.125
3.125
0.125
1.27
3.00 typ
133.37
+ 0.60
0.15
3.00
0.10
11.43
36.83
54.61
(63.67)
(75.113)
(29.119)
A
B
C
1
84
Front side
Back side
85
4.00
0.10
17.80
0.70
38.964
1.534
43.18
1.70
168
2
3.00
0.10
1.00
0.05
2.00
0.10
4.175
2.00
0.10
(DATUM -A-)
(DATUM -A-)
Unit: mm
(DATUM -A-)
R FULL
R FULL
Note: Tolerance on all dimensions
0.15 unless otherwise specified.
127.35
0.15
Component area
(Front)
Component area
(Back)
1.27
0.10
4.00 min
4.00 max.
133.37
0.15
HB52E649E12-A6B/B6B
Data Sheet E0020H20
16
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any
third party's patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage
when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as
fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,
fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
PDF 
ZIP