PIN NAMES
A0-A12
Row Address:
A0-A12
Column Address:
A0-A9, A11
BA0, BA1
Bank Select Address
DQ0-DQ7
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
DQM
Data Input/Output Mask
CKE0,CKE1
Clock Enables
CLK
System Clock
CS0, CS1
Chip Selects
V
CC
/V
SS
Power Supply/Ground
V
CCQ
/V
SSQ
Data Output Power/Ground
DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory devices. The 1 Gigabit SDRAM assembly utilizes the
space saving LP-StackTM technology to increase memory density. This stack is constructed with two 512Mb
(64M x 8) SDRAMs.
This 1Gb LP-StackTM has been designed to fit in the
same footprint as the 512Mb (64M x 8) SDRAM TSOPII
monolithic. This stack allows for system upgrade without
electrical or mechanical redesign, providing an
alternative low cost memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers' datasheets
Memory organization:
(2) 512Mb Memory devices. Each device arranged
as 64M x 8 bits (16M x 8 bits x 4 banks)
Memory stack organization:
128M x 8 bits (32M x 8 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and
footprint (with 2 CSs and 2 CKEs)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
This document contains information on a product presently under development at DPAC Technologies Corp.
PAC reserves the right to change products or specifications herein without prior notice.
1 Gigabit Synchronous DRAM
DPSD128ME8XKY5
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
30A226-21
REV. B 2/03
P
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PIN-OUT DIAGRAM
(TOP VIEW)
33
A8
VCC
1
DQ0
2
54
VSS
VCCQ
3
53
DQ7
N.C.
4
52
VSSQ
DQ1
5
51
N.C.
VSSQ
6
50
DQ6
N.C.
7
49
VCCQ
DQ2
8
48
N.C.
VCCQ
9
47
DQ5
N.C.
10
46
VSSQ
DQ3
11
45
N.C.
VSSQ
12
44
DQ4
N.C.
13
43
VCCQ
VCC
14
42
N.C.
CS1
15
41
VSS
WE
16
40
CKE1
CAS
17
39
DQM
RAS
18
38
CLK
CS0
19
37
CKE0
BA0
20
36
A12
BA1
21
35
A11
A10
22
34
A9
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
1
FUNCTIONAL BLOCK DIAGRAM
CAS
WE
DQ0-DQ7
CS0
RAS
CS1
CLK
A0-A12
CKE1
CKE0
BA0,BA1
(16M x 8 bits x 4 banks)
512 Mb SDRAM
(16M x 8 bits x 4 banks)
MECHANICAL DIAGRAM
.020 [.51]
.0315 [.80]
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
PIN 1
INDEX
.502.008
.891 MAX.
[12.75.20]
[22.63 MAX.]
.102 MAX. [.259 MAX]
Lead Toe-to-Toe per device datasheet
Inch [mm]
END VIEW DETAIL
.463 [11.76] TYP
COPLANARITY:
.004 [.10] from seating plane
TYP.
TYP.
30A226-21
REV. B 2/03
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPSD128ME8XKY5
512 Megabit Synchronous DRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215C.
P
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ORDERING INFORMATION
DP
-
PREFIX
SD 128M
E
8
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MODULE WITH DUAL CLOCK ENABLES
DEPTH
WIDTH
DESIG
XK
STACKABLE TSOP
SYNCHRONOUS DRAM
SUPPLIER
- DP
SUPPLIER CODE *
512 MEGABIT LVTTL BASED
MFR ID
XX
REVISION
MEMORY
X
BLANK
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
n
70P2
75P2
75
55
60
70
TIME
XXX
CYCLE
10
08
12
P12
P13
7.5ns (133MHz) CL3
5.5ns (183MHz) CL3
7ns (143MHz) CL3
6ns (166MHz) CL2
7ns (133MHz) CL2
7.5ns (133MHz) CL2
PC100 / CL2
12ns (83MHz)
8ns (125MHz)
10ns (100MHz)
PC100 / CL3
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