256 Megabit CMOS DRAM w/ Parity
DPD8MX36RKY5
PRELIMINARY
DESCRIPTION:
The DPD8MX36RKY5 is the 8 Meg x 36 Dynamic RAM module
that utilize the new and innovative space saving TSOP stacking
technology. The module is constructed of four 4 Meg x 16 and
two 4Mx4 quad CAS Dynamic RAM's that are configured as 2
banks of 4 Meg x 36.
The DPD8MX36RKY5 provides for a compatible upgrade path
to lower density compatible modules. The module features high
speed access times, common data inputs and outputs, and three
standard refresh modes.
FEATURES:
Access Times: 50, 60, 70ns (max.)
Byte Wide Control
5.0 Volt Supply
Common Data Inputs and Outputs
Fast Page Mode Capability
4096 Cycles / 64 ms
3 Variations of Refresh:
- RAS only Refresh
- CAS before RAS Refresh
- Hidden Refresh
Package: TSOP Leadless Stack
PIN-OUT DIAGRAM
NOTE: A12 for 8K refresh product, inquire factory.
FUNCTIONAL BLOCK DIAGRAM
8Mx36, 50 - 70ns, TSTACK
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This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
PIN NAMES
A0 - A11
Row Address:
A0 - A11
Column Address: A0 - A9
Refresh Address: A0 - A11
DQ0 - DQ31
Data In / Data Out
CAS0 - CAS3
Column Addres Strobe
RAS0 - RAS1
Row Address Enables
PAR0 - PAR3
Parity Data In/Data Out
WE
Data Write Enable
OE
Data Output Enable
V
DD
Power Supply (+5V)
V
SS
Ground
N.C.
No Connect
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DPD8MX36RKY5
Dense-Pac Microsystems, Inc.
PRELIMINARY
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way Garden Grove , California 92841-1431
(714) 898-0007 (800) 642-4477
(Outside CA)
FAX: (714) 897-1772 http://www.dense-pac.com
ORDERING INFORMATION
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