DPS 9455B
Dec/2003
PRODUCT INFORMATION
DPS 9455B
Display Processor and Scaler with HDTV and PC Input
The DPS 9455B is a single-chip digital dis-
play processor and scaler, especially
designed for FPD-TV sets (LCD-TV, PDP-
TV) supporting HDTV signal input and de-
interlacing as well as PC-signal input. The
DPS 9455B is a new member of Micronas'
IC family implemented in deep submicron
CMOS technology.
Video Inputs
Digital input for 50/60 I or 50/60 P sig-
nals in ITU-656 (8 bit) or ITU-601 (16 bit)
3
8 bit YC
r
C
b
/RGB input
2 analog RGB/YC
r
C
b
inputs for Teletext,
graphics, 480p, 576p, 1080i and 720p
4 built-in ADCs (8-bit) for RGB + Fast-
Blank with 81 MHz sampling rate
PC input up to XGA at 75 Hz and
WXGA at 60 Hz
Separate HS and VS (2
) inputs
Sync Processing
3-level sync-separation for 1080i
and 720p
HS and VS outputs to synchronize
the ext. analog RGB/ YC
r
C
b
source in
the softmix mode (see display modes)
external OSD source
Display Modes
Digital mode: video from the digital input
Analog mode: video/graphics/Teletext
from the analog RGB/YC
r
C
b
input
Softmix mode: soft mixing of the video
and component input
OSD signals can be inserted digitally
Video Processing
Full 4:4:4 processing
RGB-to-YC
r
C
b
conversion
Brightness, contrast, saturation for
analog component input
Dynamic contrast improvement (DCI)
Black level expander (BLE)
Luma & chroma transition improvement
Dynamic peaking
Brightness, contrast, saturation, tint
Programmable YC
r
C
b
-to-RGB matrix
Programmable characteristics on
R, G, B, for
-correction, blue-stretch,
white-drive
Dithering for 8 to 6-bit digital outputs
Display Format Processing
Prescaling of the input signal:
horizontal scaling factor: 1.0 to 1/64
Upscaling of the output signal:
horizontal scaling factor: 1 to 4
(5-zone panorama generator)
Vertical scaling factor: 0.5 to 4
De-interlacing with line-doubling/
upscaling
OSD
digital RGB input (6 or 12 bit/pixel)
64 entry CLUT with 12-bit colors
Picture frame and testpattern generation
Half-contrast switch (0, 25%, 50%, 100%)
Display Resolutions
640
480 (VGA; 4:3 panel)
852
480 (W-VGA; 16:9 panel)
800
600 (SVGA)
1024
768 (XGA)
1366
768 (W-XGA)
PRODUCT INFORMATION
DPS 9455B
Dec/2003
All information and data contained in this product information are without any commitment, are not to be consid-
ered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or
development sample availability and delivery are exclusively subject to our respective order confirmation form. By
this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third
parties which may result from its use.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
www.micronas.com
No part of this publication may be reproduced, photo-
copied, stored on a retrieval system, or transmitted
without the express written consent of Micronas GmbH.
Edition Dec. 17, 2003; Order No. 6251-637-1PI
I
2
C
Interface
Compontent
Input
Source Select
4 ADCs
Test Controller
Channel
Mixer
PCK1/2
ITU656
ITU601
Decoder
Scaler and
De-Interlacer
lin. H/V-Scaler
nonlin. H-Scaler
De-Interlacing
Picture
Improvements
LTI/CTI
Peaking
Blacklevel
Expander
Picture
Settings
Contrast
Brightness
Saturation
Tint
Matrix
Gamma
RGBOUT
24
16
24
11
PanelCtrl
36
12
2
ITU Domain
Input Domain
Display Domain
Pixel
Mixer
Cr/RIN1
Y/GIN1
Cb/BIN1
Cr/RIN2
Y/GIN2
Cb/BIN2
CLKIN
CLKF
SCL SDA
XOUT CLK20/XIN
CS
TEST
RESET
TDI
TMS
TCK
TDO
Dithering
and Panel
Controlling
Input Video
Processing
Upsampling
(422-444)
Line-doubling
(optional)
ITU/
RGB/
YUVIN
HOUT
VOUT
Sync
Slicer
VIN2
HIN2
VIN
HIN
LL PLL
Component
Processing
RGB
YC
r
C
b
Contrast
Brightness
Saturation
Format Detection
DPS 9455B
648 MHz
DTO
Divider
Xtal
Oscillator
OSDHC
OSDFB
OSDRGB
OSDHV
2
OSDCLK
Digital OSD Input
6/12 bit
Horizontal Expansion
Picture Frame
Testpattern
FBL1/HS
FBL2/HS
MSP
34/44xy
VPC 32xy
or
VSP 94xy
FRC
94xy*
DPS
9455
SDA
600x
CVBS
ITU
656
ITU
656
RGB, FB
Line In
Tuner
Line Out
Main
Headphones
Center
Surround
Subwoofer
SL, SL
L, R
L, R
SCART
DVD/STB
L, R
Analog
YCrCb
Y/C
Audio
SIF
CVBS
Digital YCrCb
ITUR 656
480p 1080i (D1 D4)
*
optional
PC-Input VGA - WXGA
or
ITU
601
LVDS
Output Interface
2
18 or 24-bit RGB output: dual-pixel
mode
programmable panel control signals
Miscellaneous
Up to 2 PWM outputs
Up to 8 general-purpose I/Os
I
2
C interface (400 kHz)
JTAG boundary scan interface
1.8 V and 3.3 V supply
PMQFP144 package
System Architecture
Figure 2 shows the block diagram of the
DPS 9455B. The device has digital outputs.
In principle, the device comprises three
major functional and clock domain parts.
The functional parts are
Video input processing,
Scaling, and
Display processing.
The clock domains are
ITU domain,
Input domain, and
Display domain (compare the block dia-
gram and the different shaded areas).
The input and the output signals of the IC
can be chosen in various configurations.
Fig. 2: Block diagram of the DPS 9455B
Fig. 1: Application example: LCD-TV with DPS 9455B and HDTV Input
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