Frequency Multiplying, Peak Reducing EMI Solution
W532
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07253 Rev. *A
Revised December 28, 2002
Features
Cypress PREMISTM family offering
Generates an EMI optimized clocking signal at the
output
Selectable frequency range and multiplication factor
Single 1.25% or 5% center spread output
Integrated loop filter components
Operates with a 3.3V or 5V supply
Low power CMOS design
Available in 16-pin SOIC
Key Specifications
Supply Voltages: ........................................V
DD
= 3.3V 0.3V
or V
DD
= 5V 10%
Frequency Range: .........................15 MHz
F
out
120 MHz
Cycle to Cycle Jitter: ......................................... 150 ps (typ.)
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time ................................... 5 ns (max.)
PREMIS is a trademark of Cypress Semiconductor.
Table 1. Output Frequency Range Selection
OR2
OR1
Output Range
(Multiplication Factor Selection)
0
0
reserved
0
1
15 MHz
F
IN
30 MHz
1
0
30 MHz
F
IN
60 MHz
1
1
60 MHz
F
IN
120 MHz
Table 2. Modulation Width Selection
MW
Output
0
F
avg
+
0.625%
F
out
F
avg
0.625%
1
F
avg
+
2.5%
F
out
F
avg
2.5%
Table 3. Input Frequency Range Selection
IR2
IR1
Input Range
0
0
reserved
0
1
15 MHz
F
IN
30 MHz
1
0
30 MHz
F
IN
60 MHz
1
1
60 MHz
F
IN
120 MHz
Simplified Block Diagram
Pin Configuration
SOIC
Spread Spectrum
W532
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W532
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
X1
W5
32
16
15
14
13
1
2
3
4
X1
X2
AVDD
*OR1
VDD
GND
IR1^
5
6
7
10
11
12
IR2^
SSOUT
NC
AGND
8
9
VDD
MW*
^OR2
*SSON#
GND
Notes:
1.
^ pins have internal pull-up
2.
* pins have internal pull-down
W532
Document #: 38-07253 Rev. *A
Page 2 of 8
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
SSOUT
12
O
Output Modulated Frequency: Frequency modulated signal. Frequency of
the output is selected as shown in Table 1.
CLKIN or X1
1
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
2
I
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference signal, this pin must be left unconnected.
SSON#
8
I
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
MW
9
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
these pins are used to select the amount of variation and peak EMI reduction
that is desired on the output signal (see Table 2).
IR1:2
14, 13
I
Reference Frequency Selector: Logic level provided at this input indicates
to the internal logic what range the reference frequency is in and determines
the factor by which the device multiplies the input frequency. Refer to Table 3.
These pins have internal pull-up resistors.
OR1:2
4, 7
I
Output Frequency Selection Bits: These pins select the frequency of oper-
ation for the output. Refer to Table 1. OR1: DOWN - OR2: UP.
VDD
3, 10, 16
P
Power Connection: Connected to 3.3V or 5V power supply.
GND
6, 11, 15
G
Ground Connection: Connect all ground pins to the common ground plane.
NC
5
NC
No Connect: Leave this pin floating.
W532
Document #: 38-07253 Rev. *A
Page 3 of 8
Overview
The W532 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram on page 1 shows a simple implementa-
tion.
Functional Description
The W532 uses a phase-locked loop (PLL) to frequency mod-
ulate an input clock. The result is an output clock whose fre-
quency is slowly swept over a narrow band near the input sig-
nal. The basic circuit topology is shown in Figure 1. The input
reference signal is divided by Q and fed to the phase detector.
A signal from the VCO is divided by P and fed back to the
phase detector also. The PLL will force the frequency of the
VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. The unique feature of the
Spread Spectrum Frequency Timing Generator is that a mod-
ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (IR1:2, OR1:2 pins), the frequency
range can be set (see Table 1 and Table 3). Spreading per-
centage is set with pin MW as shown in Table 2.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
Figure 1. Conceptual Block Diagram
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
V
DD
Q
P
Clock Input
Reference Input
(EMI suppressed)
W532
Document #: 38-07253 Rev. *A
Page 4 of 8
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
f
Center
X
MOD
% in the frequency spread selection table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is f
MAX
X
MOD
%. Whenever this expression is used,
Cypress has taken care to ensure that f
MAX
will never be ex-
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
SSON# Pin
An internal pull-down resistor defaults the chip into spread
spectrum mode. When the SSON# pin is asserted (active
LOW) the spreading feature is enabled. Spreading feature is
disabled when SSON# is set HIGH (V
DD
).
Figure 2. Typical Clock and SSFTG Comparison
Figure 3. Modulation Waveform Profile
SSFTG
Typical Clock
5dB/div
Am
p
l
i
t
u
d
e
(
d
B)
100%
60%
20%
80%
40%
0%
20%
40%
60%
80%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Time
F
r
eq
u
e
n
cy Sh
i
f
t
W532
Document #: 38-07253 Rev. *A
Page 5 of 8
Absolute Maximum Ratings
[3]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any Pin with Respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70 or
40 to +85
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics
: 0C < T
A
< 70C or 40C to +85C, V
DD
= 3.3V 0.3V
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
18
32
mA
t
ON
Power-Up Time
First locked clock cycle after Power
Good
5
ms
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.4
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 4
50
A
I
IH
Input High Current
Note 4
50
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 3.3V
15
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 3.3V
15
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
150
k
Z
OUT
Clock Output Impedance
25
Note:
3.
Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
4.
Inputs OR2 and IR1:2 have a pull-up resistor, Inputs SSON# OR1 and MW have a pull-down resistor.
W532
Document #: 38-07253 Rev. *A
Page 6 of 8
DC Electrical Characteristics:
0C < T
A
< 70C or 40C to +85C, V
DD
= 5V 10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
30
50
mA
t
ON
Power-Up Time
First locked clock cycle after
Power Good
5
ms
V
IL
Input Low Voltage
0.15V
DD
V
V
IH
Input High Voltage
0.7V
DD
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 4
50
A
I
IH
Input High Current
Note 4
50
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 5V
24
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 5V
24
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
150
k
Z
OUT
Clock Output Impedance
25
AC Electrical Characteristics:
T
A
= 0C to +70C or 40C to +85C, V
DD
= 3.3V 0.3V or 5V10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f
IN
Input Frequency
Input Clock
14
120
MHz
f
OUT
Output Frequency
Spread Off
13
120
MHz
t
R
Output Rise Time
V
DD
, 15-pF load, 0.82.4V
2
5
ns
t
F
Output Fall Time
V
DD
, 15-pF load, 2.40.8V
2
5
ns
t
OD
Output Duty Cycle
15-pF load
40
60
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
150
300
ps
Ordering Information
Ordering Code
Package
Name
Package Type
Temperature Range
W532
G
16-Pin Plastic SOIC (300-mil)
Commercial (0 70)
W532
GI
16-Pin Plastic SOIC (300-mil)
Industrial (40 85)
W532
Document #: 38-07253 Rev. *A
Page 7 of 8
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
16-Pin Small Outline Integrated Circuit (SOIC, 300-mil)
W532
Document #: 38-07253 Rev. *A
Page 8 of 8
Document Title: W532 Frequency Multiplying, Peak Reducing EMI Solution
Document Number: 38-07253
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110518
01/07/02
SZV
Change from Spec number: 38-01061 to 38-07253
*A
122695
12/28/02
RBI
Add power up requirements to maximum ratings information.
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