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PRELIMINARY
hyperCache
TM
/ Stand-Alone PCI Peripheral
Controller with USB
CY82C693UB
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 25, 1997 - Revised December 10, 1997
B
Features
PCI to ISA bridge
PCI Bus Rev. 2.1 compliant
Supports up to 5 additional PCI masters including the
CY82C691
Integrated DMA controllers with Type A, B, and F sup-
port
Integrated Interrupt controllers
Integrated timer/counters
Integrated Real-Time-Clock with 256 bytes of bat-
tery-backed SRAM (14 bytes of clock RAM and 242
bytes of CMOS scratch RAM)
Write-only Register Shadowing
Integrated Dual-Channel enhanced IDE controller with
-- PCI bus mastering
-- CD ROM support
-- PIO modes 0 through 4 operation
-- Single-word and Multi-word DMA modes 0 through 2
Integrated Keyboard Controller
APM compliant power management support through
SMM or under hardware control
Flash PROM support with write-protection
Power-on reset circuitry
QuietBus
TM
support for the PCI and ISA bus interfaces
for better noise immunity
General-purpose I/O pins and registers
USB Host/Hub controller with 2 USB ports
Flexible Stand-Alone configuration options
Packaged in a 208-pin PQFP
hyperCache and QuietBus are trademarks of Cypress Semiconductor Corporation.
Pentium is a trademark of Intel Corporation.
PCI LOCAL BUS
CY82C692
CY82C693UB
CY82C691
Intel
Pentium
Processor,
Cyrix M1
or
AMD K5, K6
Cypress
Clock
CY2254ASC-2
CY82C694
Expansion Cache
EPROM
CY27C010
or Flash
BIOS
DRAM
Lower 4 Bytes
DRAM
Upper 4 bytes
ISA Bus
TAG
Standard or EDO DRAMs
IDE devices
DRAMAddress,
DRAMControl
DRAM
Data[0:31]
DRAM
Data[32:63]
Control
USB Bus
CACHE
System Block Diagram
TM
CY82C693UB
PRELIMINARY
2
TABLE OF CONTENTS
Features ................................................................................................................................................... 1
CY82C693UB Signals ........................................................................................................................... 11
Pin Configuration ................................................................................................................................... 12
CY82C693UB Pin Reference (In Numerical Order by Pin Number) ...................................................... 13
CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) ................................................. 14
Introduction ............................................................................................................................................ 17
System Overview ............................................................................................................................................. 17
CY82C693UB Introduction .............................................................................................................................. 17
Functional Overview .............................................................................................................................. 17
PCI Bus Interface ............................................................................................................................................ 17
ISA Bus Interface ............................................................................................................................................. 18
Reset Logic ...................................................................................................................................................... 18
Keyboard Controller ......................................................................................................................................... 19
Operating Frequency ....................................................................................................................................................19
Resetting the Keyboard Controller ...............................................................................................................................19
Host Interface ...............................................................................................................................................................19
PS/2 Compatible Mouse Support .................................................................................................................................19
Keyboard Interface .......................................................................................................................................................19
Maximum Flexibility ......................................................................................................................................................19
Keyboard Self-Test .......................................................................................................................................................19
Power Management Logic ............................................................................................................................... 19
AT Refresh Logic ............................................................................................................................................. 20
Pre-Read/Post-Write Buffers ........................................................................................................................... 20
BIOS ROM Control .......................................................................................................................................... 20
Timer/Counter Logic ........................................................................................................................................ 20
DMA Controllers .............................................................................................................................................. 21
DMA Controller Transfer Modes ...................................................................................................................................21
IDE Controller .................................................................................................................................................. 21
Real-Time-Clock .............................................................................................................................................. 21
RTC Address Map ........................................................................................................................................................22
External RTC Control ...................................................................................................................................................22
Interrupt Controllers ......................................................................................................................................... 22
NMI Sources .................................................................................................................................................................23
Stand-Alone Operation .................................................................................................................................... 23
Use With An External PCI Arbiter .................................................................................................................................23
Splitting GNTBSY .........................................................................................................................................................23
External Reset Control .................................................................................................................................................24
FREQACK Bypassing ..................................................................................................................................................24
32-Bit I/O Space Decode ..............................................................................................................................................24
1 Mbyte ROM Decode ..................................................................................................................................................24
Universal Serial Bus (USB) Host Controller .................................................................................................... 24
CY82C693UB Signal Description .......................................................................................................... 25
Reset Signals .................................................................................................................................................. 25
PCI Interface Signals ....................................................................................................................................... 25
ISA Interface Signals ....................................................................................................................................... 27
Power Management Signals ............................................................................................................................ 33
Keyboard Interface Signals ............................................................................................................................. 33
IDE Interface Signals ....................................................................................................................................... 33
USB Interface Signals ..................................................................................................................................... 34
Miscellaneous Signals ..................................................................................................................................... 34
hyperCache Memory and I/O Map ......................................................................................................... 35
CY82C693UB Control Registers ........................................................................................................... 37
CY82C693UB
PRELIMINARY
3
TABLE OF CONTENTS
(continued)
Register 1: Peripheral Configuration Register #1 (Read/Write) -- Index=01H ................................................ 37
Register 2: Peripheral Configuration Register #2 (Read/Write) - Index=02H .................................................. 38
Register 3: Interrupt Request Level/Edge Control Register #1 (Read/Write) - Index=03H ............................. 38
Register 4: Interrupt Request Level/Edge Control Register #2 (Read/Write) - Index=04H ............................. 39
Register 5: Real-Time-Clock Configuration Register (Read/Write) - Index=05H ............................................ 39
Write-Only Shadow Registers ................................................................................................................ 40
Register 80: DMA1 Write Request Shadow Register (Read/Write) - Index=80H ........................................... 40
Register 81: DMA1 Write Single Mask Bit Shadow Register (Read/Write) - Index=81H ................................ 40
Register 82: DMA1 Write Mode Shadow Register (Read/Write) - Index=82H ............................................... 40
Register 83: DMA1 Clear Byte Pointer Shadow Register (Read/Write) - Index=83H ..................................... 40
Register 84: DMA1 Master Clear Shadow Register (Read/Write) - Index=84H ............................................. 40
Register 85: DMA1 Clear Mask Shadow Register (Read/Write) - Index=85H ................................................ 40
Register 86: Timer Counter 1 Command Mode Shadow Register (Read/Write) - Index=86H ....................... 40
Register 87: CMOS Battery-Backed RAM Address and NMI Mask Registers Shadow Register
(Read/Write) - Index=87H ............................................................................................................................... 40
Register 88: DMA2 Write Request Shadow Register (Read/Write) - Index=88H ........................................... 40
Register 89: DMA2 Write Single Mask Bit Shadow Register (Read/Write) - Index=89H ................................ 41
Register 8A: DMA2 Write Mode Shadow Register (Read/Write) - Index=8AH ............................................... 41
Register 8B: DMA2 Clear Byte Pointer Shadow Register (Read/Write) - Index=8BH .................................... 41
Register 8C: DMA2 Mask Clear Shadow Register (Read/Write) - Index=8CH .............................................. 41
Register 8D: DMA2 Clear Mask Shadow Register (Read/Write) - Index=8DH .............................................. 41
Register 8E: Coprocessor Error Shadow Register (Read/Write) - Index=8EH ............................................... 41
Register 8F: Extended CMOS RAM address Shadow Register (Read/Write) - Index=8FH ........................... 41
General Purpose I/O Registers .............................................................................................................. 42
Register 90: General Purpose I/O Control Register A (Read/Write) - Index=90H .......................................... 42
Register 91: General Purpose I/O Input/Output Control Register A (Read/Write) - Index=91H ..................... 42
Register 92: General Purpose I/O Control Register B (Read/Write) - Index=92H .......................................... 43
Register 93: General Purpose I/O Input/Output Control Register B (Read/Write) - Index=93H ..................... 43
Power Management Control Registers .................................................................................................. 44
Register 40: Standby Timer Event Detection Control (Read/Write) - Index=40H ........................................... 44
Register 41: Standby Timer Interrupt Request Detection Control #1 (Read/Write) - Index=41H ................... 45
Register 42: Standby Timer Interrupt Request Detection Control #2 (Read/Write) - Index=42H ................... 45
Register 43: Standby Timer DMA Request Detection Control #1 (Read/Write) - Index=43H ......................... 46
Register 44: Suspend Timer Event Detection Control (Read/Write) - Index=44H .......................................... 46
Register 45: Suspend Timer Interrupt Request Detection Control #1 (Read/Write) - Index=45H .................. 47
Register 46: Suspend Timer Interrupt Request Detection Control #2 (Read/Write) - Index=46H .................. 47
Register 47: Suspend Timer DMA Request Detection Control #1 (Read/Write) - Index=47H ........................ 48
Register 48: User Timer 1 Event Detection Control (Read/Write) - Index=48H ............................................. 48
Register 49: User Timer 1 Interrupt Request Detection Control #1 (Read/Write) - Index=49H ...................... 49
Register 4A: User Timer 1 Interrupt Request Detection Control #2 (Read/Write) - Index=4AH ..................... 49
Register 4B: User Timer 1 DMA Request Detection Control #1 (Read/Write) - Index=4BH .......................... 50
Register 4C: Throttle Timer Event Detection Control (Read/Write) - Index=4CH ........................................... 50
Register 4D: Throttle Timer Interrupt Request Detection Control #1 (Read/Write) - Index=4DH ................... 51
Register 4E: Throttle Timer Interrupt Request Detection Control #2 (Read/Write) - Index=4EH ................... 51
Register 4F: Throttle Timer DMA Request Detection Control #1 (Read/Write) - Index=4FH ......................... 52
Register 50: Non-motherboard Memory Address Range Decode for Event Detection
Register #1 (Read/Write) - Index=50H ........................................................................................................... 52
Register 51: Non-motherboard Memory Address Range Decode for Event Detection
Register #2 (Read/Write) - Index=51H ........................................................................................................... 52
Register 52: Non-motherboard Memory Address Mask for Event Detection Register #1
(Read/Write) - Index=52H ............................................................................................................................... 52
CY82C693UB
PRELIMINARY
4
TABLE OF CONTENTS
(continued)
Register 53: Non-motherboard Memory Address Mask for Event Detection Register #2
(Read/Write) - Index=53H ............................................................................................................................... 52
Register 54: Programmable I/O Trap 1 Address Range Register #1 (Read/Write) - Index=54H ................... 52
Register 55: Programmable I/O Trap 1 Address Range Register #2 (Read/Write) - Index=55H ................... 53
Register 56: Programmable I/O Trap 1 Address Range Register #3 (Read/Write) - Index=56H ................... 53
Register 57: Programmable I/O Trap 1 Address Range Register #4 (Read/Write) - Index=57H ................... 53
Register 58: Programmable I/O Trap 2 Address Range Register #1 (Read/Write) - Index=58H ................... 53
Register 59: Programmable I/O Trap 2 Address Range Register #2 (Read/Write) - Index=59H ................... 53
Register 5A: Programmable I/O Trap 2 Address Range Register #3 (Read/Write) - Index=5AH .................. 53
Register 5B: Programmable I/O Trap 2 Address Range Register #4 (Read/Write) - Index=5BH .................. 53
Register 5C: Programmable I/O Trap 1 Address Detection Control (Read/Write) - Index=5CH .................... 54
Register 5D: Programmable I/O Trap 2 Address Detection Control (Read/Write) - Index=5DH .................... 54
Register 5E: I/O Trap 1 and 2 Monitoring Control (Read/Write) - Index=5EH ................................................ 55
Register 5F: Standby and Suspend Timer Terminal Count Control Register (Read/Write) - Index=5FH ....... 55
Register 60: User Timer 1 and User Timer 2 Terminal Count Control Register (Read/Write) - Index=60H ... 56
Register 61: User Timer 3 Terminal Count Control Register (Read/Write) - Index=61H ................................ 56
Register 62: Throttle Timer Terminal Count Control Register (Read/Write) - Index=62H .............................. 57
Register 63: Power Management Control Register#1 (Read/Write) - Index=63H .......................................... 57
Register 64: Power Management Control Register#2 (Read/Write) - Index=64H .......................................... 58
Register 65: Power Management Clock Control Register (Read/Write) - Index=65H .................................... 58
Register 66: STOPCLK Control Register (Read/Write) - Index=66H ............................................................. 59
Register 67: Power Management SMI Control Register (Read/Write) - Index=67H ....................................... 59
Register 70: Power Management SMI Enable Register #1 (Read/Write) - Index=70H .................................. 60
Register 71: Power Management SMI Enable Register #2 (Read/Write) - Index=71H .................................. 60
Register 72: Power Management SMI Enable Register #3 (Read/Write) - Index=72H .................................. 61
Register 73: Power Management SMI Enable Register #4 (Read/Write) - Index=73H .................................. 61
Register 74: Power Management SMI Enable Register #5 (Read/Write) - Index=74H .................................. 62
Register 75: Power Management SMI Enable Register #6 (Read/Write) - Index=75H .................................. 62
Register 76: Power Management SMI Status Register #1 (Read/Write) - Index=76H ................................... 63
Register 77: Power Management SMI Status Register #2 (Read/Write) - Index=77H ................................... 64
Register 78: Power Management SMI Status Register #3 (Read/Write) - Index=78H ................................... 65
Register 79: Power Management Interrupt Request Status Register #1 (Read/Write) - Index=79H .............. 66
Register 7A: Power Management Interrupt Request Status Register #2 (Read/Write) - Index=7AH ............. 67
Register 7B: Power Management DMA Request Status Register (Read/Write) - Index=7BH ....................... 68
Register 7C: Reserved - Index=7CH ............................................................................................................... 69
Register 7D: Reserved - Index=7DH .............................................................................................................. 69
Register 7E: Reserved - Index=7EH .............................................................................................................. 69
Register 7F: Reserved - Index=7FH ............................................................................................................... 69
Special I/O Port Registers ..................................................................................................................... 70
Port 61: System Control Port B, NMI (Read/Write) - I/O Address=061H ......................................................... 70
Port 70: RTC/Configuration RAM Address Port, NMI (Write) - I/O Address=070H ......................................... 70
Port 92: PS/2 Reset Control (Read/Write) - I/O Address=092H ...................................................................... 70
Port B2: APM Control Port (Read/Write) - I/O Address=0B2H ........................................................................ 71
Port B3: APM Status Port (Read/Write) - I/O Address=0B3H ......................................................................... 71
CY82C693UB DMA Controller Registers .............................................................................................. 72
DMA Register 0: DMAC1 Channel 0 Current Address Register (Read/Write) - I/O Address=000H ............... 72
DMA Register 1: DMAC1 Channel 0 Current Word Count Register (Read/Write) - I/O Address=001H ......... 72
DMA Register 2: DMAC1 Channel 1 Current Address Register (Read/Write) - I/O Address=002H ............... 72
DMA Register 3: DMAC1 Channel 1 Current Word Count Register (Read/Write) - I/O Address=003H ......... 73
DMA Register 4: DMAC1 Channel 2 Current Address Register (Read/Write) - I/O Address=004H ............... 73
DMA Register 5: DMAC1 Channel 2 Current Word Count Register (Read/Write) - I/O Address=005H ......... 73
DMA Register 6: DMAC1 Channel 3 Current Address Register (Read/Write) - I/O Address=006H ............... 73
CY82C693UB
PRELIMINARY
5
TABLE OF CONTENTS
(continued)
DMA Register 7: DMAC1 Channel 3 Current Word Count Register (Read/Write) - I/O Address=007H ......... 73
DMA Register 8: DMAC1 Status/Command Register (Read/Write) - I/O Address=008H ............................... 73
Status Register Format (Read Only) ............................................................................................................... 74
Command Register Format (Write Only) ......................................................................................................... 75
DMA Register 9: DMAC1 DMA Request Register (Write Only) - I/O Address=009H ...................................... 75
DMA Request Register Write Format .............................................................................................................. 75
DMA Register 10: DMAC1 DMA Command/Mask Register (Write Only) - I/O Address=00AH ....................... 76
DMA Request Mask Register Write Single Bit Format .................................................................................... 76
DMA Register 11: DMAC1 DMA Mode Register (Write Only) - I/O Address=00BH ........................................ 76
Mode Register Format ..................................................................................................................................... 77
DMA Register 12: DMAC1 Address Space Expansion Flip-Flop Control Register (Write Only) -
I/O Address=00CH .......................................................................................................................................... 77
DMA Register 13: DMAC1 Master Clear Register (Write Only) - I/O Address=00DH ..................................... 77
DMA Register 14: DMAC1 DMA Mask Clear Register (Write Only) - I/O Address=00EH ............................... 77
DMA Register 15: DMAC1 Request Mask Register Control (Read/Write) - I/O Address=00FH ..................... 78
DMA Request Mask Register Read and Write All Bits Format ........................................................................ 78
DMA Register 16: DMAC2 Channel 0 (Channel 4) Current Address Register (Read/Write) -
I/O Address=0C0H .......................................................................................................................................... 78
DMA Register 17: DMAC2 Channel 0 (Channel 4) Current Word Count Register (Read/Write) -
I/O Address=0C2H .......................................................................................................................................... 78
DMA Register 18: DMAC2 Channel 1 (Channel 5) Current Address Register (Read/Write) -
I/O Address=0C4H .......................................................................................................................................... 78
DMA Register 19: DMAC2 Channel 1 (Channel 5) Current Word Count Register (Read/Write) -
I/O Address=0C6H .......................................................................................................................................... 79
DMA Register 20: DMAC2 Channel 2 (Channel 6) Current Address Register (Read/Write) -
I/O Address=0C8H .......................................................................................................................................... 79
DMA Register 21: DMAC2 Channel 2 (Channel 6) Current Word Count Register (Read/Write) -
I/O Address=0CAH .......................................................................................................................................... 79
DMA Register 22: DMAC2 Channel 3 (Channel 7) Current Address Register (Read/Write) -
I/O Address=0CCH .......................................................................................................................................... 79
DMA Register 23: DMAC2 Channel 3 (Channel 7) Current Word Count Register (Read/Write) -
I/O Address=0CEH .......................................................................................................................................... 79
DMA Register 24: DMAC2 Status/Command Register (Read/Write) - I/O Address=0D0H ............................. 79
Status Register Format (Read Only) ............................................................................................................... 80
Command Register Format (Write Only) ......................................................................................................... 81
DMA Register 25: DMAC2 DMA Request Register (Write Only) - I/O Address=0D2H ................................... 81
DMA Request Register Write Format .............................................................................................................. 81
DMA Register 26: DMAC2 DMA Command/Mask Register (Write Only) - I/O Address=0D4H ...................... 82
DMA Request Mask Register Write Single Bit Format .................................................................................... 82
DMA Register 27: DMAC2 DMA Mode Register (Write Only) - I/O Address=0D6H ........................................ 82
Mode Register Format ..................................................................................................................................... 83
DMA Register 28: DMAC2 Address Space Expansion Flip-Flop Control Register (Write Only) -
I/O Address=0D8H .......................................................................................................................................... 83
DMA Register 29: DMAC2 Master Clear Register (Write Only) - I/O Address=0DAH ..................................... 83
DMA Register 30: DMAC2 DMA Mask Clear Register (Write Only) - I/O Address=0DCH .............................. 83
DMA Register 31: DMAC2 Request Mask Register Control (Read/Write) - I/O Address=0DEH .................... 84
DMA Request Mask Register Read and Write All Bits Format ........................................................................ 84
DMA Register 32: DMAC1 Channel 2 Page Address Register (Read/Write) - Index=081H ........................ 84
DMA Register 33: DMAC1 Channel 3 Page Address Register (Read/Write) - Index=082H ........................ 84
DMA Register 34: DMAC1 Channel 1 Page Address Register (Read/Write) - Index=083H ........................ 84
DMA Register 35: DMAC1 Channel 0 Page Address Register (Read/Write) - Index=087H ........................ 84
DMA Register 36: DMAC2 Channel 6 Page Address Register (Read/Write) - Index=089H ........................ 84
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