CMOS Generic 24-Pin
Reprogrammable Logic Device
PLDC20G10B/PLDC20G10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03010 Rev. **
Revised March 26, 1997
Features
Fast
-- Commercial: t
PD
= 15 ns, t
CO
= 10 ns, t
S
= 12 ns
-- Military: t
PD
= 20 ns, t
CO
= 15 ns, t
S
= 15 ns
Low power
-- I
CC
max.: 70 mA, commercial
-- I
CC
max.: 100 mA, military
Commercial and military temperature range
User-programmable output cells
-- Selectable for registered or combinatorial operation
-- Output polarity control
-- Output enable source selectable from pin 13 or prod-
uct term
Generic architecture to replace standard logic func-
tions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10,
14L8, 16L6, 18L4, 20L2, and 20V8
Eight product terms and one OE product term per out-
put
CMOS EPROM technology for reprogrammability
Highly reliable
-- Uses proven EPROM technology
-- Fully AC and DC tested
-- Security feature prevents logic pattern duplication
--
10% power supply voltage and higher noise immu-
nity
Functional Description
Cypress PLD devices are high-speed electrically programma-
ble logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program cus-
tom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
Note:
1.
The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts.
The difference is in the location of the "no connect" or NC pins.
Logic Block Diagram
Pin Configurations
20G101
8
9
8
7
6
5
4
3
2
1
10
15
16
17
18
19
20
21
22
23
24
PROGRAMMABLE
ANDARRAY
I
I
I
I
I
I
I
I
CP/I
OUTPUT
CELL
8
OUTPUT
CELL
8
OUTPUT
CELL
OE
OE
OE
8
OE
OUTPUT
CELL
8
OE
OUTPUT
CELL
8
OE
OUTPUT
CELL
8
OE
OUTPUT
CELL
8
OE
OUTPUT
CELL
V
CC
11
12
13
14
I
V
SS
I/OE
8
OUTPUT
CELL
8
OUTPUT
CELL
I
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I
I
I
I
I
NC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
I
I
I
I
I
I
NC
9
I
I
V
I/
O
I/
O
8
I/O
I/O
V
I
I
SS
I
I
CP/I
V
I/O
I/O
0
1
0
1
CC
CC
9
8
I/
O
I/
O
V
I
I
SS
1
1
CP/I
NC
20G102
20G103
I
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
I/OE
NC
PLDC20G10
PLDC20G10B
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
NC
I
I
I
I
NC
I
I
CP/I
V
I/O
I/O
0
1
CC
9
8
I/
O
I/
O
I
I
1
V SS
20G104
I
NC
I
I/OE
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
JEDEC PLCC
Top View
STD PLCC
Top View
LCC
Top View
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
NC
I/OE
PLDC20G10
PLDC20G10B
CG7C323A
CG7C323BA
NC
[1]
PLDC20G10B/PLDC20G10
Document #: 38-03010 Rev. **
Page 2 of 13
Functional Description
(continued)
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be pro-
grammed to logic functions that include but are not limited to:
20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of defin-
ing the architecture of each output individually. Each of the 10
output cells may be configured with registered or combinatorial
outputs, active HIGH or active LOW outputs, and product term
or Pin 13 generated output enables. Three architecture bits
determine the configurations as shown in the Configuration
Table and in Figures 1 through 8. A total of eight different con-
figurations are possible, with the two most common shown in
Figure 3 and Figure 5. The default or unprogrammed state is
registered/active/LOW/Pin 11 OE. The entire programmable
output cell is shown in the next section.
The architecture bit `C1' controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The regis-
ter is clocked by the signal from Pin 1. The register is initialized
on power up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
with architecture bit `C2'. The OE signal may be generated
within the array, or from the external OE (Pin 13). The Pin 13
allows direct control of the outputs, hence having faster en-
able/disable times.
Each output cell can be configured for output polarity. The out-
put can be either active HIGH or active LOW. This option is
controlled by architecture bit `C0'.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
Selection Guide
I
CC
(mA)
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
Generic
Part Number
Com/Ind
Mil
Com/Ind
Mil
Com/Ind
Mil
Com/Ind
Mil
20G10B15
70
15
12
10
20G10B20
70
100
20
20
12
15
12
15
20G10B25
100
25
18
15
20G1025
55
25
15
15
20G1030
80
30
20
20
20G1035
55
35
30
25
20G1040
80
40
35
25
PLDC20G10B/PLDC20G10
Document #: 38-03010 Rev. **
Page 3 of 13
Programmable Output Cell
OUTPUT
SELECT
MUX
C
1
C
0
Q
Q
D
CP
INPUT/
FEED
BACK
MUX
C
3
C
1
20G105
01
00
11
10
0
1
C
0
C
2
OUTPUT
ENABLE
MUX
C
2
PIN 13
OE PRODUCT TERM
Configuration Table
Figure
C
2
C
1
C
0
Configuration
1
0
0
0
Product Term OE/Registered/Active LOW
2
0
0
1
Product Term OE/Registered/Active HIGH
5
0
1
0
Product Term OE/Combinatorial/Active LOW
6
0
1
1
Product Term OE/Combinatorial/Active HIGH
3
1
0
0
Pin 13 OE/Registered/Active LOW
4
1
0
1
Pin 13 OE/Registered/Active HIGH
7
1
1
0
Pin 13 OE/Combinatorial/Active LOW
8
1
1
1
Pin 13 OE/Combinatorial/Active HIGH
PLDC20G10B/PLDC20G10
Document #: 38-03010 Rev. **
Page 4 of 13
Registered Output Configurations
Figure 1. Product Term OE/Active LOW
Figure 2. Product Term OE/Active HIGH
Figure 3. Pin 13 OE/Active LOW
Figure 4. Pin 13 OE/Active HIGH
Q
Q
D
20G106
CP
C
2
= 0
C
1
= 0
C
0
= 0
Q
Q
D
20G107
CP
C
2
= 0
C
1
= 0
C
0
= 1
Q
Q
D
20G108
CP
C
2
= 1
C
1
= 0
C
0
= 0
Q
Q
D
20G109
CP
C
2
= 1
C
1
= 0
C
0
= 1
Combinatorial Output Configurations
[2]
Figure 5. Product Term OE/Active LOW
Figure 6. Product Term OE/Active HIGH
Figure 7. Pin 13 OE/Active Low
Figure 8. Pin 13 OE/Active HIGH
Note:
2.
Bidirectional I/O configurations are possible only when the combinatorial output option is selected
20G1010
C
2
= 0
C
1
= 1
C
0
= 0
20G1011
C
2
= 0
C
1
= 1
C
0
= 1
20G1012
C
2
= 1
C
1
= 1
C
0
= 0
20G1013
C
2
= 1
C
1
= 1
C
0
= 1
PIN 13
PIN 13
PLDC20G10B/PLDC20G10
Document #: 38-03010 Rev. **
Page 5 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 3.0V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
DC Programming Voltage
PLDC20G10B and CG7C323BA ............................... 13.0V
PLDC20G10 and CG7C323A.................................... 14.0V
Latch-Up Current ..................................................... >200 mA
Static Discharge Voltage ............................................. >500V
(per MIL-STD-883, Method 8015)
]
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +75
C
5V
10%
Military
[3]
55
C to +125
C
5V
10%
Industrial
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range (Unless Otherwise Noted)
[4]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OH
= 3.2 mA
Com'l/Ind
2.4
V
I
OH
= 2 mA
Military
V
OL
Output LOW Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OL
= 24 mA
Com'l/Ind
0.5
V
I
OL
= 12 mA
Military
V
IH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
[5]
2.0
V
V
IL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
[5]
0.8
V
I
IX
Input Leakage Current
V
SS
V
IN
V
CC
10
+10
A
I
SC
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[6, 7]
90
mA
I
CC
Power Supply Current
0
V
IN
V
CC
V
CC
= Max.,
I
OUT
= 0 mA
Unprogrammed Device
Com'l/Ind15, 20
70
mA
Com'l/Ind25, 35
55
mA
Military20, 25
100
mA
Military30, 40
80
mA
I
OZ
Output Leakage Current
V
CC
= Max., V
SS
V
OUT
V
CC
100
100
A
Capacitance
[7]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz
10
pF
C
OUT
Output Capacitance
V
IN
= 2.0V, V
CC
= 5.0V
10
pF
Notes:
3.
T
A
is the "instant on" case temperature.
4.
See the last page of this specification for Group A subgroup testing information.
5.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6.
Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
7.
Tested initially and after any design or process changes that may affect these parameters.
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