Document Outline

CS4298: SoundFusion ®Audio/Modem Codec 97(AMC97)
- FEATURES
- DESCRIPTION
- ORDERING INFORMATION
- TABLE OF CONTENTS
- LIST OF FIGURES
- LIST OF TABLES
- Contacting Cirrus Logic Support
- 1. CHARACTERISTICS AND SPECIFICATIONS
  - AUDIO ANALOG CHARACTERISTICS
  - ABSOLUTE MAXIMUM RATINGS
  - RECOMMENDED OPERATING CONDITIONS
  - MODEM CHARACTERISTICS
    - Modem Analog Transmitter Characteristics
    - Modem Analog Receiver Characteristics
  - DIGITAL CHARACTERISTICS
    - DVdd = 3.3V
    - DVdd = 5.0 V
  - SERIAL PORT TIMING
  - RESET# Timing
    - Clocks
    - Data Setup and Hold
    - Misc. Timing Parameters
  - Figure 1. Power Up Timing
  - Figure 2. Clocks
  - Figure 3. Codec Ready from Startup or Fault Condition
  - Figure 4. Data Setup and Hold
  - Figure 5. PR4 Powerdown
  - Figure 6. Test Mode
- 2. GENERAL DESCRIPTION
  - 2.1 Overview
  - 2.2 Modes of Operation
    - 2.2.1 Mode 0
    - 2.2.2 Mode 1
    - 2.2.3 Mode 2
    - 2.2.4 Mode 3
- 3. DIGITAL SECTION
  - 3.1 AC-Link
    - Figure 7. AC-link Connections
  - 3.2 Control registers
- 4. ANALOG SECTION
  - 4.1 Audio Output Mixer
  - 4.2 Audio Input Mux
  - 4.3 Audio Input Mixer
  - 4.4 Audio Volume Control
  - Figure 8. Mixer Diagram
- 5. AC 97
  - 5.1 AC 97 Frame Definition
  - 5.2 AC-Link Serial Data Output Frame
    - Figure 9. AC-link Input and Output Framing
  - 5.3 AC-Link AudioOutput Frame
    - 5.3.1 Serial Data Output Slot Tags (Slot 0)
    - 5.3.2 Register Address (Slot 1)
    - 5.3.3 Register Write Data (Slot 2)
    - 5.3.4 Playback Data (Slots 3-11)
    - 5.3.5 GPIO Data (Slot12)
  - 5.4 AC-Link Audio Input Frame
    - 5.4.1 Serial Data Input Slot Tag Bits (Slot 0)
    - 5.4.2 Read-Back Address Port (Slot 1)
    - 5.4.3 Read-Back Data Port (Slot 2)
    - 5.4.4 PCM Capture Data (Slot 3-11)
    - 5.4.5 GPIO Pin Status (Slot 12)
  - 5.5 AC 97 Reset Modes
    - 5.5.1 Cold AC 97 Reset
    - 5.5.2 Warm AC 97 Reset
    - 5.5.3 AC 97 Register Reset
  - 5.6 AC-Link Protocol Violation - Loss of SYNC
- 6. REGISTER INTERFACE
  - Table 1. Mixer Registers
  - 6.1 Register Descriptions
    - 6.1.1 Reset (Index 00h)
    - 6.1.2 Master Volume (Index 02h)
    - 6.1.3 Alternate Volume (Index 04h)
      - Table 2. Alternate Line-Out and Master Mono Attenuation
    - 6.1.4 Microphone Volume (Index 0Eh)
      - Table 3. Analog Mixer Input Gain Values
    - 6.1.5 Stereo Analog Mixer Input Gain (Indexs 10h - 18h)
      - Table 4. Stereo Volume Register Index
    - 6.1.6 Input Mux Select (Index 1Ah)
      - Table 5. Input Mux Selection
    - 6.1.7 Record Gain (Index 1Ch)
    - 6.1.8 Record Gain Microphone (Index 1Eh)
    - 6.1.9 General Purpose (Index 20h)
    - 6.1.10 3D Control (Index 22h)
    - 6.1.11 Power Down Control/Status (Index 26h)
    - 6.1.12 Extended Audio ID (Index 28h)
    - 6.1.13 Extended Audio Status / Control (Index 2Ah)
    - 6.1.14 PCM Front DAC Rate (Index 2Ch)
    - 6.1.15 PCM Surround DAC Rate (Index 2Eh)
    - 6.1.16 PCM LFE DAC Rate (Index 30h)
    - 6.1.17 PCM LR ADC Rate (Index 32h)
    - 6.1.18 PCM MIC ADC Rate (Index 34h)
    - 6.1.19 Center LFE Volume (Index 36h)
      - Table 6. 6 Channel Volume Attenuation
    - 6.1.20 LR Surround Volume (Index 38h)
    - 6.1.21 Extended Modem ID (Index 3Ch)
    - 6.1.22 Extended Modem ID (Index 3Eh)
    - 6.1.23 Line 1 DAC/ADC Rate (Index 40h)
    - 6.1.24 Line 2 DAC/ADC Rate (Index 42h)
    - 6.1.25 Handset DAC/ADC Rate (Index 44h)
    - 6.1.26 Line 1 DAC/ADC Level (Index 46h)
    - 6.1.27 Line 2 DAC/ADC Level (Index 48h)
    - 6.1.28 Handset DAC/ADC Level (Index 4Ah)
    - 6.1.29 GPIO Pin Configuration (Index 4Ch)
    - 6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh)
      - Table 7. GPIO Input/Output Configuration
    - 6.1.31 GPIO Pin Sticky (Index 50h)
    - 6.1.32 GPIO Pin Wakeup Mask (Index 4Ch)
    - 6.1.33 GPIO Pin Status (Index 54h)
    - 6.1.34 Misc. Modem AFE Status (Index 56h)
      - Table 8. Misc. Modem Configuration
    - 6.1.35 AC Mode Control (Index 5Eh)
      - Table 9. Slot Assignments
    - 6.1.36 S/PDIF Control (Index 68h)
    - 6.1.37 Vendor ID1 (Index 7Ch)
    - 6.1.38 Vendor ID2 (Index 7Eh)
      - Table 10. Reg. 7Eh Defined Part IDs
- 7. ANALOG HARDWARE DESCRIPTION
  - 7.1 Line-Level Inputs
    - Figure 10. Line Inputs
    - Figure 11. Differential CDROM In
  - 7.2 Microphone Level Inputs
    - Figure 12. PC 99 Microphone Pre-amplifier
  - 7.3 Line Level Outputs
    - Figure 13. Headphones Driver
  - 7.4 Consumer IEC-958 Digital Interface (S/PDIF)
    - Figure 14. IEC-958 Interface Examples
  - 7.5 Miscellaneous Analog Signals
  - 7.6 Power Supplies
    - Figure 15. Voltage Regulator
  - 7.7 Hybrid Interface
    - Figure 16. Hybrid Circuit Secondary
- 8. PIN DESCRIPTIONS
  - 8.1 g2
  - 8.2 Analog I/O Pins
  - 8.3 Filter and Reference Pins
  - 8.4 Modem/Telephony
  - 8.5 Power Supplies
- 9. PARAMETER AND TERM DEFINITIONS
- 10. REFERENCES
- 11.PACKAGE DIMENSIONS
  - 64L TQFP PACKAGE DRAWING

Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 1999

P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com

FEATURES

AC `97 2.0 compatible

20-bit stereo output and 18-bit stereo input codec
with fixed 48 kHz sampling rate

20-bit output and 18-bit input dual modem AFE
with fixed 48 kHz sampling rate

Dedicated ADC for handset or speakerphone

Four analog line-level stereo inputs for connec-
tion from LINE IN, CD, VIDEO, and AUX

High quality pseudo-differential CD input

Dual stereo line level output with independent 6-
bit volume control

10 General Purpose I/O pins for Modem DAA
controls

IEC-958 Digital Output (S/PDIF)

Meets or exceeds Microsoft's

PC 98 and PC 99

audio performance requirements

CrystalClearTM 3D Stereo Enhancement

DESCRIPTION

The CS4298 is an AC `97 compatible Audio/Mo-
dem Codec designed for PC multimedia systems.
Using the industry leading CrystalClearTM delta-
sigma and mixed signal technology, the CS4298 is
ideal for PC 98-compliant desktop, notebook, and
entertainment PCs, where high-quality audio and
modem features are required.The CS4298 offers
four channels of D/A and A/D conversion along
with analog mixing and 3D processing. For multi-
channel audio systems, the CS4298 can provide
four audio channels. For combined audio/modem
systems, the CS4298 can provide a modem AFE,
voice codec, and stereo audio codec..

ORDERING INFORMATION

CS4298

-KQ

64-pin TQFP 10x10x1.4mm

CS4298

-JQ

64-pin TQFP 10x10x1.4mm

VOL

MUTE

VOL

+20dB

DAC

STEREO TO

MONO MIXER

VOL

OUTPUT
BUFFER

MASTER VOLUME

ALTERNATE VOLUME

MAIN D/A

CONVERTERS

PCM_OUT

PCM OUT

PATH

STEREO

INPUT
MIXER

STEREO
OUTPUT

MIXER

MIC1

AUX

LINE

Mode Control

SYNC

SDATA_OUT

MUTE

VOL

ADC

INPUT

MUX

VOL

MUTE

ADC

MAIN ADC GAIN

ADC

DAC

RESET#

ALT_LINE_OUT

LINE_OUT

GPIO

BIT_CLK

SDATA_IN

AC-Link Interface

MIC2

MIC SELECT

VIDEO

MUTE

VOL

MUTE

VOL

ADC

DAC

VOL

Vref

(loopback) HTX-

(loopback) HTX+

Vref

(loopback) MTX-

(loopback) MTX+

MRX+

MRX-

HRX+

HRX-

HRX+

MRX+

MRX-

Class AB

Dif out

- +

+ -

Class AB

Dif out

- +

+ -

MTX+

MTX-

HTX+

HTX-

SoundFusion

Audio/Modem Codec '97(AMC'97)

CS4298

AUG `99

DS315PP2

CS4298

DS315PP2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

AUDIO ANALOG CHARACTERISTICS.................................................................................... 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6
RECOMMENDED OPERATING CONDITIONS ....................................................................... 6
MIXER CHARACTERISTICS.................................................................................................... 6
MODEM CHARACTERISTICS ................................................................................................. 7
SERIAL PORT TIMING............................................................................................................. 9

2. GENERAL DESCRIPTION ..................................................................................................... 12

2.1 Overview ........................................................................................................................... 12
2.2 Modes of Operation .......................................................................................................... 12

2.2.1 Mode 0 .................................................................................................................... 12
2.2.2 Mode 1 .................................................................................................................... 12
2.2.3 Mode 2 .................................................................................................................... 12
2.2.4 Mode 3 .................................................................................................................... 12

3. DIGITAL SECTION ................................................................................................................. 13

3.1 AC-Link ............................................................................................................................. 13
3.2 Control registers................................................................................................................ 13

4. ANALOG SECTION ................................................................................................................ 14

4.1 Audio Output Mixer ........................................................................................................... 14
4.2 Audio Input Mux ................................................................................................................ 14
4.3 Audio Input Mixer .............................................................................................................. 14
4.4 Audio Volume Control ....................................................................................................... 14

5. AC `97 ..................................................................................................................................... 16

5.1 AC `97 Frame Definition.................................................................................................... 16
5.2 AC-Link Serial Data Output Frame ................................................................................... 16
5.3 AC-Link AudioOutput Frame............................................................................................. 17
5.3.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 17
5.3.2 Register Address (Slot 1)............................................................................................... 17
5.3.3 Register Write Data (Slot 2) ........................................................................................... 18
5.3.4 Playback Data (Slots 3-11) ............................................................................................ 18
5.3.5 GPIO Data (Slot12)........................................................................................................ 18
5.4 AC-Link Audio Input Frame............................................................................................... 18
5.4.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................................... 18
5.4.2 Read-Back Address Port (Slot 1)................................................................................... 19
5.4.3 Read-Back Data Port (Slot 2) ........................................................................................ 19
5.4.4 PCM Capture Data (Slot 3-11)....................................................................................... 19
5.4.5 GPIO Pin Status (Slot 12) .............................................................................................. 19

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-
cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic webbiest or disk may be printed for use by the user. However, no part of the
printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-
graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.

CS4298

DS315PP2

5.5 AC '97 Reset Modes......................................................................................................... 20

5.5.1 Cold AC `97 Reset................................................................................................... 20
5.5.2 Warm AC '97 Reset ................................................................................................ 20
5.5.3 AC '97 Register Reset............................................................................................. 20

5.6 AC-Link Protocol Violation - Loss of SYNC ...................................................................... 20

6. REGISTER INTERFACE ........................................................................................................ 21

6.1 Register Descriptions ....................................................................................................... 23
6.1.1 Reset (Index 00h) ......................................................................................................... 23
6.1.2 Master Volume (Index 02h) .......................................................................................... 23
6.1.3 Alternate Volume (Index 04h) ....................................................................................... 24
6.1.4 Microphone Volume (Index 0Eh) ................................................................................... 24
6.1.5 Stereo Analog Mixer Input Gain (Index's 10h - 18h) ..................................................... 25
6.1.6 Input Mux Select (Index 1Ah) ........................................................................................ 25
6.1.7 Record Gain (Index 1Ch)............................................................................................... 26
6.1.8 Record Gain Microphone (Index 1Eh) ........................................................................... 26
6.1.9 General Purpose (Index 20h) ........................................................................................ 26
6.1.10 3D Control (Index 22h) ................................................................................................ 26
6.1.11 Power Down Control/Status (Index 26h) ..................................................................... 27
6.1.12 Extended Audio ID (Index 28h) .................................................................................. 28
6.1.13 Extended Audio Status / Control (Index 2Ah) ............................................................. 28
6.1.14 PCM Front DAC Rate (Index 2Ch) ........................................................................... 29
6.1.15 PCM Surround DAC Rate (Index 2Eh) ..................................................................... 29
6.1.16 PCM LFE DAC Rate (Index 30h) .............................................................................. 29
6.1.17 PCM LR ADC Rate (Index 32h)................................................................................... 29
6.1.18 PCM MIC ADC Rate (Index 34h)................................................................................. 29
6.1.19 Center LFE Volume (Index 36h) .................................................................................. 30
6.1.20 LR Surround Volume (Index 38h) ................................................................................ 30
6.1.21 Extended Modem ID (Index 3Ch) ............................................................................... 30
6.1.22 Extended Modem ID (Index 3Eh) ............................................................................... 31
6.1.23 Line 1 DAC/ADC Rate (Index 40h) .............................................................................. 31
6.1.24 Line 2 DAC/ADC Rate (Index 42h) .............................................................................. 31
6.1.25 Handset DAC/ADC Rate (Index 44h) .......................................................................... 32
6.1.26 Line 1 DAC/ADC Level (Index 46h) ............................................................................. 32
6.1.27 Line 2 DAC/ADC Level (Index 48h) ............................................................................. 32
6.1.28 Handset DAC/ADC Level (Index 4Ah) ......................................................................... 32
6.1.29 GPIO Pin Configuration (Index 4Ch) ........................................................................... 33
6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh) ..................................................... 33
6.1.31 GPIO Pin Sticky (Index 50h)........................................................................................ 33
6.1.32 GPIO Pin Wakeup Mask (Index 4Ch) ......................................................................... 34
6.1.33 GPIO Pin Status (Index 54h) ....................................................................................... 34
6.1.34 Misc. Modem AFE Status (Index 56h) ........................................................................ 34
6.1.35 AC Mode Control (Index 5Eh) ..................................................................................... 35
6.1.36 S/PDIF Control (Index 68h) ......................................................................................... 35
6.1.37 Vendor ID1 (Index 7Ch)............................................................................................... 36
6.1.38 Vendor ID2 (Index 7Eh) ............................................................................................... 36

7. ANALOG HARDWARE DESCRIPTION ................................................................................. 37

7.1 Line-Level Inputs .............................................................................................................. 37
7.2 Microphone Level Inputs .................................................................................................. 38
7.3 Line Level Outputs............................................................................................................ 38
7.4 Consumer IEC-958 Digital Interface (S/PDIF) .................................................................. 39
7.5 Miscellaneous Analog Signals .......................................................................................... 39
7.6 Power Supplies................................................................................................................. 40
7.7 Hybrid Interface ................................................................................................................ 41

CS4298

DS315PP2

8. PIN DESCRIPTIONS .............................................................................................................. 42

8.1 g2 ..................................................................................................................................... 43
8.2 Analog I/O Pins ................................................................................................................ 45
8.3 Filter and Reference Pins ................................................................................................ 46
8.4 Modem/Telephony ........................................................................................................... 47
8.5 Power Supplies ................................................................................................................ 48

9. PARAMETER AND TERM DEFINITIONS .............................................................................. 49
10. REFERENCES ...................................................................................................................... 50
11. PACKAGE DIMENSIONS ..................................................................................................... 51

LIST OF FIGURES

Figure 1. Power Up Timing............................................................................................................ 10
Figure 2. Clocks ............................................................................................................................ 10
Figure 3. Codec Ready from Startup or Fault Condition ............................................................... 10
Figure 4. Data Setup and Hold ...................................................................................................... 11
Figure 5. PR4 Powerdown ............................................................................................................ 11
Figure 6. Test Mode ...................................................................................................................... 11
Figure 7. AC-link Connections....................................................................................................... 13
Figure 8. Mixer Diagram ................................................................................................................ 15
Figure 9. AC-link Input and Output Framing.................................................................................. 16
Figure 10. Line Inputs.................................................................................................................... 37
Figure 11. Differential CDROM In ................................................................................................. 37
Figure 12. PC `99 Microphone Pre-amplifier ................................................................................. 38
Figure 13. Headphones Driver ...................................................................................................... 39
Figure 14. IEC-958 Interface Examples ........................................................................................ 40
Figure 15. Voltage Regulator ........................................................................................................ 40
Figure 16. Hybrid Circuit Secondary ............................................................................................ 41

LIST OF TABLES

Table 1. Mixer Registers ............................................................................................................... 21
Table 2. Alternate Line-Out and Master Mono Attenuation ........................................................... 24
Table 3. Analog Mixer Input Gain Values...................................................................................... 24
Table 4. Stereo Volume Register Index ........................................................................................ 25
Table 5. Input Mux Selection ......................................................................................................... 25
Table 6. 6 Channel Volume Attenuation........................................................................................ 30
Table 7. GPIO Input/Output Configuration .................................................................................... 33
Table 8. Misc. Modem Configuration............................................................................................. 34
Table 9. Slot Assignments............................................................................................................ 35
Table 10. Reg. 7Eh Defined Part ID's ........................................................................................... 36

CS4298

DS315PP2

1. CHARACTERISTICS AND SPECIFICATIONS

AUDIO ANALOG CHARACTERISTICS

(Standard test conditions unless otherwise noted:

ambient

= 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz;

=10 k

680 pF load C

= 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding

for ADC, 20-bit linear coding for DAC; Mixer registers set for unity gain.

Notes: 1. Z

refers to the analog output pin loading and C

refers to the digital output pin loading.

2. Parameter definitions are given in the

Parameter and Term Definitions

section.

3. Path refers to the signal path used to generate this data. These paths are defined in the

Parameter and

Term Definition

section.

4. Typical measured with Z

= 47 k

/680 pF load.

5. This specification is guaranteed by silicon characterization, it is not production tested.

Parameter (Note 2)

Symbol

Path

(Note 3)

CS4298-KQ

CS4298-JQ

Unit

Min Typ

Max

Min Typ

Max

Full Scale Analog Input Voltage
Line Inputs
Mic Inputs

(20 dB=0)

Mic Inputs

(20 dB=1)

A-D
A-D
A-D

0.91
0.91

0.091

1.00
1.00
0.10

-
-
-

0.91
0.91

0.091

1.00
1.00
0.10

-
-
-

RMS

Full Scale Output Voltage (Note 4)
Line and Alternate Line Outputs

D-A

0.91

1.0

1.13

0.91

1.0

1.13

RMS

Frequency Response
Analog

Ac = ± 0.5 dB

DAC

Ac = ± 0.5 dB

ADC

Ac = ± 0.5 dB

A-A
D-A
A-D

20
20
20

-
-
-

20,000
20,000
20,000

20
20
20

-
-
-

20,000
20,000
20,000

Hz
Hz
Hz

Dynamic Range
Stereo Analog inputs to LINE_OUT
Mono Analog inputs to LINE_OUT
DAC Dynamic Range
ADC Dynamic Range

A-A
A-A
D-A
A-D

90
85
85
85

95
90
90
90

-
-
-
-

90
85
87
85

-
-
-
-

dB FS A
dB FS A
dB FS A
dB FS A

DAC SNR (-20 dB FS input w/
CCIR-RMS filter on output)

SNR

D-A

Total Harmonic Distortion + Noise
(-3 dB FS input signal):
Line/Alternate Line Output
DAC
ADC

(all inputs except phone/mic)

ADC

(phone/mic)

THD+N

A-A
D-A
A-D
A-D

-
-
-
-

-94
-86
-87
-87

-80
-80
-80
-74

-
-
-
-

-74
-74
-74
-74

dB FS A
dB FS A
dB FS A
dB FS A

Power Supply Rejection Ratio
(1 kHz, 0.5 V

RMS

w/ 5 V DC offset)(Note 5)

Interchannel Isolation

Spurious Tone

(Note 5)

-100

dB FS

Input Impedance

(Note 5)

External Load Impedance

Output Impedance

(Note 5)

730

Input Capacitance

(Note 5)

Vrefout

2.0

2.3

2.4

2.0

2.3

2.4

CS4298

DS315PP2

MODEM CHARACTERISTICS

(Analog Transmitter Specifications: T

ambient

= 0° to 70° C, AVdd = 5.0

V; Sample Frequency, Fs = 48 kHz; Audio specifications for 20Hz - 5 kHz, actual digital filter may cutoff at 20 kHz,
600

differential load where applicable)

Notes: 6. This is the FCC specification for Out-of-Band energy at the telephone jack interface. 9 kHz refers to the

bin size of an FFT performed over the entire range. The amount of noise plus tone power in each 8kHz
bin must be less than -55dBV.

Parameter

Min

Typical

Max

Units

Modem Analog Transmitter Characteristics

Resolution

bits

Dynamic Range (Note 5)

100

dB FS

Passband

5000

Passband Ripple

±0.125

dB1K

Total Harmonic Distortion

dB FS

Full Scale Peak to Peak Output Voltage (TX+ to TX-)

TBD

5.6

TBD

Volts

AC Output Impedance (TX+, TX-) (Note 5)

0.1

Load Impedance (per pin) (Note 5)

250

Power Supply Rejection (1kHz) (Note 5)

Output Current (per pin)

7.4

Offset (relative) (Note 5)

Out of Band specifications (T

ambient

= 25° C, AVdd = 5 V;

Sample Frequency, Fs = 48 kHz; measurement bandwidth
20 kHz - 1MHz, R

=600

, C

=33nF) (Note

-40

Total Out of Band energy (20 kHz - 1 MHz)

(Note 5)

-30

dBV

Highest 9kHz band (noise + tone) power (90 kHz - 2 MHz)

(Note 5, 6)

-55

dBV

Modem Analog Receiver Characteristics

Resolution

bits

Dynamic Range

Gain = 0

dB FS

Passband

5000

Passband Ripple

±0.125

dB1K

Total Harmonic Distortion Gain = 0 85

Total Absolute Gain Accuracy

-5

Full Scale Peak to Peak Input Voltage (RX+ to RX-,
differential)

Gain = 0

2.8

Volts

Input Impedance (per pin)

(Note 5)

Offset (relative)

(Note 5)

Power Supply Rejection

(Note 5)

CS4298

DS315PP2

SERIAL PORT TIMING

Notes: 7. BIT_CLK measured with 47

series termination and C

= 50

pF.

Parameter

Symbol

Min

Typ

Max

Unit

RESET# Timing

Vdd stable to RESET# inactive

vdd2rst#

RESET# active low pulse width

rst_low

1.0

RESET# inactive to BIT_CLK start-up delay

rst2clk

120

1st SYNC active to CODEC READY set

sync2crd

62.4

Clocks

BIT_CLK frequency

clk

12.288

MHz

BIT_CLK period

clk_period

81.4

BIT_CLK output jitter (depends on XTAL_IN source)

750

BIT_CLK high pulse width

clk_high

40.7

BIT_CLK low pulse width

clk_low

40.7

SYNC frequency

sync

kHz

SYNC period

sync_period

20.8

SYNC high pulse width

sync_high

1.3

SYNC low pulse width

sync_low

19.5

Data Setup and Hold

Output Propagation delay from rising edge of BIT_CLK

Input setup time from falling edge of BIT_CLK

isetup

Input hold time from falling edge of BIT_CLK

ihold

Input Signal rise time

irise

Input Signal fall time

ifall

Output Signal rise time

(Note 5, 7)

orise

Output Signal fall time

(Note 5, 7)

ofall

Misc. Timing Parameters

End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)

s2_pdown

.34

1.0

SYNC pulse width (PR4) Warm Reset

sync_pr4

1.1

SYNC inactive (PR4) to BIT_CLK start-up delay

sync2clk

162.8

350

Setup to trailing edge of RESET# (test mode)

(Note 5)

setup2rst

Rising edge of RESET# to Hi-Z delay

(Note 5)

off

CS4298

DS315PP2

2. GENERAL DESCRIPTION

2.1

Overview

The CS4298 is a Mixed-Signal Audio/Modem Codec (AMC) based on the AC `97 1.0 Specification,
and the AC `97 2.0 Extensions. It is designed to be paired with a digital controller, typically located
on the PCI bus. The AMC Controller is responsible for all communications between the CS4298 and
the rest of the system. The CS4298 functions as an analog mixer, a stereo audio ADC, a stereo audio
DAC, a dual modem AFE, and a control and digital stream interface to the AMC Controller. The
CS4298 contains three distinct functional sections: Digital, Analog Audio, and Analog Modem.

The Digital Section includes the AC-Link registers, power management support, SYNC detection
circuitry, and AC-Link serial port interface logic. The Analog Audio section includes the analog in-
put multiplexor (mux), stereo output mixer, stereo ADCs, stereo DACs, and analog volume controls.
The Analog Modem section includes dual differential ADCs, dual differential DACs, analog loop-
back logic, GPIO control and status, and power down and wake-up logic.

2.2

Modes of Operation

The CS4298 has four basic modes of operation. Each mode allows varying functionality to meet a
wide variety of software and hardware configurations. On power up or system reset, the device re-
verts to the basic configuration Mode 0. The audio ADC's and DAC's functionality remains fixed
for each mode, but the modem ADC's and DAC's functionality changes per each configuration.
From a system perspective, the device can provide standard audio with modem, two line interface,
speakerphone, and four channel enhanced audio.

2.2.1

Mode 0

This is the default operating mode for the CS4298. It supports the legacy AC `97 audio modes of op-
eration including audio mixer, ADC's, and DAC's. The modem configuration supports a phone line
for modem ADC/DAC1 and a handset interface for modem ADC/DAC2.

2.2.2

Mode 1

This is the two phone line mode of operation. It is similar to mode 0 but the modem ADC/DAC2 is
interfaced to a second phone line in place of the handset.

2.2.3

Mode 2

This mode facilitates a full duplex speakerphone mode of operation. The ADC of modem
ADC/DAC2 is connected directly to the audio microphone in place of the handset or line 2 input.
This dedicated microphone capture path allows the host controller to implement echo cancellation
for hands free telephone operation. The modem DAC2 is not used in this mode.

2.2.4

Mode 3

Mode 3 is the four channel expansion mode. The modem ADC/DAC pairs are utilized for enhanced
audio functionality. The modem DAC's are routed to the alternate line audio outputs providing 2 ad-
ditional audio channels. The modem ADC inputs may be connected to the output of the analog stereo
input mixer for enhanced audio effect processing or enhanced digital docking in a note book appli-
cation.

CS4298

DS315PP2

3. DIGITAL SECTION

3.1

AC-Link

All communication with the Codec is estab-
lished with a 5-wire digital interface to the Con-
troller chip as shown in Figure 7. All clocking
for the serial communication is synchronous to
the BIT_CLK signal. BIT_CLK is generated by
the primary Codec and is used to slave the Con-
troller and any secondary Codecs, if applicable.
An AC-link audio frame is a sequence of 256 se-
rial bits organized into 13 groups referred to as
`slots'. One frame consists of one 16-bit slot and
twelve 20-bit slots. During each audio frame,
data is passed bi-directionally between the Co-
dec and the Controller. The input frame is driv-
en from the Codec on the SDATA_IN line. The
output frame is driven from the Controller SDATA_OUT line. Both input and output frames contain
the same number of bits and are organized with the same `slot' configuration. The input and output
frame have differing functions for each slot. The Controller synchronizes the beginning of a frame
with the SYNC signal. In Figure 9 the position of each bit location within the frame is noted. The
first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is
F255. When SYNC goes active (high) and is sampled active by the CS4298 (on the falling edge of
BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT
pin at this clock edge is the final bit of the previous frame's serial data. On the next rising edge of
BIT_CLK, the first bit of Slot 0 is driven by the Controller on the SDATA_OUT pin. The CS4298
latches in this data, as the first bit of the frame, on the next falling edge of the BIT_CLK clock signal.
The Controller is also responsible for issuing reset via the RESET# signal. After being reset, the Co-
dec is responsible for flagging the Controller that it is ready for operation after synchronizing its in-
ternal functions. The AC-link signals may be referenced to either 5 Volts or 3.3 Volts. The CS4298
must use the same digital supply voltage as the Controller chip.

3.2

Control registers

All read accesses to the Codec are generated by requesting a register address (index number) in slot
1 of a SDATA_OUT frame. The following SDATA_IN frame will contain the register content in its
slot 2. The write operation is identical with the index in slot 1 and the write data in slot 2. The AC `97
Frame Definition section details the function of each input and output frame. Individual register de-
scriptions are found in the Register Interface section.

AC-97 Register Interface

The CS4298 implements the AC '97 Registers in accordance with the AC '97 2.0 Specification. See
the Register Interface section for details on the CS4298's register set.

CODEC

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC'97

Controller

Figure 7. AC-link Connections

CS4298

DS315PP2

4. ANALOG SECTION

Please refer to Figure 8, Mixer diagram, for a high-level graphical representation of the CS4298 an-
alog mixer structure.

4.1

Audio Output Mixer

There are two output mixers on the CS4298. The stereo output mixer sums together the analog out-
puts from the Input Mixer, 3D enhancement, and the PCM DAC output. The stereo output mix is sent
to the LINE_OUT and ALT_LINE_OUT output pins of the CS4298. When the device is set to Mode
3 or Mode 0-2 and the EAM in AC Mode Control (Index 5Eh) is set, the modem DAC outputs are
routed to ALT_LINE_OUT.

4.2

Audio Input Mux

The input multiplexor controls which analog input is sent to the ADCs. The output of the input mux
is converted to stereo 18-bit digital PCM data and sent to the AMC Controller chip in Slots 3 and 4
of the AC-Link SDATA_IN signal.

4.3

Audio Input Mixer

The input mixer is an analog mix of the analog input signals such as MIC, LINE_IN, etc., and the
PCM Audio DAC output. The output of the mixer is routed to the ADC Input Mux, Audio Output
Mixer, and may be routed to the Modem ADC input.

4.4

Audio Volume Control

The volume control registers of the AC '97 Register interface control analog input level to the input
mixer, the master volume level, and the alternate volume level. All analog volume controls imple-
ment volume steps at nominally 1.5 dB per step. The analog inputs allow a mixing range of +12 dB
of signal gain to -34.5 dB of signal attenuation. The analog output volume controls allows from 0 dB
to -94.5 dB of attenuation.

CS4298

DS315PP2

5. AC `97

5.1

AC `97 Frame Definition

The AC Link is a bi-directional serial port with thirteen time-division multiplexed slots in each di-
rection. The first slot is 16 bits long and termed the tag slot. Bits in the tag slot determine if the Codec
is ready and indicate which, if any, other slots contain valid data. Slots 1 through 11 are 20-bits long
and can contain audio data. Slot 12 contains data to be written and read from GPIO. The serial data
line is defined from the Controller's perspective, NOT from the Audio Codec's perspective.

5.2

AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin TO the CS4298 FROM the
Controller. Figure 9 illustrates the serial port timing.

20.8

(48 kHz)

Tag Phase

Data Phase

12.288 MHz

81.4 nS

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

F16

F15

F14

F13

F12

F35

F56

F76

F255

Valid

Frame

Slot 1

Valid

SCRA1 SCRA0

R/W

WD15

F36

F57

LP19

LP18

RP19

LC17

LC16

RC17

RD15

Bit Frame Position:

F16

F15

F14

F13

F12

F35

F56

F76

F255

F36

F57

F255

F97

Slot 0

Slot 1

Slot 2

Slot 3

Slot 4

Slots 5-12

Slot 2

Valid

Slot 1

Valid

Slot 2

Valid

Codec
Ready

Bit Frame Position:

Figure 9. AC-link Input and Output Framing

CS4298

DS315PP2

5.3

AC-Link AudioOutput Frame

5.3.1

Serial Data Output Slot Tags (Slot 0)

Valid FrameDetermines if any of the following slots contain either valid playback data for the Codec's DACs, data

for read/write operation, or GPIO data. When set, at least one of the other AC-link slots contain valid
data. If this bit is clear, the remainder of the frame is ignored.

Slot [1:2] ValidIndicates valid slot data when accessing the register set of the primary Codec (SCRA[1:0] = 00). For

a read operation, Slot 1 Valid is set when

(Slot 1) contains valid data. For a write op-

eration, Slot 1 Valid and Slot 2 Valid are set indicating

(Slot 1) and

(Slot 2) contain valid data. The register address and write data must be valid within the same frame.
SCRA[1:0] must be cleared when accessing the primary Codec. The physical address of a Codec is
determined by the ID[1:0]# input pins which are reflected in the

Extended Audio ID

(Index 28h) register

and the

Extended Modem ID

(Index 3Ch) register.

Slot [3:11] Valid

If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored.
The definition of each slot is determined by the basic operating mode selected for the CS4298. For more
information, see the

AC Mode Control

(Index 5Eh) register.

Slot 12 ValidIf Slot 12 Valid is set, Slot 12 contains valid write data for the GPIO pins.

SCRA[1:0] Secondary Codec Register Access. Unlike the primary Codec, SCRA[1:0] indicate valid slot data when

accessing the register set of a secondary Codec. The value set in SCRA[1:0] (01,10,11) determines
which of the three possible secondary Codecs is accessed. For a read operation, the SCRA[1:0] bits
are set when

(Slot 1) contains valid data. For a write operation, SCRA[1:0] bits are

set when

(Slot 1) and

(Slot 2) contain valid data. The write oper-

ation requires the register address and the write data to be valid within the same frame. SCRA[1:0] must
be cleared when accessing the primary Codec. They must also be cleared during the idle period where
no register read or write is pending. The physical address of a Codec is determined by the ID[1:0]# input
pins which are reflected in the

Extended Audio ID

(Index 28h) register and the

Extended Modem ID

(In-

dex 3Ch) register. The SCRA[1:0] bits are listed as the ID[1:0] bits in Slot 0 in the AC `97 specification.

5.3.2

Register Address (Slot 1)

R/W #

Read/Write#. Determines if a read (R/W# = 1) or write (R/W# = 0) operation is requested. For a read
operation, the following Input Frame will return the register index in the

Read-Back Address Port

(Slot

1) and the contents of the register in the

Read-Back Data Port

(Slot 2). A write operation does not return

any valid data in the following frame. If the R/W# bit = 0, data must be valid in both the

(Slot 1) and the

(Slot 2)

during a frame when Slot [1:2] Valid or SCRA[1:0] are set.

RI[6:0]

Register index/address. Registers can only be accessed on word boundaries; RI0 must be set to 0.
RI[6:0] must contain valid data during a frame when the Slot 1 Valid or SCRA[1:0] are set.

Bit 15

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

SCRA

Bit 19

R/W# RI6

RI5

RI4

RI3

RI2

RI1

RI0

CS4298

DS315PP2

5.3.3

Register Write Data (Slot 2)

WD[15:0]

Codec register data for write operations. For read operations, this data is ignored. If R/W# = 0, data must
be valid in both the

(Slot 1) and the

(Slot 2)

during a frame when

the Slot [1:2] Valid = 11 or either SCRA[1:0] bit is set. Splitting the register address and the write data
across multiple frames is not permitted.

5.3.4

Playback Data (Slots 3-11)

PD[19:0]

20-bit PCM playback (2's compliment) data for the left and right DACs, S/PDIF transmitter, or GPIO
pins. Any PCM data from the Controller less than 20 bits should be left justified in the slot and zero-
padded. Table 9 on page 35 lists the definition of each respective slot. The mapping of a given slot is
determined by the MD[1:0] bits found in the

AC Mode Control

(Index 5Eh) register

5.3.5

GPIO Data (Slot12)

GP[9:0]

GPIO Output Date. Output data is transferred to the GPIO pins every frame in Slot 12.

5.4

AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4298 to the AC '97
Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates
the serial port timing.

5.4.1

Serial Data Input Slot Tag Bits (Slot 0)

Codec ReadyIndicates the readiness of the CS4298's AC-link and Control and Status registers. Immediately after a

Cold Reset this bit will be clear. Once the CS4298's clocks and voltages are stable, this bit will be set.
Until the Codec Ready bit is set, no AC-link transactions should be attempted by the Controller. The
Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function.
Those must be checked in the

Power Down Control/Status

(Index 26h),

Ext'd Audio Ctrl/Stat (Index

2Ah)

, and

Ext'd Modem Ctrl/Stat (Index 3Eh)

registers by the Controller before any access is made to

the mixer registers. Any accesses to the Codec while Codec Ready is clear is ignored.

Slot 1 Valid Tag

Indicates Slot 1 contains a valid read back address.

Slot 2 Valid Tag

Indicates Slot 2 contains valid register read data.

Slot [3:11] Valid Tag

Indicates Slot [3:11] contains valid capture data from the Codec's ADC.

Slot 12 Valid Tag

Indicates Slot 12 contains valid read data of the

GPIO Pin Status Register

(Index 54h).

Bit 19

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

Bit 19

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Bit 19

GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

Bit 15

Codec
Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

CS4298

DS315PP2

5.4.2

Read-Back Address Port (Slot 1)

RI[6:0]

Register index. The Read-Back Address Port echoes the AC '97 Register address when a register read
has been requested in the previous frame. The Codec will only echo the register index for a read access.
Write accesses will not return valid data in Slot 1.

5.4.3

Read-Back Data Port (Slot 2)

RD[15:0]

16-bit register value. The Read-Back Data Port contains the register data requested by the Controller
from the previous read request. All read requests will return the read address in the

Read-Back Address

Port

(Slot 1) and the register data in the

Read-Back Data Port

(Slot 2) on the following serial data frame.

5.4.4

PCM Capture Data (Slot 3-11)

CD[17:0]

18-bit PCM (2's compliment) data. The mapping of a given slot to an ADC is determined by the state of
the MD[1:0] bits found in the

AC Mode Control

(Index 5Eh) register.

5.4.5

GPIO Pin Status (Slot 12)

GI[9:0]

Status of the GPIO[9:0] pin.

IRQ

Set when the GPIO generates a wake up or interrupt cycle. See

GPIO Pin Wake Up Mask (Index 52h)

The capture data in Slot [3:12] will only be valid when the respective slot valid bit is set in Slot 0.

Bit 19

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Bit 19

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Bit 19

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

Bit 19

GI9

GI8

GI7

GI6

GI5

GI4

GI3

GI2

GI1

GI0

IRQ

CS4298

DS315PP2

5.5

AC '97 Reset Modes

Three methods of resetting the CS4298, as defined in the AC '97 Specification, are supported: Cold
AC '97 Reset, Warm AC '97 Reset, and AC '97 Register Reset. A Cold AC '97 Reset is required to
restart the AC-link when bit PR5 is set in the Power Down Control/Status (Index 26h) register.

5.5.1

Cold AC `97 Reset

A Cold Reset is performed by asserting RESET# in accordance with the minimum timing specifica-
tions in the Serial Port Timing section. Once de-asserted, all of the Codec's registers will be reset to
their default power-on states and the BIT_CLK clock and SDATA_IN signals will be reactivated.
The timing of power-up/reset events is discussed in detail in the Power Management section.

5.5.2

Warm AC '97 Reset

The CS4298 may also be reactivated when the AC-link is powered down (refer to the PR4 bit de-
scription in the Power Management section) by a Warm Reset. A Warm Reset allows the AC-link to
be reactivated without losing information in the Codec's registers. Warm Reset is initiated when the
SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_CLK clock
signal. The BIT_CLK clock will not restart until at least 2 normal BIT_CLK clock periods
(± 162.8 ns) after the SYNC signal is de-asserted.

5.5.3

AC '97 Register Reset

The third reset mode provides a register reset to the CS4298. This is available only when the
CS4298's AC-link is active and the Codec Ready bit is set. The audio and modem subsections may
be reset independently. Any write to Reset (Index 00h) register will reset the audio subsection while
any write to Ext'd Modem Ctrl/Stat (Index 3Eh) register will reset the modem subsection. See the
respective register descriptions for additional information.

5.6

AC-Link Protocol Violation - Loss of SYNC

The CS4298 is designed to handle SYNC protocol violations. The following are situations where the
SYNC protocol has been violated:

· The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an

audio frame.

· The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous

SYNC assertion.

· The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous

SYNC assertion.

Upon loss of synchronization with the Controller, the Codec will mute all analog outputs and clear
the Codec Ready bit in the serial data input frame until two valid frames are detected. During this
detection period, the Codec will ignore all register reads and writes and will discontinue the trans-
mission of PCM capture data.

CS4298

DS315PP2

6. REGISTER INTERFACE

Certain register locations change definition based on the basic operating mode (Mode 0-3) selected
by the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register. The reset default is Mode 0.

Reg

Num

Name

D15

D14

D13

D12

D11

D10

Default

00h

Reset Mode 0

SE4 SE3 SE2 SE1

ID8

ID7

ID4

1990h

00h

Reset Mode 1

SE4 SE3 SE2 SE1

ID8

ID7

ID4

1990h

00h

Reset Mode 2

SE4 SE3 SE2 SE1

ID8

ID7

ID4

ID0

1991h

00h

Reset Mode 3

SE4 SE3 SE2 SE1

ID8

ID7

1980h

02h

Master Volume

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

8000h

04h

Alternate Line Out Volume Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

8000h

06h

Master Volume Mono

Mute

MM4

MM3

MM2

MM1

MM0

8000h

0Eh

Mic Volume

Mute

20dB

GN4

GN3

GN2

GN1

GN0

8008h

10h

Line In Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

12h

CD Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

14h

Video Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

16h

Aux Volume

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

18h

PCM Out Vol

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

8808h

1Ah

Record Select

SL2

SL1

SL0

SR2

SR1

SR0

0000h

1Ch

Record Gain

Mute

GL3

GL2

GL1

GL0

GR3

GR2

GR1

GR0

8000h

Record Gain Microphone

Mute

GR3

GR2

GR1

GR0

8000h

20h

General Purpose

POP

LPBK

0000h

22h

3D Control

0000h

26h

Powerdown Ctrl/Stat

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

000Fh

28h

Ext'd Audio ID Mode 0

ID1

ID0

VRA

x000h

28h

Ext'd Audio ID Mode 1

ID1

ID0

VRA

x000h

28h

Ext'd Audio ID Mode 2

ID1

ID0

VRA

x000h

28h

Ext'd Audio ID Mode 3

ID1

ID0

LDAC SDAC CDAC

VRA

x1C0h

2Ah

Ext'd Audio Ctrl Mode 0

0000h

2Ah

Ext'd Audio Ctrl Mode 1

0000h

2Ah

Ext'd Audio Ctrl Mode 2

PRL

MADC

0200h

2Ah

Ext'd Audio Ctrl Mode 3

PRK

PRJ

PRI

LDAC SDAC CDAC

01C0h

2Ch

PCM Front DAC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

2Eh

PCM Surround DAC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

30h

PCM LFE DAC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

32h

PCM Left/Right ADC Rate SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

34h

MIC ADC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

36h

Center LFE Volume

Mute

LFE5 LFE4 LFE3

LFE2

LFE1

LFE0

Mute

CNT5 CNT4 CNT3 CNT2 CNT1

CNT0 8080h

38h

LR Surround Volume

Mute

LSR5 LSR4 LSR3 LSR2 LSR1

LSR0 Mute

RSR5 RSR4 RSR3 RSR2 RSR1

RSR0 8080h

3Ch

Ext'd Modem ID Mode 0

ID1

ID0

HSET

LIN1

x005h

3Ch

Ext'd Modem ID Mode 1

ID1

ID0

LIN2

x003h

3Ch

Ext'd Modem ID Mode 2

ID1

ID0

LIN1

x001h

Ext'd Modem ID Mode 3

ID1

ID0

x000h

Ext'd Modem Stat/Ctrl

Mode 0

PRH

PRG

PRD

PRC

PRB

PRA

HDAC HADC

DAC1 ADC1 MREF

GPIO 00CFh

Ext'd Modem Stat/Ctr

Mode1

PRF

PRE

PRD

PRC

PRB

PRA

DAC2 ADC2 DAC1 ADC1 MREF

GPIO 003Fh

Ext'd Modem Stat/Ctrl

Mode 2

PRH

PRD

PRC

PRB

PRA

HDAC

DAC1 ADC1 MREF

GPIO 008Fh

Ext'd Modem Stat/Ctrl

Mode 3

PRG

PRC

PRB

PRA

HADC

ADC1 MREF

GPIO 0047h

Line 1 DAC/ADC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

Line 2 DAC/ADC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

Handset DAC/ADC Rate

SR15

SR14 SR13 SR12 SR11 SR10 SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

BB80h

Line 1 DAC/ADC Level

Mute

DAC3 DAC2 DAC1

DAC0 Mute

ADC3 ADC2

8080h

Table 1. Mixer Registers

CS4298

DS315PP2

Line 2 DAC/ACD Level

Mute

DAC3 DAC2 DAC1

DAC0 Mute

ADC3 ADC2

8080h

Handset DAC/ACD Level

Mute

DAC3 DAC2 DAC1

DAC0 Mute

ADC3 ADC2

8080h

GPIO Pin Configuration

GC9

GC8

GC7

GC6

GC5

GC4

GC3

GC2

GC1

GC0

03FFh

GPIO Pin Polarity/Type

GP9

GP8

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

FFFFh

GPIO Pin Sticky

GS9

GS8

GS7

GS6

GS5

GS4

GS3

GS2

GS1

GS0

0000h

GPIO Pin Walk-up Mask

GW9

GW8

GW7

GW6

GW5

GW4

GW3

GW2

GW1

GW0

0000h

GPIO Pin Status

GI9

Gi8

GI7

GI6

GI5

GI4

GI3

GI2

GI1

GI0

xxxxh

Misc. Modem AFE Stat

Mode 0

HSB2 HSB1

HSB0

L1B2

L1B1

L1B0

0000h

Misc. Modem AFE Stat

Mode 1

L2B2

L2B1

L2B0

L1B2

L1B1

L1B0

0000h

Misc. Modem AFE Stat

Mode 2

L1B2

L1B1

L1B0

0000h

Misc. Modem AFE Stat

Mode 3

0000h

Cirrus Defined Registers:

Crystal Revision / Fab

0302h

Slot Map Register

EDM

EAM

DDM

MD1

MD0

0000h

S/PDIF Enable

SPEN

CC6

CC5

CC4

CC3

CC2

CC1 CC0

Pre

Copy #Audio

Pro

0000h

7Ch

Vendor ID1(CR)

4352h

7Eh

Vendor ID2(Y-)

PID2

PID1

PID0

RID2

RID1

RID0

5923h

Reg

Num

Name

D15

D14

D13

D12

D11

D10

Default

Table 1. Mixer Registers

(cont.)

CS4298

DS315PP2

6.1

Register Descriptions

6.1.1

Reset (Index 00h)

SE[4:0]

3D Stereo Enhancement Technique.
00110 - Crystal 3D Stereo Enhancement.

ID8 set

18-bit ADC resolution.

ID7 set

20-bit DAC resolution.

ID4 set

Headphone out support. (Alternate Line Output)

ID1 set

Dedicated Mic PCM.

Read-only dataMode 0,1 1990h

Mode 2 1991h
Mode 3 1980h

Any write to this register causes the audio control registers (Index 02h - 38h) and the Crystal specific
registers (Index 5Eh - 68h) to be reset forcing them to their default state. The mode control bits
MD[1:0] of the AC Mode Control (Index 5Eh) register are also cleared forcing the Codec to Mode 0
configuration. Reads return configuration information about the audio Codec

6.1.2

Master Volume (Index 02h)

Mute

Master mute for the LINE_OUT_L and the LINE_OUT_R output signals.

ML[5:0]

Master Volume control for LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 = 0 dB.
The total range is 0 dB to -94.5 dB.

MR[5:0]

Master Volume control for LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 = 0 dB.
The total range is 0 dB to -94.5 dB.

Default

8000h, corresponding to 0 dB attenuation and mute on.

In Mode 3 the LINE_OUT volume is controlled by the Left Right Surround (Index 38h) register in place
of Master Volume.

Mode

D15

D14

D13

D12

D11

D10

SE4

SE3

SE2

SE1

SE0

ID8

ID7

ID4

SE4

SE3

SE2

SE1

SE0

ID8

ID7

ID4

SE4

SE3

SE2

SE1

SE0

ID8

ID7

ID4

ID0

SE4

SE3

SE2

SE1

SE0

ID8

ID7

D15

D14

D13

D12

D11

D10

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

CS4298

DS315PP2

6.1.3

Alternate Volume (Index 04h)

Mute

Master mute for the ALT_LINE_OUT_L and the ALT_LINE_OUT_R output signals.

ML[5:0]

Master Volume control for ALT_LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 =
0 dB. The total range is 0 dB to -94.5 dB.

MR[5:0]

Master Volume control for ALT_LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 =
0 dB. The total range is 0 dB to -94.5 dB.

Default

8000h, corresponding to 0 dB attenuation and mute on.

In Mode 3 the ALT_LINE_OUT volume is controlled by the LFE/CNT Volume (Index 36h) register
in place of Alternate Volume..

6.1.4

Microphone Volume (Index 0Eh)

Mute

When set, mutes MIC1/MIC2 signal.

GN[4:0]

MIC1/MIC2 Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range
is 12 dB to -34.5 dB.

20dB

Enables 20 dB microphone gain block.

Default

8008h, 0 dB attenuation and Mute set.

This register controls the gain level of the Microphone input source to the Input Mixer. It also con-
trols the +20 dB gain block which connects to the input volume control and to the Input Record Mux.
The selection of MIC1 or MIC2 input pins is controlled by the MS bit in the General Purpose (Index
20h) register. The gain mapping for this register is shown in Table 3.

D15

D14

D13

D12

D11

D10

Mute

ML5

ML4

ML3

ML2

ML1

ML0

MR5

MR4

MR3

MR2

MR1

MR0

ML[5:0]/MR[5:0]/MM[5:0]

Write

ML[5:0]/MR[5:0]/MM[5:0

Read

Gain Level

000000

0 dB

000001

-1.5 dB

...

111111

-94.5 dB

Table 2. Alternate Line-Out and Master Mono Attenuation

D15

D14

D13

D12

D11

D10

Mute

20dB

GN4

GN3

GN2

GN1

GN0

GN4 - GN0

Gain Level

Mic Gain with 20dB = 1

00000

+12.0 dB

+32.0 dB

00001

+10.5 dB

30.5 dB

...

00111

+1.5 dB

21.5 dB

01000

0.0 dB

20.0 dB

01001

-1.5 dB

18.5 dB

...

11111

-34.5 dB

-14.5 dB

Table 3. Analog Mixer Input Gain Values

CS4298

DS315PP2

6.1.5

Stereo Analog Mixer Input Gain (Index's 10h - 18h)

Mute

When set mutes the respective input. Setting this bit mutes both right and left inputs.

GL[4:0]

Left Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12 dB
to -34.5 dB. See Table 3.

GR[4:0]

Right Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12
dB to -34.5 dB. See Table 3.

Default

8808h, 0 dB gain with Mute enabled.

These registers control the gain levels of the analog input sources to the Input Mixer. The analog in-
puts associated with registers 10h-18h are found in Table 4.

6.1.6

Input Mux Select (Index 1Ah)

SL[2:0]

Left Channel ADC input source select.

SR[2:0]

Right Channel ADC input source select.

Default

0000h, MIC inputs selected for both channels.

When capturing PCM data, this register controls the input MUX for the ADCs. Table 5 below lists
the possible values for each input.

D15

D14

D13

D12

D11

D10

Mute

GL4

GL3

GL2

GL1

GL0

GR4

GR3

GR2

GR1

GR0

Register Index

Function

10h

Line IN Volume

12h

CD Volume

14h

Video Volume

16h

Aux Volume

18h

PCM Out Volume

Table 4. Stereo Volume Register Index

D15

D14

D13

D12

D11

D10

SL2

SL1

SL0

SR2

SR1

SR0

Sx2 - Sx0

Record Source

MIC

CD Input

Video Input

AUX Input

Line Input

Stereo Mix

Mono Mix

Not Available

Table 5. Input Mux Selection

CS4298

DS315PP2

6.1.7

Record Gain (Index 1Ch)

Mute

When set, mutes the input to the ADCs.

GL[3:0]

Left ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.
The total range is 0 dB to +22.5 dB.

GR[3:0]

Right ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.
The total range is 0 dB to +22.5 dB.

Default

8000h, 0 dB gain with Mute on.

6.1.8

Record Gain Microphone (Index 1Eh)

Mute

When set, mutes the input to MADC2.

GM[3:0]

Dedicated Microphone gain. Least significant bit represents +1.5 dB with 0000 = 0 dB.
The total range is 0 dB to +22.5 dB.

Default

8000h, 0 dB gain with Mute on.

This register is only available in Mode 2.

6.1.9

General Purpose (Index 20h)

POP

PCM Output Path. By default, the PCM output is mixed prior to the 3D enhancement. When set, the
PCM output is mixed after the 3D enhancement.

3D Enable. If set, enables the CrystalClear 3D stereo enhancement.

Microphone Select. Determines which of the two MIC inputs are passed to the mixer. When set, MIC2
input is selected; when clear MIC1 is selected.

LPBK

Loopback. If set, enables Analog ADC/DAC Loopback Mode.

Default

0000h.

6.1.10 3D Control (Index 22h)

S[3:0]

Spacial Enhancement Depth. Spacial Enhancement is enabled by the 3D bit in the

General Purpose

(Index 20h) register.
0000 - No spacial enhancement.
1111 - Full spacial enhancement.

Default

0000h, no spacial enhancement added.

The Spacial Enhancements is not available on the ALT_LINE output when the codec is in Mode 3
or EAM is set. See the AC Mode Control (Index 5Eh) register for more detail.

D15

D14

D13

D12

D11

D10

Mute

GL3

GL2

GL1

GL0

GR3

GR2

GR1

GR0

D15

D14

D13

D12

D11

D10

Mute

GM3

GM2

GM1

GM0

D15

D14

D13

D12

D11

D10

POP

LPBK

D15

D14

D13

D12

D11

D10

CS4298

DS315PP2

6.1.11 Power Down Control/Status (Index 26h)

PR6

When set, the alternate line-out buffer is powered down.

PR5

When set, the internal master clock is disabled. The only way to recover from setting this bit is through
a cold AC `97 reset (driving the RESET# signal active).

PR4

When set, the AC link is powered down. The AC link can be restarted through a warm AC `97 reset using
the SYNC signal, or a cold AC `97 reset using the RESET# signal (the primary codec only).

PR3

When set, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL,
ADC, and DAC bits should be checked before writing any mixer registers. Because the reference volt-
age is shared with the modem subsection, it will not power down unless the PRB bit is also set in the

Ext'd Modem Stat/Ctrl

(Index 3Eh) register.

PR2

When set, the analog mixer is powered down (the voltage reference is still active). When clearing this
bit, the ANL bit should be checked before writing any mixer registers.

PR1

When set, the DACs are powered down. When clearing this bit, the DAC bit should be checked before
sending any data to the DACs.

PR0

When set, the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data
will be sent down the AC link until the ADC bit goes high.

REF

Voltage Reference Ready Status. When set, indicates the voltage reference is at a nominal level.

ANL

Analog Ready Status. When set, the analog output mixer, input multiplexer, and volume controls are
ready. When clear, no volume control registers should be written.

DAC

DAC Ready Status. When set, the DACs are ready to receive data across the AC link. When clear, the
DACs will not accept any valid data.

ADC

ADC Ready Status. When set, the ADCs are ready to send data across the AC link. When clear, no data
will be sent to the Controller.

Default

0000h, all blocks are powered on. The lower four bits will eventually change as the Codec finishes an
initialization and calibration sequence.

The PR[6:0] are power-down control for different sections of the Codec. The REF, ANL, DAC, and
ADC bits are status bits which, when set, indicate that a particular section of the Codec is ready. After
the Controller receives the Codec Ready bit in Slot 0, these status bits must be checked before writing
to any mixer registers.

D15

D14

D13

D12

D11

D10

PR6

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

CS4298

DS315PP2

6.1.12 Extended Audio ID (Index 28h)

ID[1:0]

Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the ID[1:0]# con-
figuration pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits
in this register.

LDAC

PCM LFA DAC. Indicates a LFE DAC is supported.

SDAC

PCM Surround DAC. Indicates a Surround DAC is supported.

CDAC

PCM Center DAC. Indicates a Center DAC is supported.

VRA

Variable Rate Audio. This bit is clear indicating variable sample rates are not supported.

Read-only data Mode 0,1,2 x000h. Where x is determined by the state of ID[1:0] input pins.

Mode 3 x1C0h.

6.1.13 Extended Audio Status / Control (Index 2Ah)

CDAC

PCM Center DAC Ready. When set, the Center DAC is ready.

LDAC

PCM LFE DAC Ready. When set, the LFE DAC is ready.

SDAC

PCM Surround DAC Ready. When set, the Surround DACs are ready.

MADC

MIC ADC Ready. When Set, the dedicated Microphone ADC is ready.

PRI

PCM Center DAC Disable. When set, the Center DAC is disabled.

PRJ

PCM Surround DAC Disable. When set, the Surround DAC is disabled.

PRK

PCM LFE DAC Disable. When set, the LFE DAC is disabled.

PRL

Dedicated Microphone ADC Disable. When set, the MIC ADC is disabled.

Default

Mode 0,1 0000h
Mode 2 0200h
Mode 3 01C0h

CDAC, LDAC, SDAC, and MADC are read only bits.

Mode

D15

D14

D13

D12

D11

D10

ID1

ID0

VRA

ID1

ID0

VRA

ID1

ID0

VRA

ID1

ID0

LDAC SDAC CDAC

VRA

Mode

D15

D14

D13

D12

D11

D10

PRL

MDAC

PRK

PRJ

PRI

LDAC

SDAC

CDAC

CS4298

DS315PP2

6.1.14 PCM Front DAC Rate (Index 2Ch)

SR[15:0]

Front DAC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.15 PCM Surround DAC Rate (Index 2Eh)

SR[15:0]

Surround DAC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.16 PCM LFE DAC Rate (Index 30h)

SR[15:0]

LFE DAC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.17 PCM LR ADC Rate (Index 32h)

SR[15:0]

LR ADC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.18 PCM MIC ADC Rate (Index 34h)

SR[15:0]

MIC ADC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

CS4298

DS315PP2

6.1.19 Center LFE Volume (Index 36h)

LFE[5:0]

LFE Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -
94.5 dB.

CNT[5:0]

Center Volume.Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -
94.5 dB.

Default

8080h, indicating mute with 0 dB attenuation.

6.1.20 LR Surround Volume (Index 38h)

LSR[5:0]

Left Surround Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0
dB to -94.5 dB.

RSR[5:0]

Right Surround Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0
dB to -94.5 dB.

Default

8080h, indicating 0 dB attenuation.

6.1.21 Extended Modem ID (Index 3Ch)

HSET

Handset. Indicates handset ADC/DAC is supported.

LIN1

Line 1. When set, indicates 1st line is supported.

LIN2

Line 2. When set, indicates 2nd line is supported.

ID[1:0]

Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the configuration
pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this reg-
ister.

Default

Mode 0 x005h
Mode 1 x003h
Mode 2 x001h
Mode 3 x000h Where x is determined by the state of ID[1:0] input pins.

The Extended Modem ID is a read/write register that identifies the Codec's modem capabilities. This
register reports the features available based on the basic operating mode determined by MD[1:0] of
AC Mode (Index 5Eh) register. Writing any value to this location issues a reset to the modem regis-
ters (Index 3Ch-56h). Audio registers are not reset by a write to this location.

NOTE: All GPIO registers (Index 46h-54h) are reset by any write to this location.

D15

D14

D13

D12

D11

D10

Mute

LFE5

LFE4

LFE3

LFE2

LFE1

LFE0

Mute

CNT5 CNT4

CNT3 CNT2 CNT1

CNT0

LFE[5:0]/LSR[5:0]

CNT[5:0]/RSR[5:0]

Write

LFE[5:0]/LSR[5:0]

CNT[5:0]/RSR[5:0]

Read

Gain Level

000000

0 dB

000001

-1.5 dB

...

111111

-94.5 dB

Table 6. 6 Channel Volume Attenuation

D15

D14

D13

D12

D11

D10

Mute

LSR5

LSR4

LSR3

LSR2

LSR1

LSR0

Mute

RSR5 RSR4 RSR3 RSR2 RSR1 RSR0

Mode

D15

D14

D13

D12

D11

D10

ID1

ID0

HSET

LIN1

ID1

ID0

LIN2

ID1

ID0

LIN1

ID1

ID0

CS4298

DS315PP2

6.1.22 Extended Modem ID (Index 3Eh)

PRH

Handset DAC. When set powers down the Handset DAC.

PRG

Handset ADC. When set powers down the Handset ADC.

PRF

Line 2 DAC. When set powers down the Line 2 DAC.

PRE

Line 2 ADC. When set powers down the Line 2 ADC.

PRD

Line 1 DAC. When set powers down the Line 1 DAC.

PRC

Line 1 ADC. When set powers down the Line 1 ADC.

PRB

Modem Reference. When set powers down the modem reference. The modem and audio share a com-
mon reference. The reference will not power down unless PR3 of the

Power Down Ctrl/Stat

(Index 26h)

PRA

GPIO. When set the GPIO pins are tri-state and powered down. Slot 12 is marked invalid if the AC-link
is active.

HDAC

Handset DAC. When set indicates the Handset DAC is ready.

HADC

Handset ADC. When set indicates the Handset ADC is ready.

DAC2

Line 2 DAC. When set indicates the Line 2 DAC is ready.

ADC2

Line 2 ADC. When set indicates the Line 2 ADC is ready.

DAC1

Line 1 DAC. When set indicates the Line 1 DAC is ready.

ADC1

Line 1 ADC. When set indicates the Line 1 ADC is ready.

MREF

Modem Reference. When set indicates the modem reference is ready.

GPIO

GPIO. When set the GPIO pins are ready. Slot 12 is marked valid.

Default

Mode 0 x0CFh
Mode 1 x03Fh
Mode 2 x08Fh
Mode 3 x047h Where x is determined by the state of ID[1:0] input pins.

PR[A:H] are read/write bits that provide power management of the modem AFE subsection. All re-
maining bits are read/only status indicating modem subsystems are ready for operation. After reset
or issuing a change to the MD[1:0] of AC Mode (Index 5Eh) register, the respective status bits for
that mode will be clear until the subsystem becomes ready.

6.1.23 Line 1 DAC/ADC Rate (Index 40h)

SR[15:0]

Line 1 DAC/ADC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.24 Line 2 DAC/ADC Rate (Index 42h)

SR[15:0]

Line 2 DAC/ADC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

Mode

D15

D14

D13

D12

D11

D10

PRH

PRG

PRD

PRC

PRB

PRA

HDAC

HADC

DAC1

ADC1

MREF

GPIO

PRF

PRE

PRD

PRC

PRB

PRA

DAC2

ADC2

DAC1

ADC1

MREF

GPIO

PRH

PRD

PRC

PRB

PRA

HDAC

DAC1

ADC1

MREF

GPIO

PRG

PRC

PRB

PRA

HADC

ADC1

MREF

GPIO

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

CS4298

DS315PP2

6.1.25 Handset DAC/ADC Rate (Index 44h)

SR[15:0]

Handset DAC/ADC Sample Rate.

Default

Read-only value BB80h, indicating 48 kHz sample rate.

6.1.26 Line 1 DAC/ADC Level (Index 46h)

Mute[D15] Mute. Mutes the input of Line 1 DAC.

Mute[D7]

Mute. Mutes the output of Line 1 ADC.

DAC[3:0]

Line 1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0
dB to -22.5 dB.

ADC[3:2]

Line 1 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB.

Default

8080h indicating mute with 0 dB attenuation or gain.

When EAM of the AC Mode Control (Index 5Eh) is set, the Line 1 DAC attenuation is controlled by
ML[4:0] of the Alternate Volume (Index 04h) register.

6.1.27 Line 2 DAC/ADC Level (Index 48h)

Mute[D15] Mute. Mutes the input of Line 2 DAC.

Mute[D7]

Mute. Mutes the output of Line 2 ADC.

DAC[3:0]

Line 2 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0
dB to -22.5 dB.

ADC[3:2]

Line 2 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB.

Default

8080h indicating mute with 0 dB attenuation or gain.

When EAM of the AC Mode Control (Index 5Eh) is set, the Line 2 DAC attenuation is controlled by
MR[4:0] of the Alternate Volume (Index 04h) register.

6.1.28 Handset DAC/ADC Level (Index 4Ah)

Mute[D15] Mute. Mutes the input of Handset DAC.

Mute[D7]

Mute. Mutes the output of Handset ADC.

DAC[3:0]

Handset1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range
is 0 dB to -22 dB.

ADC[3:2]

Handset ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to
+18 dB.

Default

8080h indicating mute with 0 dB attenuation or gain.

D15

D14

D13

D12

D11

D10

SR15

SR14

SR13

SR12

SR11

SR10

SR9

SR8

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

D15

D14

D13

D12

D11

D10

Mute

DAC3 DAC2 DAC1 DAC0

Mute

ADC3 ADC2

D15

D14

D13

D12

D11

D10

Mute

DAC3 DAC2 DAC1 DAC0

Mute

ADC3 ADC2

D15

D14

D13

D12

D11

D10

Mute

DAC3 DAC2 DAC1 DAC0

Mute

ADC3 ADC2

CS4298

DS315PP2

6.1.29 GPIO Pin Configuration (Index 4Ch)

GC[9:0]

GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input

Default

03FFh

After a cold reset, power up, or modem register reset (see Extended Modem ID (Index 3Ch)) all
GPIO pins are configured as inputs.

6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh)

GP[9:0]

GPIO Pin Configuration. The definition of GP[9:0] changes based on the pin defined as an input or an
output by GC[9:0] of

GPIO Pin Configuration (Index 4Ch).

Default

FFFFh

When the GPIO pin is defined as an input, its status is reported in the GPIO Pin Status (Index 54h)
register as well as Slot 12.

6.1.31 GPIO Pin Sticky (Index 50h)

GS[9:0]

GPIO Pin Sticky. If set, the GPIO pin input is latched.

Default

0000h

If a GPIO is defined as "sticky" the input requires a transition of the GPIO input pin to set the corre-
sponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When "sticky" is set the corre-
sponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge
of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to
low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the "sticky" input.

D15

D14

D13

D12

D11

D10

GC9

GC8

GC7

GC6

GC5

GC4

GC3

GC2

GC1

GC0

D15

D14

D13

D12

D11

D10

GP9

GP8

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

GCx

GPx

Function

Output

CMOS drive

Output

Open drain

Input

Active Low

Input

Active High (default)

Table 7. GPIO Input/Output Configuration

D15

D14

D13

D12

D11

D10

GS9

GS8

GS7

GS6

GS5

GS4

GS3

GS2

GS1

GS0

CS4298

DS315PP2

6.1.32 GPIO Pin Wakeup Mask (Index 4Ch)

GS[9:0]

Wake up mask. If set, allow the GPIO input to generate AC-LINK wake up protocol.

Default

0000h

The CS4298 has the ability to generate a "wake up" cycle by a transition of a GPIO pin when the
AC-Link has been powered down. If a mask bit is set, a one being set in the corresponding GPIO Pin
Status (Index 54h) will initiate a wake up interrupt. Bit 0 of SDATA_IN Slot 12 will be set indicating
a GPIO interrupt. GPIO pins must be defined as "input", "sticky", and the mask set to allow a GPIO
interrupt. The GPIO interrupt is cleared by writing a 0 to the respective status bit in GPIO Pin Status
(Index 54h) register.

6.1.33 GPIO Pin Status (Index 54h)

GI[9:0]

GPIO pin status. Reflects the state of all GPIO pins either input or output. If the GPIO pin is defined as
an output, the respective bit reflects the state of SDATA_OUT Slot 12. If the GPIO pin is defined as an
input, the register is reflected in SDATA_IN Slot 12. GPIO output pins cannot be accessed by Slot 1,2
register access, only by SDATA_OUT Slot 12.

6.1.34 Misc. Modem AFE Status (Index 56h)

HSB[2:0]

Handset Loopback.

L2B[2:0]

Line 2 Loopback.

L1B[2:0]

Line 1 Loopback.

Default

0000h.

D15

D14

D13

D12

D11

D10

GW9

GW8

GW7

GW6

GW5

GW4

GW3

GW2

GW1

GW0

D15

D14

D13

D12

D11

D10

GI9

GI8

GI7

GI6

GI5

GI4

GI3

GI2

GI1

GI0

Mode

D15

D14

D13

D12

D11

D10

HSB2

HSB1

HSB0

L1B2

L1B1

L1B0

L2B2

L2B1

L2B0

L1B2

L1B1

L1B0

L1B2

L1B1

L1B0

Loop Back Mode

HSB[2:0], L2B[2:0], L1B[2:0]

Function

000

Disabled

001

Digital Loop Back

010

Local Analog Loop Back

011

DAC to ADC 1-Bit data Loop Back

100

Remote Analog Loop Back

101

AC-Link Loop Back

110-111

Not Used

Table 8. Misc. Modem Configuration

CS4298

DS315PP2

6.1.35 AC Mode Control (Index 5Eh)

DDM

DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When set, the
Left and Right DAC directly drive the line and alternate line outputs by bypassing the audio mixer. When
clear, the audio mixer is the source for the line and alternate line outputs.

EAM

Extended Audio Mode. When set the output of MDAC2 and MDAC1 are mapped to the ALT_LINE OUT-
PUT. The MDAC volumes are set by the

Alternate Line Volume (Index 04h)

EDM

Extended Docking Mode. When set the output of the analog input mixer is routed to the MADC1 and
MADC2 inputs. This allows any analog input mix to be digitized and routed to a second AC `97 codec
or allows the host controller to add effects processing to analog sources.

MD[1:0]

Mode. Sets basic operating mode for the codec. This effects the mapping of the ADCs and DACs to AC-
LINK Slot locations. See the Mode of Operation subsection for additional detail. Table XXX below details
the Slot mapping.

Default

0000h

6.1.36 S/PDIF Control (Index 68h)

SPEN

S/PDIF Enable. When set, Slot 6 and Slot 9 are mapped to the SPDIF_OUT pin. When in Mode 3 and
SPEN set, data is not passed to Modem DAC1 and Modem DAC2.

Validity Bit. When set, this bit notifies the S/PDIF receiver that the subframe data is not suitable for con-
version.

Generation Level.

CC[6:0]

Category Code.

Pre

Premphasis. If set, filter premphasis is 50/15

s. If clear, premphasis is none.

Copy

#Audio

#Audio valid. When clear, the data routed to the S/PDIF transmitter contains valid PCM data. For trans-
mitting all other compressed data formats, the #Audio bit must be set.

Default

0000h.

D15

D14

D13

D12

D11

D10

EDM

EAM

DDM

MD1

MD0

Mode

Definition

Audio

DAC1

Audio

DAC2

Audio

ADC1

Audio

ADC2

Modem

DAC1

Modem

DAC2

Modem

ADC1

Modem

ADC2

GPIO

Basic

Left

Right

Left

Right

Line 1

Handset

Line 1

Handset

2 Line

Left

Right

Left

Right

Line 1

Line 2

Line 1

Line 2

Speakerphone

Left

Right

Left

Right

Line 1

Handset

Line 1

Mic

Extended 4

Channel

Surrnd

Left

Surrnd

Right

Left

Right

Center

LFE

Line 1

Handset

Table 9. Slot Assignments

D15

D14

D13

D12

D11

D10

SPEN

CC6

CC5

CC4

CC3

CC2

CC1

CC0

Pre

Copy #Audio

CS4298

DS315PP2

7. ANALOG HARDWARE DESCRIPTION

The analog hardware consist of a four line-level stereo inputs, two selectable mono microphone in-
puts, two mono inputs, a mono output, and dual, independent stereo line outputs. This section de-
scribes the analog hardware needed to interface with these pins.

7.1

Line-Level Inputs

The analog inputs consist of four stereo analog inputs and four mono inputs. As shown in Figure 8,
the input to the ADCs comes from the Input Mux which selects one of the following: Phone (Mono),
Aux, Video, CD, Mic1 or Mic2 (Mono), Line, Stereo Output Mix, or the Mono Output Mix (Mono).
Unused analog inputs should be connected together and then connected through a capacitor to analog
ground or tied to the Vrefout line directly.

The analog input mixer is designed to accommodate five stereo inputs and one mono input. These
inputs are: a stereo line-level input (LINE), a mono microphone input (MIC), a stereo CD-ROM in-
put (CD), a stereo auxiliary line-level input (AUX), and the PCM output from the DACs. Each of the
stereo inputs has separate volume controls for each channel and one mute control for each left/right
pair. The mono microphone input has one mute and one volume control.

The inputs to the output mixer are: the input mixer output, the PC Beep mono input, and the Phone
mono input.

All analog inputs to the CS4298, including CD_GND, should be capacitively coupled to the input
pins.

Since many analog levels can be as large as 2 V

RMS

, the circuit shown in Figure 10 can be used to

attenuate the analog input by 6 dB (to 1 V

RMS)

which is the maximum voltage allowed for all the

stereo line-level inputs: LINE_IN, AUX_IN, and VIDEO_IN.

The CD line-level inputs have an extra pin, CD_GND, which provides a pseudo-differential input for
both CD_L and CD_R. This pin takes the common-mode noise out of the CD inputs when connected
to the ground coming from the CD analog source. Connecting the CD pins as shown in Figure 11
provides extra attenuation of common mode noise coming from the CDROM drive, thereby produc-
ing a higher quality signal. One percent resistors are recommended since the better the resistors
match, the better the common-mode attenuation of unwanted signals. If CD is not used, the inputs
should be connected through AC capacitors to analog ground or connected to Vrefout.

6.8 k

1.0

6.8 k

Figure 10. Line Inputs

Figure 11. Differential CDROM In

6.8 k

1.0

CD_L

CD_R

6.8 k

3.4 k

CD_GND

2.0

3.4 k

(All resistors 1%)

CS4298

DS315PP2

7.2

Microphone Level Inputs

The microphone level inputs, MIC1 and MIC2, include a selectable -34.5 dB to +12 dB gain stage
for interfacing to an external microphone. An additional 20 dB gain block is also available. Figure 12
illustrates a single-ended microphone input buffer circuit that will support lower gain mics. The cir-
cuit in Figure 12 supports dynamic mics and phantom-powered mics that use the right channel (ring)
of the jack for power..

7.3

Line Level Outputs

The analog output section provides a stereo line-level output and an alternate stereo line-level output.
LINE_OUT_L, LINE_OUT_R, ALT_LINE_OUT_L, and ALT_LINE_OUT_R outputs should be
capacitively coupled to external circuitry.

The mono output, MONO_OUT, can be used as either a sum of the left and right output channels
attenuated by 6 dB to prevent clipping at full scale or the selected MIC_IN signal. The mono out
channel can be used to drive the PC internal mono speaker using an appropriate drive circuit. This
approach allows the traditional PC sounds to be integrated with the rest of the audio system. The mute
control is independent of the line outputs allowing the mono channel to mute the speaker without
muting the line outputs.

Each of the 5 analog outputs, if used in the design, require 680 pF or larger NPO dielectric capacitors
between the corresponding pin and AGND. Each analog output is DC biased up to the Vrefout volt-
age signal reference which is nominally 2.2 V. This requires that the output either be AC coupled to
external circuitry (AC load must be greater than 10 k

) or DC coupled to a buffer op-amp biased at

the Vrefout voltage (see Figure 13 for the recommended headphone op-amp circuit).

AGND

+5 VA

100 k

2.7 k

CGND

220 pF

68 k

AGND

0.068 µF

X7R

AGND

+5 VA

U1A
MC33078D

47 k

10 µF

AGND

47 k

AGND

+5 VA

47 k

6.8 k

10 µF

AGND

220 pF

47 k

U1B
MC33078D

1 µF

X7R

MIC1

Figure 12. PC `99 Microphone Pre-amplifier

CS4298

DS315PP2

7.4

Consumer IEC-958 Digital Interface (S/PDIF)

The CS4298 supports the industry standard IEC-958 consumer digital interface. Sometimes this stan-
dard is referred to as S/PDIF, which refers to an older version of this standard. This output provides
an interface, external to the PC, for storing digital CD-ROM) or playing digital audio from digital
speakers. Figure 14 illustrates the circuit necessary for implementation of the IEC-958 consumer in-
terface. The CS4298 is capable of directly driving the voltage divider for the 75

interface. An op-

tional current driver is shown when an increase of the transmission range of the coaxial circuitry is
required. An optional fiber optic circuit may be connected directly to the CS4298.

7.5

Miscellaneous Analog Signals

The AFILT1 and AFILT2 pins must have a 1000 pF NPO capacitor (must not be smaller than 390
pF) to analog ground. These capacitors, along with an internal resistor, provide a single-pole low-
pass filter at the inputs to the ADCs. By placing these filters at the input to the ADCs, low-pass filters
at each analog input pin are not necessary.

The REFFLT pin lowers the noise of the internal voltage reference. A 1

F (must not be greater than

F) and 0.1

F capacitor to analog ground should be connected with a short, wide trace to this pin.

No other connection should be made, as any coupling onto this pin will degrade the analog perfor-
mance of the Codec. Likewise, digital signals should be kept away from REFFLT for similar reasons.

Figure 13. Headphones Driver

AGND

1/4 WATT

HP_OUT_R

ALT_LINE_OUT_L

HP_OUT_L

Vrefout

ALT_LINE_OUT_R

22pF

NPO

39k

1
2

22pF

NPO

TDA1308

27k

1
2

TDA1308

220

ELEC

47K

1 2

ELEC

680pF

NPO

680pF

NPO

0.1

Y5V

1.0

Y5V

220

CS4298

DS315PP2

The Vrefout pin is typically 2.2 V and provides a common mode signal for single-supply external
circuits. Vrefout only supports light DC loads and should be buffered if AC loading is needed. For
typical use, a 0.1

F in parallel with a 1

F capacitor should be connected to Vrefout.

7.6

Power Supplies

The power supplies providing analog power should be as clean as possible to minimize coupling into
the analog section which could degrade analog performance. The pins AVdd1 and AVdd2 supply
power to all the analog circuitry on the CS4298. This 5 Volt analog supply should be generated from
a voltage regulator (7805 type) connected to a +12 Volt supply. This helps isolate the analog circuitry
from noise typically found on +5 V digital supplies which power many digital circuits in a PC envi-
ronment. A typical voltage regulator circuit for analog power using an MC78M05CDT is shown in
Figure 15.

The digital power pins DVdd1 and DVdd2 should be connected to the same digital supply as the AC
'97 Controller's AC-Link interface. Since the digital interface on the CS4298 may operate at either
3.3 V or 5 V, proper connection of these pins will depend on the digital power supply of the AC '97
Controller. connections (vias). The AC-Link digital interface connection traces should be routed

DGND

374

90.9

J-RCA-R4-PCB

GND

VCC

+5 V PCI

0.1

SN75179D

DGND

+5V_PCI

SPDIFO

TOTX-173

8.2K

SPDIFO

Figure 14. IEC-958 Interface Examples

+12VD

AGND

DGND

+5VA

0.1µF

Y5V

10µF

ELEC

10µF

ELEC

MC78M05CDT

OUT

GND

0.1µF

Y5V

Figure 15. Voltage Regulator

CS4298

DS315PP2

8.1

Digital I/O Pins

RESET# - AC '97 Chip Reset, Input

This active low signal is the asynchronous Cold Reset input to the CS4298. The CS4298 must
be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the
RESET# rising edge will be used as an AC `97 2.1 Warm Reset only, preserving register
values.

SYNC - AC-link Serial Port Sync pulse, Input

This signal is the serial port timing signal for the AC-link of the CS4298. Its period is the
reciprocal of the sample rate of the CS4298, 48 kHz. This signal is generated by the AC '97
Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the
CS4298 is in a PR4 powerdown state and is configured as a primary codec. A series
terminating resistor of 47

should be connected on this signal close to the device driving the

signal.

BIT_CLK - AC-link Serial Port Master Clock, Input/Output

This input/output signal controls the master clock timing for the AC-link. In codec primary
mode, this signal is an output 12.288 MHz clock signal which is divided down by two from the
XTL_IN input clock pin. In codec secondary mode, this signal is an input which controls the
AC-link serial interface. In BIT_CLK mode, this signal generates all internal clocking including
the AC-link serial interface timing. A series terminating resistor of 47

should be connected

on this signal close to the CS4298 in primary mode or close to the BIT_CLK source if in
secondary mode.

SDATA_OUT - AC-link Serial Data Input Stream to AC `97, Input

This input signal transmits the control information and digital audio output streams to be sent
to the DACs. The data is clocked into the CS4298 on the falling edge of BIT_CLK. A series
terminating resistor of 47

should be connected on this signal close to the device driving the

input.

SDATA_IN - AC-link Serial Data Output Stream from AC `97, Output

This output signal transmits the status information and digital audio input streams from the
ADCs. The data is clocked out of the CS4298 on the rising edge of BIT_CLK. A series
terminating resistor of 47

should be connected on this signal as close to the CS4298 as

possible.

XTL_IN - Crystal Input

This pin accepts either a crystal, with the other pin attached to XTL_OUT, or an external
CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except
when operating in BIT_CLK mode. The crystal frequency must be 24.576 MHz and designed
for fundamental mode, parallel resonance operation.

CS4298

DS315PP2

XTL_OUT - Crystal Output

This pin is used for a crystal placed between this pin and XLT_IN. If an external clock is used
on XTL_IN or the codec is in BIT_CLK mode, this pin must be left floating with no traces or
components connected to it.

ID1#, ID0# - Codec ID, Inputs

These pins select the codec ID and mode of operation for the CS4298. They are sampled after
the rising edge of RESET# and not used after. These inputs have internal 100 k

pull-ups and

should be left floating for a logic 0 or tied to analog ground for a logic 1. The pins utilize
inverted logic, so the condition of both pins floating sets the codec to primary mode while any
other combination sets the codec to a secondary mode. In primary mode, the codec is always
clocked from an external crystal or an external oscillator connected to the XTL_IN and/or
XTL_OUT pins with BIT_CLK as an output. In secondary mode, the clocking mechanism is
determined by the state of the BCM# pin with BIT_CLK always being an input.

BCM# - BIT_CLK Mode, Input

This pin selects the secondary mode clocking mechanism. BCM# is sampled after the rising
edge of RESET# and not used after. In codec secondary mode (ID1# and or ID0# grounded),
grounding this input will select BIT_CLK mode. In this mode, BIT_CLK is defined as an input
and all internal timing will be derived from the BIT_CLK signal and no connections should be
made to XTAL_IN and XTAL_OUT. When BCM# is floating, all timing will be derived from
the XTAL_IN pin. In this case, XTAL_IN must be syncronous to BIT_CLK. In primary mode,
BCM# must be left floating.

S/PDIF_OUT - Sony/Phillips Digital Interface, Output

This pin generates IEC 958 consumer compatible (S/PDIF) digital output from the CS4298
using output slots 6 and 9 when the SPDIF_EN bit in register 68h is set. For use with consumer
audio equipment, the output may be used to drive an RS422A compliant interface through an
isolation transformer, or a CP-1201 compliant interface through a TOSLINK module. When
S/PDIF_OUT is not being used this output is driven to a logic `0'.

GPIO[9:0] - General Purpose Input/Output

These GPIO pins are used to control modem DAAs and other discrete digital functions. When a
GPIO pin is configured as an input, it behaves as a Schmitt trigger input with 350 mV of
hysteresis at 5 V and 220 mV of hysteresis at 3.3 V. When a GPIO pin in configured as an
output, it may function as a normal CMOS output (4 mA drive) or as an open drain output.
GPIO pins power up in the high impedance state (tri-state).

CS4298

DS315PP2

8.2

Analog I/O Pins

MIC1 - Analog Mono Source, Input

This analog input is a monophonic source to the analog output mixer. It is intended to be used
as a desktop microphone connection to the audio subsystem. This input is MUX selectable to
the input mixer with the MIC2 input source. The maximum allowable input is 1 V

RMS

(sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is
100 mV

RMS

(sinusoidal). This input is internally biased at the Vrefout voltage reference and

requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to
analog ground.

MIC2 - Analog Mono Source, Input

This analog input is a monophonic source to the analog output mixer. It is intended to be used
as an alternate microphone connection to the audio subsystem. This input is MUX selectable to
the input mixer with the MIC1 input source. The maximum allowable input is 1 V

RMS

(sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is
100 mV

RMS

(sinusoidal).This input is internally biased at the Vrefout voltage reference and

requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to
analog ground.

LINE_IN_L and LINE_IN_R- Analog Line Source, Inputs

These inputs form a stereo input pair to the CS4298. The maximum allowable input is
1 V

RMS

(sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC

coupling to external circuitry is required. If these inputs are not used, they should both be
connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog
ground.

CD_L and CD_R - Analog CD Source, Inputs

These inputs form a stereo input pair to the CS4298. It is intended to be used for the Red Book
CD audio connection to the audio subsystem. The maximum allowable input is 1 V

RMS

(sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to
external circuitry is required. If these inputs are not used, they should both be connected to the
Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground.

CD_GND - Analog CD Common Source, Input

This analog input is used to remove common mode noise from Red Book CD audio signals.
The impedance on the input signal path should be one half the impedance on the CD_L and
CD_R input paths. This pin requires AC coupling to external circuitry. If this input is not used,
it should be connected to the Vrefout pin or AC coupled to analog ground.

CS4298

DS315PP2

VIDEO_L and VIDEO_R - Analog Video Audio Source, Inputs

These inputs form a stereo input pair to the CS4298. It is intended to be used for the audio
signal output of a video device. The maximum allowable input is 1 V

RMS

(sinusoidal). These

inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry
is required. If these inputs are not used, they should both be connected to the Vrefout pin or
both AC coupled, with separate AC coupling caps, to analog ground.

AUX_L and AUX_R - Analog Auxiliary Source, Inputs

These inputs form a stereo input pair to the CS4298. The maximum allowable input is 1 V

RMS

LINE_OUT_L and LINE_OUT_R - Analog Line Level Outputs

These signals are analog outputs from the stereo output mixer. The full scale output voltage for
output is nominally 1 V

RMS

and is internally biased at the Vrefout voltage reference. It is

required to either AC couple these pins to external circuitry or DC couple them to a buffer op-
amp biased at the Vrefout voltage. These pins need a 680 pF NPO capacitor attached to analog
ground.

ALT_LINE_OUT_L and ALT_LINE_OUT_R - Analog Alternate Line Level Outputs

These signals are analog outputs from the stereo output mixer. The full scale output voltage for
each output is nominally 1 V

RMS

and is internally biased at the Vrefout voltage reference. It is

required to either AC couple these pins to external circuitry or DC couple them to a buffer op-
amp biased at the Vrefout voltage. These pins need a 680 pF NPO capacitor attached to analog
ground.

8.3

Filter and Reference Pins

REFFLT - Internal Reference Voltage, Input

This is the voltage reference used internal to the part. A 0.1

F and a 1

F (must not be larger

than 1

F) capacitor with short, wide traces must be connected to this pin. No other

connections should be made to this pin.

Vrefout - Voltage Reference, Output

All analog inputs and outputs are centered around Vrefout which is nominally 2.2 Volts. This
pin may be used to level shift external circuitry, however any external loading should be
buffered.

AFLT1 - Left Channel Antialiasing Filter Input

This pin needs a 390 pF NPO capacitor attached to analog ground.

AFLT2 - Right Channel Antialiasing Filter Input

This pin needs a 390 pF NPO capacitor attached to analog ground.

CS4298

DS315PP2

FLTI - 3D Filter Input

A 1000 pF capacitor must be attached between this pin and FLTO if the 3D function is used.

FLTO - 3D Filter Output

A 1000 pF capacitor must be attached between this pin and FLTI if the 3D function is used.

FLT3D - 3D Filter

A 0.01

F capacitor must be attached from this pin to AGND if the 3D function is used.

8.4

Modem/Telephony

MRX+, MRX- - Modem Line Differential Receive, Inputs

This differential input receive pair connects to a 2- to 4-wire hybrid converter or an integrated
DAA and is used to sample the analog phone line signal. The maximum full scale differential
input is 3.0 Vp-p. These pins may be used in single ended fashion by connecting the input to
MRX+ and AC-grounding the MRX- pin, or by tying one of the two inputs to Vrefout to
provide DC-biasing.

HRX+, HRX- - Handset Differential Receive, Inputs

This differential input receive pair connects to a 2- to 4-wire hybrid converter and is used to
communicate with the local handset. These input pins may also be used to interface to a second
telephone line. The maximum full scale differential input is 3.0 Vp-p. These pins may be used
in single ended fashion by connecting the input to HRX+ and AC-grounding the HRX- pin, or
by tying one of the two inputs to Vrefout to provide DC-biasing.

MTX+, MTX- - Modem Line Differential Transmit, Outputs

This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an
integrated DAA and is used to transmit over the analog phone line. The maximum full scale
differential output is 5.6 Vp-p (MTX+ to MTX-). Each output pin is internally biased at the
Vrefout voltage. These pins may be used in single ended fashion by using one leg of the
differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms.

HTX+, HTX- - Handset Differential Transmit, Outputs

This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an
integrated DAA and is used to transmit over the analog phone line. The maximum full scale
differential output is 5.6 Vp-p (HTX+ to HTX-). Each output pin is internally biased at the
Vrefout voltage. These pins may be used in single ended fashion by using one leg of the
differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms.

CS4298

DS315PP2

Frequency Response (FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The
amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz
reference point. The listed minimum and maximum frequencies are guaranteed to be within the
Ac from minimum frequency to maximum frequency inclusive.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor,
in the presence of a signal, available at any instant in time (no change in gain settings between
measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by
the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over
a 20 Hz to 20 kHz bandwidth with units in dB FS.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the
noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with
units in dB.

S/PDIF

Sony/Phillips Digital Interface. This interface was established as a means of digitally
interconnecting consumer audio equipment. The documentation for S/PDIF has been
superseded by the IEC-958 consumer digital interface document.

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input
channel with 1 kHz, 0 dB, signal present on the other line input channel. Units in dB.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get an equal code on both channels. For the
DACs, the difference in output voltages for each channel when both channels are fed the same
code. Units in dB.

PATHS

A-D: Analog in, through the ADC, onto the serial link.

D-A: Serial interface inputs through the DAC to the analog output.

A-A: Analog in to Analog out (analog mixer).

10. REFERENCES

Intel, Audio Codec `97 Component Specification, Revision 2.1, May 22,1998.
http://developer.intel.com/pc-supp
/platform/ac97/

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