CDB5340

DS601DB1

TABLE OF CONTENTS

1. CDB5340 SYSTEM OVERVIEW .............................................................................................. 3
2. CS8406 DIGITAL AUDIO TRANSMITTER ............................................................................... 3
3. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 3
4. POWER SUPPLY CIRCUITRY ................................................................................................. 3
5. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3
6. ANALOG INPUT FILTER ......................................................................................................... 3

LIST OF FIGURES

Figure 1. System Block Diagram and Signal Flow .......................................................................... 5
Figure 2. Analog Audio Input........................................................................................................... 6
Figure 3. CS5340 ............................................................................................................................ 7
Figure 4. Level Shifters ................................................................................................................... 8
Figure 5. CS8406 Digital Audio Interface ........................................................................................ 9
Figure 6. Power Circuit.................................................................................................................. 10
Figure 7. Top Layer Silkscreen ..................................................................................................... 11
Figure 8. Top Layer ...................................................................................................................... 12
Figure 9. Bottom Layer................................................................................................................. 13

LIST OF TABLES

Table 1. System Connections ........................................................................................................ 4
Table 2. CDB5340 Jumper and Switch Settings ............................................................................ 4

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to

www.cirrus.com

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DS601DB1

CDB5340

1. CDB5340 SYSTEM OVERVIEW

The CDB5340 evaluation board is an excellent means of quickly evaluating the CS5340. The
CS8406 digital audio interface transmitter provides an easy interface to digital audio signal ana-
lyzers including the majority of digital audio test equipment.

The CDB5340 schematic has been partitioned into 5 schematics shown in

Figure 2

through

Figure 6

. Each partitioned schematic is represented in the system diagram shown in

Figure 1

Notice that the system diagram also includes the interconnections between the
partitioned schematics.

2. CS8406 DIGITAL AUDIO TRANSMITTER

The system generates and encodes standard S/PDIF data using a CS8406 Digital Audio Trans-
mitter (see

Figure 5

). The outputs of the CS8406 are RS422 compatible differential line drivers.

The CS8406 supports both Left Justified and I

S data formats, as determined by the DIP switch,

S2. A description of the CS8406 is included in the CS8406 datasheet.

3. INPUT/OUTPUT FOR CLOCKS AND DATA

The evaluation board has been designed to allow interfacing to external systems via the 10-pin
header, J11. The schematic for the clock/data input/output is shown in

Figure 4

The CDB5340 allows some flexibility as to the generation of the clocks. When the CS5340 and
CS8406 are in slave mode, the SCLK and LRCK must be provided via the header, J11. MCLK
can be generated from the on-board oscillator, Y1 or provided via the header, J11 as determined
by the DIP switch, S2. The on-board oscillator is socketed to allow other frequency oscillators to
be used. Please note that the on-board oscillator must be removed if an external MCLK is pro-
vided through header J11.

4. POWER SUPPLY CIRCUITRY

Power is supplied to the evaluation board by four binding posts (VA/VD, VL, GND, +5V),
see

Figure 6

. The VA/VD input supplies the VA and VD pins of the CS5340. VL supplies power

to the VL pin of the CS5340 and to the level shifter circuits. The +5V input supplies power to the
digital circuitry and the input amplifiers.

5. GROUNDING AND POWER SUPPLY DECOUPLING

The CS5340 requires careful attention to power supply and grounding arrangements to optimize
performance.

Figure 3

details the power distribution used on this board. The decoupling capac-

itors are located as close to the CS5340 as possible. Extensive use of ground plane fill in the
evaluation board yields large reductions in radiated noise.

6. ANALOG INPUT FILTER

The CDB5340 implements a single-ended analog input buffer, as shown in

Figure 2

. Note that

there is no attenuation or gain associated with the input buffer.

CDB5340

DS601DB1

* denotes default factory settings

CONNECTOR

INPUT/OUTPUT

SIGNAL PRESENT

VA/VD

Input

+3.3V to +5V power for the CS5340

Input

+2.5V to +5V power for the CS5340

GND

Input

Ground connection from power supply

+5V

Input

+ 5 Volt power

AINL

Input

Analog input left channel

AINR

Input

Analog input right channel

Optical Output

Output

Digital audio output

Coax Output

Output

Digital audio output

Table 1. System Connections

JUMPER/SWITCH

PURPOSE

POSITION

FUNCTION SELECTED

VA/VD Power Source

ADJ
*+3.3V
+5V

Power from the Binding Post (J1)
Power from the +3.3V Regulator
Power from the +5V Supply

VL Power Source

ADJ
*+3.3V
+5V

Power from the Binding Post (J2)
Power from the +3.3V Regulator
Power from the +5V Supply

J11

Input/Output for
clocks/data

Reset for the CDB5340

CDB5340 Configuration

M1/M0

Open
*Closed

Hi
Low

SCLK/LRCK Open

*Closed

Header J11 is an input for clocks.
Header J11 is an output for clocks.

MCLK

Open
*Closed

Header J11 is an input for MCLK.
Header J11 is an output for MCLK.

8406

Open
*Closed

CS8406 in Master mode
CS8406 in Slave mode

DIF

Open
*Closed

Digital interface format set to I

Digital interface format set to
Left Justified

Table 2. CDB5340 Jumper and Switch Settings

Электронный компонент: CDB5340

Document Outline