CP494
SWITCHMODE Pulse Width Modulation Control Circuit
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Fax:886-3-3521052
Page 1 of 11
Rev 1.0 Apr.19,2004
The CP494 is a fixed frequency, pulse width modulation control
circuit designed primarily for SWITCHMODE power supply control.
Complete Pulse Width Modulation Control Circuitry
OnChip Oscillator with Master or Slave Operation
OnChip Error Amplifiers
OnChip 5.0 V Reference
Adjustable Deadtime Control
Uncommitted Output Transistors Rated to 500 mA Source or Sink
Output Control for PushPull or SingleEnded Operation
Undervoltage Lockout
MAXIMUM RATINGS
(Full operating ambient temperature range applies,
unless otherwise noted.)
Rating
Symbol
Value
Unit
Power Supply Voltage
V
CC
42
V
Collector Output Voltage
V
C1
,
V
C2
42
V
Collector Output Current
(Each transistor) (Note 1)
I
C1
, I
C2
500
mA
Amplifier Input Voltage Range
V
IR
0.3 to +42
V
Power Dissipation @ T
A
45
C
P
D
1000
mW
Thermal Resistance,
JunctiontoAmbient
R
q
JA
80
C/W
Operating Junction Temperature
T
J
125
C
Storage Temperature Range
T
stg
55 to +125
C
Operating Ambient Temperature Range
T
A
0 to +70
C
Derating Ambient Temperature
T
A
45
C
1. Maximum thermal limits must be observed.
C
T
R
T
Ground
C1
1
Inv
Input
C2
Q2
E2
E1
1
0.1 V
Oscillator
V
CC
5.0 V
REF
(Top View)
Noninv
Input
Inv
Input
V
ref
Output
Contro
l
V
CC
Noninv
Input
Compen/PWN
Comp Input
Deadtime
Control
Error
Amp
+
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2 Error
Amp
+
-
Q1
PIN CONNECTIONS
CP494
SWITCHMODE Pulse Width Modulation Control Circuit
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Fax:886-3-3521052
Page 2 of 11
Rev 1.0 Apr.19,2004
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
V
CC
7.0
15
40
V
Collector Output Voltage
V
C1
, V
C2
30
40
V
Collector Output Current (Each transistor)
I
C1
, I
C2
200
mA
Amplified Input Voltage
V
in
0.3
V
CC
2.0
V
Current Into Feedback Terminal
l
fb
0.3
mA
Reference Output Current
l
ref
10
mA
Timing Resistor
R
T
1.8
30
500
k
W
Timing Capacitor
C
T
0.0047
0.001
10
m
F
Oscillator Frequency
f
osc
1.0
40
200
kHz
ELECTRICAL CHARACTERISTICS
(V
CC
= 15 V, C
T
= 0.01
m
F, R
T
= 12 k
W
, unless otherwise noted.)
For typical values T
A
= 25
C, for min/max values T
A
is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics
Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Voltage (I
O
= 1.0 mA)
V
ref
4.75
5.0
5.25
V
Line Regulation (V
CC
= 7.0 V to 40 V)
Reg
line
2.0
25
mV
Load Regulation (I
O
= 1.0 mA to 10 mA)
Reg
load
3.0
15
mV
Short Circuit Output Current (V
ref
= 0 V)
I
SC
15
35
75
mA
OUTPUT SECTION
Collector OffState Current
(V
CC
= 40 V, V
CE
= 40 V)
I
C(off)
2.0
100
m
A
Emitter OffState Current
V
CC
= 40 V, V
C
= 40 V, V
E
= 0 V)
I
E(off)
100
m
A
CollectorEmitter Saturation Voltage (Note 2)
CommonEmitter (V
E
= 0 V, I
C
= 200 mA)
EmitterFollower (V
C
= 15 V, I
E
= 200 mA)
V
sat(C)
V
sat(E)
1.1
1.5
1.3
2.5
V
Output Control Pin Current
Low State (V
OC
v
0.4 V)
High State (V
OC
= V
ref
)
I
OCL
I
OCH
10
0.2
3.5
m
A
mA
Output Voltage Rise Time
CommonEmitter (See Figure 12)
EmitterFollower (See Figure 13)
t
r
100
100
200
200
ns
Output Voltage Fall Time
CommonEmitter (See Figure 12)
EmitterFollower (See Figure 13)
t
f
25
40
100
100
ns
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
CP494
SWITCHMODE Pulse Width Modulation Control Circuit
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Fax:886-3-3521052
Page 3 of 11
Rev 1.0 Apr.19,2004
ELECTRICAL CHARACTERISTICS
(V
CC
= 15 V, C
T
= 0.01
m
F, R
T
= 12 k
W
, unless otherwise noted.)
For typical values T
A
= 25
C, for min/max values T
A
is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics
Symbol
Min
Typ
Max
Unit
ERROR AMPLIFIER SECTION
Input Offset Voltage (V
O (Pin 3)
= 2.5 V)
V
IO
2.0
10
mV
Input Offset Current (V
O (Pin 3)
= 2.5 V)
I
IO
5.0
250
nA
Input Bias Current (V
O (Pin 3)
= 2.5 V)
I
IB
0.1
1.0
m
A
Input Common Mode Voltage Range (V
CC
= 40 V, T
A
= 25
C)
V
ICR
0.3 to V
CC
2.0
V
Open Loop Voltage Gain (
D
V
O
= 3.0 V, V
O
= 0.5 V to 3.5 V, R
L
= 2.0 k
W
)
A
VOL
70
95
dB
UnityGain Crossover Frequency (V
O
= 0.5 V to 3.5 V, R
L
= 2.0 k
W
)
f
C
350
kHz
Phase Margin at UnityGain (V
O
= 0.5 V to 3.5 V, R
L
= 2.0 k
W
)
f
m
65
deg.
Common Mode Rejection Ratio (V
CC
= 40 V)
CMRR
65
90
dB
Power Supply Rejection Ratio (
D
V
CC
= 33 V, V
O
= 2.5 V, R
L
= 2.0 k
W
)
PSRR
100
dB
Output Sink Current (V
O (Pin 3)
= 0.7 V)
I
O
0.3
0.7
mA
Output Source Current (V
O (Pin 3)
= 3.5 V)
I
O
+
2.0
4.0
mA
PWM COMPARATOR SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Zero Duty Cycle)
V
TH
2.5
4.5
V
Input Sink Current (V
(Pin 3)
= 0.7 V)
I
I
0.3
0.7
mA
DEADTIME CONTROL SECTION (Test Circuit Figure 11)
Input Bias Current (Pin 4) (V
Pin 4
= 0 V to 5.25 V)
I
IB (DT)
2.0
10
m
A
Maximum Duty Cycle, Each Output, PushPull Mode
(V
Pin 4
= 0 V, C
T
= 0.01
m
F, R
T
= 12 k
W
)
(V
Pin 4
= 0 V, C
T
= 0.001
m
F, R
T
= 30 k
W
)
DC
max
45
48
45
50
50
%
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
V
th
0
2.8
3.3
V
OSCILLATOR SECTION
Frequency (C
T
= 0.001
m
F, R
T
= 30 k
W
)
f
osc
40
kHz
Standard Deviation of Frequency* (C
T
= 0.001
m
F, R
T
= 30 k
W
)
s
f
osc
3.0
%
Frequency Change with Voltage (V
CC
= 7.0 V to 40 V, T
A
= 25
C)
D
f
osc
(
D
V)
0.1
%
Frequency Change with Temperature (
D
T
A
= T
low
to T
high
)
(C
T
= 0.01
m
F, R
T
= 12 k
W
)
D
f
osc
(
D
T)
12
%
UNDERVOLTAGE LOCKOUT SECTION
TurnOn Threshold (V
CC
increasing, I
ref
= 1.0 mA)
V
th
5.5
6.43
7.0
V
TOTAL DEVICE
Standby Supply Current (Pin 6 at V
ref
, All other inputs and outputs open)
(V
CC
= 15 V)
(V
CC
= 40 V)
I
CC
5.5
7.0
10
15
mA
Average Supply Current
(C
T
= 0.01
m
F, R
T
= 12 k
W
, V
(Pin 4)
= 2.0 V)
(V
CC
= 15 V) (See Figure 12)
7.0
mA
* Standard deviation is a measure of the statistical distribution about the mean as derived from the formula,
s
N
n = 1
S
(X
n
X)
2
N 1
CP494
SWITCHMODE Pulse Width Modulation Control Circuit
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Fax:886-3-3521052
Page 4 of 11
Rev 1.0 Apr.19,2004
Figure 1. Representative Block Diagram
Figure 2. Timing Diagram
6
R
T
C
T
5
4
Deadtime
Control
Oscillator
0.12V
0.7V
0.7mA
+
1
-
-
+
-
+
+
2
-
D
Q
Ck
-
+
+
-
3.5V
4.9V
13
Reference
Regulator
Q1
Q2
8
9
11
10
12
V
CC
V
CC
1
2
3
15
16
14
7
Error Amp
1
Feedback PWM
Comparator Input
Ref.
Output
Gnd
UV
Lockout
Flip-
Flop
Output Control
Error Amp
2
Deadtime
Comparator
PWM
Comparator
Q
Capacitor C
T
Feedback/PWM Comp.
Deadtime Control
Flip-Flop
Clock Input
Flip-Flop
Q
Flip-Flop
Q
Output Q1
Emitter
Output Q2
Emitter
Output
Control
This device contains 46 active transistors.
CP494
SWITCHMODE Pulse Width Modulation Control Circuit
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Fax:886-3-3521052
Page 5 of 11
Rev 1.0 Apr.19,2004
APPLICATIONS INFORMATION
Description
The
CP494 is a fixedfrequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (See
Figure 1.) An internallinear sawtooth oscillator is
frequency programmable by two external components, R
T
and C
T
. The approximate oscillator frequency is determined
by:
f
osc
1.1
R
T
C
T
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor C
T
to either of two control signals. The NOR gates,
which drive output transistors Q1 and Q2, are enabled only
when the flipflop clockinput line is in its low state. This
happens only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in controlsignal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
The control signals are external inputs that can be fed into
the deadtime control, the error amplifier inputs, or the
feedback input. The deadtime control comparator has an
effective 120 mV input offset which limits the minimum
output deadtime to approximately the first 4% of the
sawtoothcycle time. This would result in a maximum duty
cycle on a given output of 96% with the output control
grounded, and 48% with it connected to the reference line.
Additional deadtime may be imposed on the output by
setting the deadtimecontrol input to a fixed voltage,
ranging between 0 V to 3.3 V.
Functional Table
Input/Output
Controls
Output Function
f
out
f
osc
=
Grounded
Singleended PWM @ Q1 and Q2
1.0
@ V
ref
Pushpull Operation
0.5
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent ontime, established by the deadtime
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
common mode input range from 0.3 V to (V
CC
2V), and
may be used to sense powersupply output voltage and
current. The erroramplifier outputs are active high and are
ORed together at the noninverting input of the pulsewidth
modulator comparator. With this configuration, the
amplifier
that demands minimum output on time, dominates
control of the loop.
When capacitor C
T
is discharged, a positive pulse is
generated on the output of the deadtime comparator, which
clocks the pulsesteering flipflop and inhibits the output
transistors, Q1 and Q2. With the outputcontrol connected
to the reference line, the pulsesteering flipflop directs the
modulated pulses to each of the two output transistors
alternately for pushpull operation. The output frequency is
equal to half that of the oscillator. Output drive can also be
taken from Q1 or Q2, when singleended operation with a
maximum ontime of less than 50% is required. This is
desirable when the output transformer has a ringback
winding with a catch diode used for snubbing. When higher
outputdrive currents are required for singleended
operation, Q1 and Q2 may be connected in parallel, and the
outputmode pin must be tied to ground to disable the
flipflop. The output frequency will now be equal to that of
the oscillator.
The
CP494 has an internal 5.0 V reference capable of
sourcing up to 10 mA of load current for external bias
circuits. The reference has an internal accuracy of
$5.0%
with a typical thermal drift of less than 50 mV over an
operating temperature range of 0
to 70
C.
Figure 3. Oscillator Frequency versus
Timing Resistance
500 k
100 k
10 k
1.0 k
500
1.0 k 2.0 k 5.0 k 10 k 20 k 50 k
100 k 200 k 500 k 1.0 M
R
T,
TIMING RESISTANCE (W)
, OSCILLA
T
OR FREQUENCY
(Hz)
f osc
V
CC
= 15 V
0.01 mF
0.1 mF
C
T
= 0.001 mF
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