1
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 00
15 Volt Digitally Programmable Potentiometer (DPPTM)
with 128 Taps and 2-wire Interface
CAT5132
FEATURES
s
Single linear Digitally Programmable Potentiometer
s
128 Resistor taps
s
End-to-end resistance of 10k
, 50k
& 100k
s
Potentiometer control and memory access via
2-wire interface (I
2
C-like)
s
Nonvolatile memory storage for wiper settings
s
Automatic recall of saved wiper setting at power up
s
Special increment/decrement instruction mode for
automatic trimming adjustments
s
V
CC
operation from 2.7 V to 5.5 V
s
V+ (Analog Voltage Supply) operation from +8 V to
+15V
s
Standby current less than 15
A
s
100 year nonvolatile memory data retention
s
10-pin MSOP package
s
Operating temperature of -40C to + 85C
APPLICATIONS
s
LCD screen adjustment
s
Volume control
s
Mechanical potentiometer replacement
s
Gain adjustment
s
Line impedance matching
s
VCOM setting adjustments
DESCRIPTION
The CAT5132 is a high voltage Digitally Programmable
Potentiometer (DPP) integrated with EEPROM memory
and control logic to operate in a similar manner as a
mechanical potentiometer. The DPP consists of a series
of resistive elements connected between two externally
accessible end points. The tap points between each
resistive element are connected to the wiper output with
CMOS switches. A separate 7-bit control register (WCR)
independently controls the wiper tap switches for the
DPP. Associated with the control register is a 7-bit
nonvolatile memory data register (DR) used for storing
wiper settings. Writing to the wiper control register or the
nonvolatile data register is via a 2-wire serial bus (I
2
C-
like).
On power-up, WCR is set to mid scale (1000000) and
after the Power Supply becomes stable, the contents of
the data register (DR) are transferred to the wiper control
register (WCR) and the wiper is positioned to that
location.
The CAT5132 comes with 2 voltage supply inputs: V
CC
,
the digital supply voltage input and V+, an analog supply
voltage input. These inputs allow the V+ to be as much
as 10 volts higher than the V
CC
and allow the DPP
terminal values to be as much as 15 volts above ground.
The CAT5132 can be used as a potentiometer or as a
two-terminal variable resistor. It is intended for circuit
level adjustments. It is supplied standard in the -40
C to
+85
C industrial operating temperature range and offered
in the 10-pin MSOP package.
SDA
SCL
A0
A1
VCC
CONTROL LOGIC AND
ADDRESS DECODE
128 TAP POSITION
DECODE CONTROL
7-BIT WIPER
CONTROL
REGISTER
(WCR)
7-BIT
NONVOLATILE
MEMORY
REGISTER
(DR)
V+
RH
127 RESISTIVE
ELEMENTS
RL
RW
127
0
BLOCK DIAGRAM
CAT5132
2
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PIN CONFIGURATION
SDA
GND
VCC
A1
A0
1
2
3
4
5
10
9
8
7
6
SCL
V+
RL
RW
RH
PIN DESCRIPTION
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MSOP 10-Pin Package
Package
Prefix
Device #
Suffix
5132
R
-10
TE13
Product
Number
Tape & Reel
2500 units/Reel
CAT
Resistance
Company ID
R: MSOP
Z: MSOP (Green with Sn Lead Finish)
GZ: MSOP (Green with NiPd Au Lead Finsh)
-10: 10k ohms
-50: 50k ohms
-100: 100k ohms
Notes:
1.
The device used in the above example is a CAT5132R-10TE13 (MSOP, 10k ohms, Tape & Reel).
2.
The Industrial Temperature range of -40C to +85C is standard on the above product.
ORDERING INFORMATION
CAT5132
3
Doc No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
RECOMMENDED OPERATING CONDITIONS
V
CC
= +2.7V to +5.5V
V+ = 8.0V to +15V
Operating Temperature Range: -40C to +85C
COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions outside of those listed
in the operational sections of this specification is not implied. Exposure to any
absolute maximum rating for extended periods may affect device performance
and reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias....................-55C to +125C
Storage Temperature ........................ -65C to +150C
Voltage on any SDA, SCL, A0 & A1 pins with respect
to Ground
(1)(2)
.............................. -2.0V to V
CC
+ 2.0V
Voltage on R
H
, R
L
& R
W
Pins with respect
to Ground .................................... -2.0V to "V+" + 1.0V
V
CC
with respect to Ground ................... -2.0V to 7.0V
V+ with respect to Ground ................... -2.0V to 16.0V
Wiper Current (10 sec) ...................................... +6mA
Lead Soldering temperature (10 sec) .............. +300C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
4. LSB = (R
HM -
R
LM
)/127; where R
HM
and R
LM
are the highest and lowest measured values on the wiper terminal.
5. n = 1, 2, ..., 127
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CAT5132
4
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
D.C. ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
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A.C. CHARACTERISTICS
Notes:
1.
This parameter is tested initially and after a design or process change that affects the parameter.
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CAT5132
5
Doc No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER UP TIMING
(1)(2)
l
o
b
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s
m
WRITE CYCLE LIMITS
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not
respond to its slave address.
RELIABILITY CHARACTERISTICS
Notes:
1.
This parameter is tested initially and after a design or process change that affects the parameter.
2.
t
PUR
and t
PUW
are the delays required from the time VCC is stable until the specified operation can be initiated.
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TYPICAL PERFORMANCE CHARACTERISTICS
Resistance between R
W
and R
L
0.000
2.000
4.000
6.000
8.000
10.000
12.000
0
16
32
48
64
80
96
112
128
Tap position
R
WL
(K
oh
m)
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=15V
Icc2 (NV write) vs Temperature
0
50
100
150
200
250
300
350
400
-50 -30 -10 10
30
50
70
90 110 130
Temperature (C)
I
cc2
(
u
A
)
Vcc = 2.7V
Vcc = 5.5V
CAT5132
6
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 2. Write Cycle Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing
TYPICAL PERFORMANCE CHARACTERISTICS (CONT)
Absolute Linearity Error per Tap Position
-1.000
-0.800
-0.600
-0.400
-0.200
0.000
0.200
0.400
0.600
0.800
1.000
0
16
32
48
64
80
96
112
128
Tap position
A
LIN
E
rro
r
(LS
B
)
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=15V
Tamb = 25 C
Rtotal = 10K
Relative Linearity Error
-0.500
-0.400
-0.300
-0.200
-0.100
0.000
0.100
0.200
0.300
0.400
0.500
0
16
32
48
64
80
96
112
128
Tap position
R
LI
N
Er
r
o
r
(
L
SB)
Vcc=2.7V; V+=8V
Vcc=5.5V; V+=15V
Tamb = 25 C
Rtotal = 10K
CAT5132
7
Doc No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 4. Acknowledge Condition
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock is high will be
interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically
a processor or controller, and the device being controlled
is the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the CAT5132 will be considered
a slave device in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5132 monitors the
SDA and SCL lines and will not respond until this
condition is met (see Fig. 3).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Fig. 3).
Figure 3. Start/Stop Condition
START CONDITION
SDA
STOP CONDITION
SCL
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data (see Fig. 4).
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge,
the CAT5132 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5132 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5132 is still busy with the write operation, no ACK
will be returned. If the CAT5132 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
CAT5132
8
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 5. Access Register Addressing Using 3 Bytes
Table 2. Byte 1 Slave Address and Instruction Byte
h
2
0
-
s
s
e
r
d
d
a
R
A
on
i
t
c
e
l
e
s
)
h
0
0
(
R
D
/
)
h
0
8
(
R
WC
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
P
S
1st byte
2nd byte
3rd byte
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
SP
Table 1. Access Control Register
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR of CAT5132 are accessed only by addressing the
volatile Access Register AR first, using the 3 byte I
2
C
interface for all read and write operations (see Table 1).
The first byte is the slave address/instruction byte (see
details below). The second byte contains the address
(02h) of the AR register. The data in the third byte
controls which register WCR (80h) or DR (00h) is being
addressed (see Figure 5).
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave/DPP Address Byte. The
most significant five bits of the slave address are a
device type identifier. These bits for the CAT5132 are
fixed at 01010 (refer to Table 2).
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A1 and A0 input pins
to successfully address the CAT5132. Only the device
with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to
reside on the same bus. The A1 and A0 inputs can be
actively driven by CMOS input signals or tied to V
CC
or
Ground.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a "1" a read command is
initiated and if it is a "0" a write is initiated. For the AR
register only write is allowed.
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
SLAVE
ADDRESS
& INSTRUCTION
S
A
C
K
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
C
K
FIXED
VARIABLE
AR REGISTER
ADDRESS
WCR/DR
SELECTION
r
e
i
f
i
t
n
e
d
I
e
p
y
T
e
c
i
v
e
D
s
s
e
r
d
d
A
e
v
a
l
S
/
d
a
e
R
e
ti
r
W
4
D
I
3
D
I
2
D
I
1
D
I
0
D
I
1
A
0
A
/
R
W
0
1
0
1
0
X
X
X
)
B
S
M
(
)
B
S
L
(
CAT5132
9
Doc No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along
its resistor array. The WCR is a volatile register and is
written with the contents of the nonvolatile Data Register
(DR) on power-up. The Wiper Control Register loses its
contents when the CAT5132 is powered-down. The
contents of the WCR may be read or changed directly by
the host using a READ/WRITE command after addressing
the WCR (see Table 1 to access WCR). Since the
CAT5132 will only make use of the 7 LSB bits (The first
data bit, or MSB, is ignored) on write instructions and will
always come back as a "0" on read commands.
X
X
X
X
X
X
X
A
X
A
h
2
0
-
s
s
e
r
d
d
a
R
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
P
S
1st byte
2nd byte
3rd byte
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
WCR(80h) selection
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
P
S
slave address byte
WCR address - 00h
data byte
STOP
ACK
ACK
START
ACK
1
1
1
A
1
A
h
2
0
-
s
s
e
r
d
d
a
R
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
1st byte
2nd byte
3rd byte
A
SP
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
WCR(80h) selection
T
S
0
1
0
1
1
0
0
0
A
0
0
0
0
0
0
0
0
SP
slave address byte
WCR address - 00h
increment (1) / decrement (0) bits
STOP
ACK
ACK
START
0
0
0
0
A
h
2
0
-
s
s
e
r
d
d
a
R
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
WCR(80h) selection
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
slave address byte
WCR address - 00h
ACK
START
T
S
0
1
0
1
0
0
0
1
A
0
X
X
X
X
X
X
X
slave address byte
data byte
START
SP
STOP
1st byte
2nd byte
3rd byte
A
SP
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written only to volatile registers, then the device enters its standby state.
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),
a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the
data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop
is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max positions.
A read operation (see Table 5) requires a Start condition, followed by a valid slave address byte for write, a valid address
byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132
responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation
by issuing a STOP condition following the last bit of Data byte.
Table 3. WCR Write Operation
Table 4. WCR Increment/Decrement Operation
Table 5. WCR Read Operation
CAT5132
10
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Data Register (DR)
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB
bit as a "0". Writing to the DR is performed in the same
fashion as the WCR except that a time delay of up to 5ms
is experienced while the nonvolatile store operation is
being performed. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state.
The WCR is also written during a write to DR. After a DR
WRITE is complete the DR and WCR will contain the
same wiper position.
X
X
X
X
X
X
X
A
X
A
h
2
0
-
s
s
e
r
d
d
a
R
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
P
S
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
DR(00h) selection
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
P
S
slave address byte
DR address - 00h
data byte
STOP
ACK
ACK
START
ACK
1st byte
2nd byte
3rd byte
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds
with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing
a STOP condition following the last bit of Data byte.
Table 6. DR Write Operation
Table 7. DR Read Operation
A
h
2
0
-
s
s
e
r
d
d
a
R
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
ACK
DR(00h) selection
T
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
slave address byte
DR address - 00h
ACK
START
T
S
0
1
0
1
0
0
0
1
A
0
X
X
X
X
X
X
X
slave address byte
data byte
START
SP
STOP
1st byte
2nd byte
3rd byte
A
SP
CAT5132
11
Doc No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POTENTIOMETER OPERATION
Power-On
The CAT5132 is a 128-position, digital controlled
potentiometer. At power-up the device turns on at the
mid-point wiper location (64) until the wiper register can
be loaded with the nonvolatile memory location previously
stored in the device. After the nonvolatile memory data
is loaded into the wiper register the wiper location will
change to the previously stored wiper position.
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the
total resistor. Each of these contact points is addressed
by the 7 bit wiper register which is decoded to select one
of these 128 contact points.
Each contact point generates a linear resistive value
between the 0 position and the 127 position. These
values can be determined by dividing the end-to-end
value of the potentiometer by 127. In the case of the
10k
potentiometer~79
is the resistance between
each wiper position. However in addition to the ~79
for
each resistive segment of the potentiometer, a wiper
resistance offset must be considered. Table 8 shows the
effect of this value and how it would appear on the wiper
terminal.
This offset will appear in each of the CAT5132 end-to-
end resistance values in the same way as the 10k
example. However resistance between each wiper
position for the 50k
version will be ~395
and for the
100k
version will be ~790
.
Table 8. Potentiometer Resistance and Wiper
Resistance Offset Effects
n
o
i
t
i
s
o
P
R
l
a
c
i
p
y
T
W
R
o
t
L
r
o
f
e
c
n
a
t
s
i
s
e
R
k
0
1
P
P
D
0
0
0
7
r
o
0
0
7
+
1
0
9
4
1
r
o
9
7
0
7
+
3
6
7
4
0
,
5
r
o
7
7
9
,
4
0
7
+
7
2
1
0
7
0
,
0
1
r
o
0
0
0
,
0
1
0
7
+
n
o
i
t
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s
o
P
R
l
a
c
i
p
y
T
W
R
o
t
H
r
o
f
e
c
n
a
t
s
i
s
e
R
k
0
1
P
P
D
0
0
0
7
0
,
0
1
r
o
0
0
0
,
0
1
0
7
+
4
6
7
4
0
,
5
r
o
7
7
9
,
4
0
7
+
6
2
1
9
4
1
r
o
9
7
0
7
+
7
2
1
0
7
r
o
0
0
7
+
CAT5132
12
Doc. No. 25092, Rev. 00
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PACKAGE OUTLINES
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Publication #:
25092
Revison:
00
Issue date:
09/12/05
REVISION HISTORY
Date
Rev.
Reason
09/12/2005
00
Initial Issue
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