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Электронный компонент: DDC114

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FEATURES
D
SINGLE-CHIP SOLUTION TO DIRECTLY
MEASURE FOUR LOW-LEVEL CURRENTS
D
HIGH PRECISION, TRUE INTEGRATING
FUNCTION
D
INTEGRAL LINEARITY:
0.01% of Reading
0.5ppm of FSR
D
VERY LOW NOISE: 5.2ppm of FSR
D
LOW POWER: 13.5mW/channel
D
ADJUSTABLE DATA RATE: Up to 3.125kSPS
D
PROGRAMMABLE FULL SCALE
D
DAISY-CHAINABLE SERIAL INTERFACE
APPLICATIONS
D
CT SCANNER DAS
D
PHOTODIODE SENSORS
D
INFRARED PYROMETER
D
LIQUID/GAS CHROMATOGRAPHY
Protected by US Patent #5841310
Dual
Switched
Integrator
Dual
Switched
Integrator
Modulator
Digital
Filter
Digital
Input/Output
FORMAT
DCLK
DCLK
DVALID
DOUT
DOUT
DIN
DIN
Control
IN3
IN1
VREF
DVDD
AVDD
DGND
AGND
Dual
Switched
Integrator
Dual
Switched
Integrator
Modulator
Digital
Filter
IN4
IN2
CLK
CONV
RANGE0
RANGE1
RANGE2
TEST
CLK_4X
HISPD/LOPWR
RESET
DESCRIPTION
The DDC114 is a 20-bit quad channel, current-input
analog-to-digital (A/D) converter. It combines both
current-to-voltage and A/D conversion so that four
low-level current output devices, such as photodiodes, can
be directly connected to its inputs and digitized.
For each of the four inputs, the DDC114 provides a
dual-switched integrator front-end. This allows for
continuous current integration: while one integrator is
being digitized by the onboard A/D converter, the other is
integrating the input current. Adjustable full-scale ranges
from 12pC to 350pC and adjustable integration times from
50
s to 1s allow currents from fAs to
As to be measured
with outstanding precision. Low-level linearity is
0.5ppm
of the full-scale range and noise is 5.2ppm of the full-scale
range.
Two modes of operation are provided. In Low-Power
mode, total power dissipation is only 13.5mW per channel
with a maximum data rate of 2.5kSPS. The High-Speed
mode supports data rates up to 3.125kSPS with a
corresponding dissipation of 18mW per channel.
The DDC114 has a serial interface designed for
daisy-chaining in multi-device systems. Simply connect
the output of one device to the input of the next to create
the chain. Common clocking feeds all the devices in the
chain so that the digital overhead in a multi-DDC114
system is minimal.
The DDC114 is a single-supply device using a +5V analog
supply and supporting a +2.7V to +5.25V digital supply.
Operating over the industrial temperature range of -40
C
to 85
C, the DDC114 is offered in a QFN-48 package.
DDC114
SBAS255A - JUNE 2004 - REVISED NOVEMBER 2004
Quad Current Input 20-Bit
ANALOG-TO-DIGITAL CONVERTER
www.ti.com
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
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DDC114
SBAS255A - JUNE 2004 - REVISED NOVEMBER 2004
www.ti.com
2
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information,
see the Package Option Addendum located at the end of
this data sheet.
ABSOLUTE MAXIMUM RATINGS
(1)
Analog Input Current
750
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD
-0.3V to +6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to AGND
-0.3V to +6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD to DGND
-0.3V to +6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND
0.2V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREF Input to AGND
2.0V to AVDD + 0.3V
. . . . . . . . . . . . . . . . . .
Analog Input to AGND
-0.3V to +0.7V
. . . . . . . . . . . . . . . . . . . . . . .
Digital Input Voltage to DGND
-0.3V to DVDD + 0.3V
. . . . . . . . . . .
Digital Output Voltage to DGND
-0.3V to AVDD + 0.3V
. . . . . . . . .
Operating Temperature
-40
C to +85
C
. . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature
-60
C to +150
C
. . . . . . . . . . . . . . . . . . . . . . . .
Junction Temperature (TJ)
+150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
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DDC114
SBAS255A - JUNE 2004 - REVISED NOVEMBER 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
At TA = +25
C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.
Low-Power Mode: TINT = 400
s and CLK = 4MHz; High-Speed Mode: TINT = 320
s and CLK = 4.8MHz.
Low-Power Mode
High-Speed Mode
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT RANGE
Range 0
10.2
12
13.8
(1)
pC
Range 1
47.5
50
52.5
pC
Range 2
95
100
105
pC
Range 3
142.5
150
157.5
pC
Range 4
190
200
210
pC
Range 5
237.5
250
262.5
pC
Range 6
285
300
315
pC
Range 7
332.5
350
367.5
pC
Negative Full-Scale Range
-0.4% of Positive Full-Scale Range
pC
Input Current
(2)
750
1
DYNAMIC CHARACTERISTICS
Data Rate
2.5
3.125
kSPS
Integration Time, T
INT
Continuous Mode
400
1,000,000
320
S
Integration Time, T
INT
Noncontinuous Mode, Range 1 to 7
50
S
System Clock Input (CLK)
CLK_4X = 0
4
4.8
MHz
CLK_4X = 1
16
19.2
MHz
Data Clock (DCLK)
16
MHz
ACCURACY
Noise, Low-Level Input
(3)
C
SENSOR
(4)
= 50pF, Range 5 (250pC)
5.2
6.5
5.5
7
ppm of
FSR
(5)
, rms
Integral Linearity Error
(6)
0.01% Reading
0.5ppm FSR, typ
Integral Linearity Error
(6)
0.025% Reading
1.0ppm FSR, max
Resolution
FORMAT = 1
20
Bits
Resolution
FORMAT = 0
16
Bits
Input Bias Current
0.1
10
pA
Range Error Match
(7)
All Ranges
0.1
0.5
% of FSR
Range Sensitivity to VREF
V
REF
= 4.096
0.1V
1:1
Offset Error
400
1000
ppm of FSR
Offset Error Match
(7)
100
ppm of FSR
DC Bias Voltage
(9)
0.05
2
mV
Power-Supply Rejection Ratio
at dc
25
200
ppm of FSR/V
Internal Test Signal
11
pC
Internal Test Accuracy
10
%
PERFORMANCE OVER TEMPERATURE
Offset Drift
0.5
3
(8)
ppm of
FSR/
C
Offset Drift Stability
0.2
1
(8)
ppm of FSR/
minute
DC Bias Voltage Drift
(9)
3
V/
C
Input Bias Current Drift
T
A
= +25
C to +45
C
0.01
1
(8)
pA/
C
Range Drift
(10)
25
ppm/
C
Range Drift Match
(7)
0.05
ppm/
C
REFERENCE
Voltage
4.000
4.096
4.200
V
Input Current
(11)
Average Value
75
95
A
(1)
indicates specification is the same as Low-Power Mode.
(2) Exceeding maximum input current specification may damage device.
(3) Input is less than 1% of full scale.
(4) CSENSOR is the capacitance seen at the DDC114 inputs from wiring, photodiode, etc.
(5) FSR is Full-Scale Range.
(6) A best-fit line is used in measuring nonlinearity.
(7) Matching between side A and side B of the same input.
(8) Ensured by design, not production tested.
(9) Voltage produced by the DDC114 at its input which is applied to the sensor.
(10)Range drift does not include external reference drift.
(11)Input reference current decreases with increasing TINT (see the Voltage Reference section, page 11).
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DDC114
SBAS255A - JUNE 2004 - REVISED NOVEMBER 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25
C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted.
Low-Power Mode: TINT = 400
s and CLK = 4MHz; High-Speed Mode: TINT = 320
s and CLK = 4.8MHz.
High-Speed Mode
Low-Power Mode
PARAMETER
UNITS
MAX
TYP
MIN
MAX
TYP
MIN
TEST CONDITIONS
DIGITAL INPUT/OUTPUT
Logic Levels
V
IH
0.8DVDD
DVDD + 0.1
V
V
IL
- 0.1
0.2DVDD
V
V
OH
I
OH
= -500
A
DVDD - 0.4
V
V
OL
I
OL
= 500
A
0.4
V
Input Current (I
IN
)
0 < V
IN
< DVDD
10
A
Data Format
(12)
Straight Binary
POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage (AVDD)
4.75
5.25
V
Digital Power-Supply Voltage (DVDD)
2.7
5.25
V
Supply Current
Total Analog Current
10.5
14.0
mA
Total Digital Current
DVDD = +3V
0.5
0.67
mA
Total Power Dissipation
DVDD = +3V
54
75
72
100
mW
Total Power Dissipation per Channel
DVDD = +3V
13.5
18.75
18
25
mW
(12)Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).
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DDC114
SBAS255A - JUNE 2004 - REVISED NOVEMBER 2004
www.ti.com
5
PIN CONFIGURATIONS
Top View
QFN
36
35
34
33
32
31
30
29
28
27
26
25
DIN
DIN
NC
NC
RESET
TEST
DGND
DGND
AGND
AVDD
AGND
AGND
DG
ND
DG
ND
CO
NV
DG
ND
DV
A
L
ID
DG
ND
CL
K
DG
ND
DCL
K
DCL
K
DG
ND
DV
DD
AG
N
D
AG
N
D
AI
N
4
AG
N
D
AI
N
3
AG
N
D
AG
N
D
AG
N
D
AI
N
2
AG
N
D
AI
N
1
AG
N
D
1
2
3
4
5
6
7
8
9
10
11
12
DOUT
DOUT
CLK_4X
FORMAT
HISPD/LOPWR
RANGE0
RANGE1
RANGE2
AGND
VREF
AGND
AGND
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DDC114
PIN DESCRIPTIONS
PIN
NUMBER
FUNCTION
DESCRIPTION
DOUT
1
Digital Output
Serial Data Output
DOUT
2
Digital Output
Serial Data Output: Complementary Signal
CLK_4X
3
Digital Input
Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4
FORMAT
4
Digital Input
Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits
HISPD/LOPWR
5
Digital Input
Mode Control: 0 = Low Power, 1 = High Speed
RANGE0
6
Digital Input
Range Control 0 (least significant bit)
RANGE1
7
Digital Input
Range Control 1
RANGE2
8
Digital Input
Range Control 2 (most significant bit)
AGND
9, 11-14, 16, 18-20,
22, 24-26, 28
Analog
Analog Ground
VREF
10
Analog Input
External Voltage Reference Input, 4.096V Nominal
AIN4
15
Analog Input
Analog Input 4
AIN3
17
Analog Input
Analog Input 3
AIN2
21
Analog Input
Analog Input 2
AIN1
23
Analog Input
Analog Input 1
AVDD
27
Analog
Analog Power Supply, 5V Nominal
DGND
29, 30, 38, 41, 43, 45,
47, 48
Digital
Digital Ground
TEST
31
Digital Input
Test Mode Control
RESET
32
Digital Input
Resets the Digital Circuitry, Active Low
NC
33, 34
--
No Connection
DIN
35
Digital Input
Serial Data Input: Complementary Signal (optional, see text on page 13)
DIN
36
Digital Input
Serial Data Input
DVDD
37
Digital
Digital Power Supply, 3V Nominal
DCLK
39
Digital Input
Serial Data Clock Input: Complementary Signal (optional, see text on page 13)
DCLK
40
Digital Input
Serial Data Clock Input
CLK
42
Digital Input
Master Clock Input
DVALID
44
Digital Output
Data Valid Output, Active Low
CONV
46
Digital Input
Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A

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