FEATURES
q
12-BIT RESOLUTION
q
500MHz UPDATE RATE
q
GUARANTEED SPURIOUS
PERFORMANCE
q
LOW GLITCH
q
FAST SETTLING
q
INTERNAL EDGE-TRIGGERED LATCH
q
LASER TRIMMED ACCURACY
q
INTERNAL REFERENCE
q
CLEAN LOW-NOISE OUTPUT
DAC650
FPO
70%
Ref
50
Offset
Trim
Reference
Output
ECL
LO IN
Reference
Adjust
12-Bit
ECL Lines
20mA
CLK
Edge Triggered Bit Latch
+10V
Reference
Input
50
V
OUT
V
OUT
ECL Logic
Threshold
Reference 1.3V
Tracking
ECL Logic
Threshold
Reference
V
BBOUT
V
BBEXT
V
BBIN
ECL
HI IN
CLK
DESCRIPTION
The DAC650 is a high performance 12-bit digital to
analog converter for high frequency waveform gen-
eration. It is complete with an internal low drift refer-
ence and edge-triggered data latch. The internal seg-
mentation and latching provide for minimal output
glitch energy.
The ECL compatibility provides for low digital noise
at high update rates. The 50
output resistance and
low output capacitance simplify transmission line de-
sign and filtering at the output. Complementary out-
puts are offered for increased performance while driv-
ing transformers or differential amplifiers.
The DAC650 combines precision thin film and bipolar
technology with high speed gallium arsenide to create
a high performance, cost effective solution for modern
waveform synthesis systems.
12-Bit 500MHz
DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
q
DIRECT DIGITAL SYNTHESIS
q
ARBITRARY WAVEFORM GENERATION
q
HIGH RESOLUTION GRAPHICS
q
COMMUNICATIONS LOCAL OSCILLATORS
Spread Spectrum
Base Stations
Digitally Tuned Receivers
q
HIGH-SPEED MODEMS
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1992 Burr-Brown Corporation
PDS-1130B
Printed in U.S.A. May, 1994
DAC650
2
SPECIFICATIONS
ELECTRICAL
Over full specified temperature range, using the internal +10V reference and rated supplies, unless otherwise noted.
DAC650JL
DAC650KL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TEMPERATURE RANGE
Specification: DAC650JL, KL
(1)
Ambient
0
+70
*
*
C
CA
27
*
C/W
JC
13
*
C/W
DIGITAL INPUTS
Logic
12 Parallel Input Lines
ECL Compatible
Resolution
12
*
Bits
ECL Logic Input Levels
(2)
: V
IL
Logic "0"
1.475
1.8
2
*
*
*
V
I
IL
1.0
10
*
*
A
V
IH
Logic "1"
1.115
0.8
0.6
*
*
*
V
I
IH
1.0
10
*
*
A
Logic Threshold Voltage
1.2
1.3
1.4
*
*
*
V
DIGITAL TIMING
Input Data Rate
DC
500
*
*
MHz
CLK Pulse Width Low
1.0
*
ns
Set-Up Time
2.0
1.8
*
*
ns
Hold Time (Referred to CLK)
500
600
*
*
ps
Propagation Delay
1.5
*
ns
ANALOG OUTPUT
Bipolar Output Current
R
L
= 0
20
*
mA
Bipolar Output Voltage
R
L
=
1.0
*
V
Output Resistance
V
OUT
, V
OUT
to Ground
49
50
51
*
*
*
Output Resistance Drift
50
*
ppm/
C
Output Capacitance
5
*
pF
TRANSFER CHARACTERISTICS
Integral Linearity Error
Best Fit Straight Line
0.018
0.036
0.012
0.024
%FSR
Differential Linearity Error
+25
C
0.018
0.036
0.08
0.024
%FSR
Over Temperature
0.018
0.036
0.012
0.024
%FSR
Monotonicity
Typical
Guaranteed
Bipolar Gain Error
Output Voltage, R
L
=
0.5
1.0
0.5
1.0
%FSR
Bipolar Offset Error
Output Voltage, R
L
=
0.5
1.0
0.25
0.5
%FSR
TIME DOMAIN PERFORMANCE
Glitch Energy
Major Carry
20
*
pV-s
Output Rise Time
10% to 90%
300
*
ps
Output Fall Time
90% to 10%
350
*
ps
Settling Time
(3)
:
0.1%FSR
Major Carry, 1LSB Change
2.0
*
ns
REFERENCES
V
BB
Input Range (Pin 1)
1.4
1.3
1.2
*
*
*
V
V
BB INT
Reference (Pin 68)
1.4
1.3
1.2
*
*
*
V
V
BB EXT
Tracking Reference (Pin 67) ECL
HI IN
= 0.8V, ECL
LO IN
= 1.8V
1.4
1.3
1.2
*
*
*
V
Internal
Reference
Voltage
(Ref
Out)
9.95
10
10.05
*
*
*
V
Ref in Resistance
4950
*
Ref in Operating Voltage Range
4.5
10.0
11.0
*
*
*
V
DYNAMIC PERFORMANCE
Spurious Free Dynamic Range
(4)
f
O
= 1MHz, f
CLK
= 100MHz
+25
C, Span = DC to f
CLK
/2
65
68
68
70
dBc
(5)
f
O
= 10MHz, f
CLK
= 100MHz
+25
C, Span = DC to f
CLK
/2
59
63
62
65
dBc
f
O
= 30MHz, f
CLK
= 200MHz
+25
C, Span = DC to f
CLK
/2
50
52
53
56
dBc
f
O
= 80MHz, f
CLK
= 200MHz
+25
C, Span = DC to f
CLK
/2
47
50
50
52
dBc
f
O
= 80MHz, f
CLK
= 500MHz
+25
C, Span = DC to 150MHz
49
55
52
58
dBc
f
O
= 100MHz, f
CLK
= 500MHz
+25
C, Span = 50MHz to 150MHz
51
56
54
59
dBc
Output Noise
Full Scale Sine Wave Output
1.0
*
V/ Hz
POWER SUPPLIES
Supply Voltages: +V
CC
Operating, T
MIN
to T
MAX
+14.25
+15
+15.75
*
*
*
V
V
CC
15.75
15
14.25
*
*
*
V
+V
DD1
+4.75
+5
+5.25
*
*
*
V
V
DD2
5.46
5.2
4.94
*
*
*
V
Power Supply Rejection
All Supplies,
5% Change
0.05
0.08
*
*
%/%
Supply Currents: +I
CC
Operating
10
13
*
*
mA
I
CC
47
50
*
*
mA
+I
DD1
53
57
*
*
mA
I
DD2
191
245
*
*
mA
Power Consumption
Operating
2.0
2.6
*
*
W
NOTE: (1) Extended temperature range devices are available, inquire. (2) V
BBIN
(Pin 1) connected to V
BB INT
(Pin 68). (3) Settling time is influenced by load due to
fast edge speeds. Use good transmission line techniques for best results. (4) Spurious Free Dynamic Range includes both harmonic and non-harmonic related spurs
in the bandwidth indicated. (5) dBc is "dB referred to the fundamental amplitude."
DAC650
3
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that this integrated circuit
be handled and stored using appropriate ESD protection
methods.
TEMPERATURE
MODEL
DESCRIPTION
RANGE (AMBIENT)
DAC650JL, KL
68-Pin Ceramic, Gullwing Leads
0
C to +70
C
ORDERING INFORMATION
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
DAC650JL, KL
68-Pin Ceramic Gullwing
256
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
V
CC
..................................................................................................
18V
Logic Input ......................................................................... +0.5V to 5.5V
Case Temperature .......................................................... 40
C to +125
C
Junction Temperature .................................................................... +150
C
Storage Temperature ...................................................... 55
C to +125
C
Lead Temperature (soldering, 10s) ................................................ +300
C
Stresses above these ratings may permanently damage the device.
ABSOLUTE MAXIMUM RATINGS
PIN DEFINITIONS
PIN NO
DESIGNATION
DESCRIPTION
1
V
BB
Sets Logic Threshold for Bits 1-12
2
Bit 1
MSB
3
Bit 2
4
Bit 3
5
Bit 4
6
Bit 5
7
Bit 6
8
Bit 7
9
Bit 8
10
Bit 9
11
Bit 10
12
Bit 11
13
Bit 12
LSB
14
V
EE
Logic Power (5.2V Nominal)
(1)
15
V
EE
16
CLK
Clock
17
CLK
NOT
Not Clock
18
DNC
Do Not Connect
19
V
EE
20
V
EE
21
V
EE
22
V
EE
23
V
EE
24
V
EE
25
V
EE
26
V
EE
27
DGND
Ground for Logic
28
DGND
29
DGND
30
DGND
31
DGND
32
DGND
33
DGND
34
DGND
PIN NO
DESIGNATION
DESCRIPTION
35
AGND
Ground for Analog Output Current
36
AGND
37
AGND
38
AGND
39
V
OUT
Complementary Output Voltage
40
V
OUT
41
V
OUT
42
AGND
43
AGND
44
AGND
45
V
OUT
Output Voltage
46
V
OUT
47
V
OUT
48
AGND
49
AGND
50
AGND
51
AGND
52
15V
15V Supply
53
15V
54
PWR GND
Ground for Analog Supplies
55
+5V
+5V Supply
56
+5V
+5V Supply
57
V
OS
ADJ
Offset Adjust
58
PWR GND
Ground for Analog Supplies
59
Ref
ADJ
Reference Out Adjust
60
Ref
OUT
Reference Out (+10V, Buffered)
61
Ref
IN
Reference In (4.950k
)
62
+15V
+15V Supply
63
PWR GND
Ground for Analog Supplies
64
5.2V Analog
Analog Power (5.2V Nominal)
(1)
65
ECL LO
IN
External ECL LOW input (optional)
66
ECL HI
IN
External ECL HI input (optional)
67
V
BBEXT
The buffered mean of LO
EXT
and HI
EXT
68
V
BBINT
Internally generated 1.3V reference
NOTE: (1) Both the 5.2V Logic and 5.2V analog pins should be powered from a common supply.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC650
4
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0
20
40
60
100
80
f
O
= 29.32MHz
f
CLK
= 200MHz
Amplitude = +3.1dBm
Resolution BW = 1.2kHz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
15
21
27
33
45
39
f
O
= 29.93MHz
f
CLK
= 200MHz
Amplitude = +3.13dBm
Resolution BW = 290Hz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0
10
20
30
50
40
f
O
= 9.96MHz
f
CLK
= 100MHz
Amplitude = +3.35dBm
Resolution BW = 580Hz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
5
7
9
11
15
13
f
O
= 9.98MHz
f
CLK
= 100MHz
Amplitude = +3.4dBm
Resolution BW = 580Hz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0
10
20
30
50
40
f
O
= 1.0MHz
f
CLK
= 100MHz
Amplitude = +3.58dBm
Resolution BW = 290Hz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0.5
0.7
0.9
1.1
1.5
1.3
f
O
= 1.0MHz
f
CLK
= 100MHz
Amplitude = +3.6dBm
Resolution BW = 150Hz
Amplitude (dBm)
TYPICAL PERFORMANCE CURVES
T
A
= +25
C unless otherwise noted.
DAC650
5
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
50
70
90
110
150
130
f
O
= 99.75MHz
f
CLK
= 500MHz
Amplitude = +2.7dBm
Resolution BW = 2.3kHz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0
20
40
60
100
80
f
O
= 79.27MHz
f
CLK
= 200MHz
Amplitude = +0.93dBm
Resolution BW = 9.1kHz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
50
60
70
80
100
90
f
O
= 79.88MHz
f
CLK
= 200MHz
Amplitude = +0.93dBm
Resolution BW = 1.2kHz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
0
30
60
90
150
120
f
O
= 79.92MHz
f
CLK
= 500MHz
Amplitude = +3.0dBm
Resolution BW = 4.6kHz
Amplitude (dBm)
OUTPUT SPECTRUM
Frequency (MHz)
+5
15
35
55
75
95
25
35
45
55
75
65
f
O
= 49.88MHz
f
CLK
= 500MHz
Amplitude = +3.3dBm
Resolution BW = 1.2kHz
Amplitude (dBm)
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C unless otherwise noted.
DAC650
6
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C unless otherwise noted.
SPURIOUS FREE DYNAMIC RANGE
vs CLOCK FREQUENCY
(Span = DC to f
CLK
/2)
80
70
60
50
40
0
100
200
300
400
500
Clock Frequency (MHz)
Spurious Free Dynamic Range (dBc)
f
OUT
= 10MHz
f
OUT
= 50MHz
f
OUT
= 1MHz
f
OUT
= 20MHz
SPURIOUS FREE DYNAMIC RANGE
vs CLOCK FREQUENCY
(Span = DC to 200MHz)
Clock Frequency (MHz)
Spurious Free Dynamic Range (dBc)
60
55
50
45
40
300
350
400
450
500
f
OUT
= 100MHz
f
OUT
= 125MHz
SPURIOUS FREE DYNAMIC RANGE
vs OUTPUT FREQUENCY
(Span = DC to 200MHz)
Output Frequency (MHz)
Spurious Free Dynamic Range (dBc)
0
20
40
60
80
100
120
140
80
70
60
50
40
f
CLK
= 400MHz
f
CLK
= 500MHz
SPURIOUS FREE DYNAMIC RANGE
vs OUTPUT FREQUENCY
(Span = DC to f
CLK
/2)
Output Frequency (MHz)
Spurious Free Dynamic Range (dBc)
0
20
40
60
80
100
120
140
80
70
60
50
40
f
CLK
= 100MHz
f
CLK
= 200MHz
f
CLK
= 300MHz
DAC650
7
TECHNOLOGY OVERVIEW
The DAC650 uses a unique design approach to achieve very
fast settling time and high resolution. This mixed-technol-
ogy design uses two active chips: one gallium arsenide and
the other silicon.
The GaAs MESFET die is used for those circuits which
determine speed. This includes the latches, data decoders,
and current switches. A silicon die with thin film is used for
those circuits which determine accuracy, such as the preci-
sion references and current sources. The precision R-2R
resistor ladders are laser trimmed to further increase the
accuracy of the DAC650. A block diagram of the DAC650
is shown in Figure 1.
THEORY OF OPERATION
The DAC650 employs a familiar architecture where input
bits switch on the appropriate current sources. Bits 1-3 are
decoded into 7 segments before the first set of latches. A
similar delay is given for the 9 least significant bits to
minimize data skew. The edge triggered master-slave latches
are driven by an internal clock buffer. This buffer placement
has matched the clock lines to each of the 32 latches, thus
minimizing output glitch energy.
There are 7 current sources for bits 1 to 3. Current sources
for bits 4-8 are scaled down in binary fashion. These current
sources are switched directly to the output of the R-2R
ladder. Bits 9-12 are fed to the laser trimmed R-2R ladder for
proper scale-down. The segmentation further minimizes
output glitch which can cause spectral degradation.
The output current sees 50
of output impedance from the
equivalent resistance of a R-2R ladder (100
) in parallel
with 100
(Figure 1). With all of the current sources off, the
output voltage is at +1V. With all current sources on
(40mA), the output voltage is at 1V. There is also a
complementary V
OUT
output that allows for a differential
output signals. The full scale complementary outputs (V
OUT
and V
OUT
) can be simply modeled as
20mA in parallel
with 50
. This gives an output swing of 1Vp-p with an
external 50
load.
REFERENCE/GAIN ADJUSTMENT
A precision +10V reference is included in the DAC650. A
50
resistor should be connected between REF
IN
and REF
OUT
for the specified unadjusted gain. This internal reference has
been laser trimmed to minimize offset and gain drift. Alter-
natively, an external reference may be used. Multiple DACs
may be run from one master reference by connecting a 50
resistor from each REF
IN
to the master REF
OUT
. A 100
potentiometer may be used in place of the 50
resistor in
order to provide a
1% gain adjustment range (Figure 2).
A wider adjustment range of
20% may be achieved by
connecting a 10k
potentiometer from REF
OUT
to ground,
with the wiper connected to the REF
ADJ
pin. Adjusting the
output to more than 40mA full scale may degrade high
frequency performance and reliability due to higher current
densities and operating temperature. Alternatively, lower
full scale currents will affect operation because there is less
current available to charge internal and external capaci-
tances.
It should be noted that the gain adjust techniques mentioned
above affect the current output and thus the voltage output
from the DAC650. The voltage output will also be affected
by an external load acting in parallel with the 50
output
impedance.
OFFSET ADJUST
The offset may be adjusted by connecting a potentiometer
between the +5V supply and ground with the wiper con-
nected to the offset adjust pin. The voltage on this pin with
no connection is about 2V, with an equivalent impedance of
1.6k
. A 10k
potentiometer will give the necessary ad-
justment range. The full scale range of the DAC output may
be offset so it is not symmetrical around zero, but the full
scale range must also be adjusted so that the output swing
does not exceed
1V. Connecting the offset adjust pin to
ground gives a unipolar output of 0 to 2V (with no load) or
0 to 1V (with a 50
load). This also reduces the current
requirements for the +5V supply by 20mA.
DIGITAL INPUTS, LOGIC THRESHOLDS,
and TERMINATION
The input logic levels and clock levels are ECL compatible.
The data inputs are single ended ECL and the clock input is
differential.
The internal impedance of the data and clock inputs is a high
impedance (FET gate), and is clamped to the digital supply
and ground to protect against ESD damage. ESD precau-
tions should still be used when handling the DAC650.
The inputs will most likely be driven by high-speed ECL
gate outputs. These outputs should be terminated using
standard high-speed transmission line techniques. Consult
an ECL handbook for proper methods of termination.
Termination resistors should not be connected to the analog
ground plane close to the DAC650. The fast changing digital
bit currents will cause noise in the analog ground plane
under this layout scheme. These fast changing digital cur-
rents should be steered away from the sensitive DAC650
analog ground plane. For speeds of up to 256MHz, series
termination with 47
resistors will be adequate
(Figure 3). This termination technique will greatly lessen the
issue of termination currents coupling into the analog ground
plane. Above 256MHz, parallel termination of the transmis-
sion line at the package pin may be required for clean digital
input.
The input data threshold level is set by connecting the
appropriate voltage (1.2V to 1.4V) to pin 1. The actual
level may be provided 3 ways:
(1) The user connects the DAC650's internal 1.3V thresh-
old reference directly to pin 1. This simple connection
provides excellent noise margins for ECL levels.
DAC650
8
FIGURE 1. Functional Block Diagram of the DAC650.
5V Ref
Current
Sources
Current
Switches
100
100
100
100
+2V
(Ladder
Equivalent
Resistance)
V
OUT
V
OUT
Switch Drivers
Latches
Latches
Receivers
ECL Logic
Threshold
Tracking
ECL Logic
Threshold
MSB
2
3
4
5
6
7
8
9
10
11
LSB
V
BBOUT
(1.3V)
V
BBEXT
(Mid-point
Out)
2k
8k
4.95k
3k
3k
3k
V
BB
+1V
+1V
Clock Buffer
ECL High In
ECL Low In
CLK
CLK
Ref
ADJUST
Ref
OUT
Ref
IN
Offset Adjust
FIGURE 2. Using a Potentiometer for
1% Gain Adjust.
DAC650
100
Ref
IN
61
Ref
OUT
60
FIGURE 3. Series Bit Termination.
5.2V
ECL Drive Gates
Recommended
Pull Down Resistor
DAC650
Bit
Input
47
DAC650
9
(2) An external V
BB
system reference is applied to pin 1.
This technique may allow data threshold levels to track
the system over supply and temperature variations.
(3) The internal tracking ECL threshold reference (pin 67) is
applied to pin 1. The output of the tracking ECL
threshold reference is simply the average of two exter-
nally applied levels. These levels are a system logic low
(pin 65) and system logic high (pin 66). This technique
may provide increased noise margin for systems with
levels slightly different from ECL. Leave pins 65-67
open if this option is not used.
TIMING
The DAC650 has an internal edge triggered latch. The
output changes on the positive edge of CLK. This master-
slave latching will assure that the 12 bits will arrive at the bit
switches with a minimum of data skew. Data must have
adequate setup and hold time for proper operation (refer to
Figure 4). Note that the Hold time is negative. Therefore the
data may change before the rising edge of clock and still be
valid.
The DAC650 has a differential ECL clock input. This clock
input can also be driven by a single-ended clock if desired
by tying the CLK input to an external voltage of 1.3V.
Using a true differential clock provides much improved
digital feedthrough immunity, however.
DATA IN/VOUT CORRESPONDENCE
The each full scale output of the DAC650 may be modeled
as either
20mA current source in parallel with 50
or a
1V voltage source in series with 50
. The nominal current
and voltage bit weights are given in Table I and the input
code vs output voltage relationships are given in Table II.
Transmission line techniques at the output are also recom-
mended to minimize ringing and glitching. Ideally, both of
the outputs should see the same termination, including any
delay between the DAC650 and the load.
Since the outputs V
OUT
and V
OUT
are equal in magnitude but
opposite in sign, they are ideal for driving RF
transformers (Figures 5). The primary may be connected
between the two outputs. The secondary may be floating or
referenced to ground. This results in a 2X signal power and
some cancellation of clock feedthrough, glitching, and
distortion. Figures 6 and 7 give recommended output
amplifiers.
FIGURE 4. Timing Diagram for the DAC650.
Clock 1
t
PWL
Data 1
V
OUT
1
t
P
CLK
Data
V
OUT
t
P
t
SU
t
H
t
PWL
Propagation delay. 50% of CLK to 50% of V
OUT
.
Setup time DATA must remain stable before CLK.
Hold time DATA must remain stable after CLK.
CLK pulse width low (50% to 50%).
SYMBOL
DESCRIPTION
MIN
1.5
1.8
600
TYP
MAX
ns
ns
ps
ns
UNITS
t
H
t
SU
2.0
500
1.0
Clock 0
Clock 2
Data 2
Data 0
DAC650
10
If only one output is used, the unused output should be
terminated identically. If the terminations cannot be identi-
cal and the unused output must be unterminated, the termi-
nation for the used output should be as close as possible to
the DAC650.
LAYOUT AND POWER SUPPLIES
A multilayer PC board with a solid ground and power planes
is recommended. An example of a typical circuit configura-
tion is given in Figures 8. The DAC650 has multiple ground
pins to minimize pin impedances. All of the ground pins
(analog and digital both) should be connected directly to the
analog ground plane at the DAC650.
Wide busses for the power paths are recommended as good
general practice. There are several internal power supply
bypass capacitors, but external bypassing is still recom-
mended. A 10
F tantalum capacitor in parallel with a
0.01
F chip capacitor will be sufficient in most applications.
Pin 64, Analog V
EE
, should be connected to the same supply
as the digital V
EE
pins (5.2V).
MAXIMIZING PERFORMANCE
The DAC650 has been designed to give a very clean analog
output with minimal noise, overshoot, and ringing. In addi-
tion to optimizing the layout and ground of the DAC650,
there are other important issues to consider when optimizing
the performance of this DAC in various AC applications.
The DAC650 includes an internal 50
output impedance to
simplify output interfacing to a 50
load. Because some
loads may be a complex impedance, care must be taken to
match the output impedance with the load. Mismatching of
impedances can cause reflections which will affect the
measured AC performance parameters such as settling time,
harmonic distortion, rise/fall times, etc. Often complex im-
pedances can be matched by placing a variable 3 to 10pF
capacitor at the output of the DAC to ground. Also, probing
the output can present a complex impedance.
The typical performance curves of Spurious Free Dynamic
Range vs various combinations of clock rate and/or input
frequency should give a general idea of the spectral perfor-
mance of the DAC under system specific clock and output
frequencies. We have defined Spurious Free Dynamic Range
as any harmonic or non-harmonic spurs in the indicated
bandwidth . In phase lock loop applications, the harmonics
often fall outside the loop bandwidth of the PLL. In these
cases, as well as cases where the output is filtered, Spurious
BIT
VOLTAGE (No External Load)
CURRENT
1
1V
20mA
2
.5V
10mA
3
0.25V
5mA
4
0.125V
2.5mA
5
62.5mV
1.25mA
6
31.25mV
625
A
7
15.625mV
312.5
A
8
7.8125mV
156.25
A
9
3.9063mV
78.125
A
10
1.9531mV
39.06
A
11
976
V
19.53
A
12 (LSB)
488
V
9.76
A
TABLE I. Nominal Bit Weight Values.
TABLE II. Input Code vs Output Voltage Relationships.
INPUT BITS OUTPUT VOLTAGES
1 2 3 4 5 6 7 8 9 10 11 12
V
OUT
NV
OUT
0 0 0 0 0 0 0 0 0
0
0
0
+1.000
1 + 488
V
0 0 0 0 0 0 0 0 0
0
0
1
+1 488
V
1 + 976
V
0 0 0 0 0 0 0 0 0
0
1
0
+1 976
V
1 + 1.464mV
0 1 0 0 0 0 0 0 0
0
0
0
0.50
0.50 + 488
V
1 0 0 0 0 0 0 0 0
0
0
0
0.000
+488
V
1 1 1 1 1 1 1 1 1
1
1
1
1 + 488
V
+1.000
FIGURE 5. Using an RF Transformer at the Output of the
DAC650. Filtering the Outputs Before the
Transformer Improves the Performance in Some
Applications.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
Load
Mini Circuits
TT5-1A
FIGURE 6. A High Speed Single Ended Amplifier at the
Output. The Gain is R
F
/50
.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
OPA64X
or
OPA600
FIGURE 7. A High Speed Differential Amplifier at the
Output.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
OPA64X
or
OPA600
R
F
DAC650
11
Free Dynamic Range will generally be much better due to
the harmonics falling outside the passband. Even with a
bandpass filter, updating the DAC at greater than 4 times per
cycle will (1) minimize the 2nd and 3rd harmonic magni-
tudes by having the output slew excessively between any
successive clock and (2) will keep the (f
CLK
2f
O
) spur and
other even order spurs from folding back close to the
fundamental under the condition f
OUT
= 1/3f
CLK
and (3) will
keep the (f
CLK
3f
O
) spur and other spurs from folding back
close to the fundamental under the condition f
OUT
= 1/4f
CLK
.
Making use of the high update rate of the DAC650 helps to
lessen the problems of harmonics "folding back" into the
passband.
EVALUATION BOARD
The high frequency signals used in operating the DAC650
can cause difficult layout problems. It is especially difficult
to build a high-performance prototype board using the
DAC650. It is recommended that an evaluation fixture be
used for prototyping. An evaluation fixture includes a
DAC650 soldered to the PC board. Both grades are available
for the evaluation fixture.
MODEL
DESCRIPTION
DEM-DAC650J-E
Evaluation Board with DAC650JL Attached
DEM-DAC650K-E
Evaluation Board with DAC650KL Attached
DEM-DAC650 PDS
Data Sheet for DAC650 Evaluation Board
ORDERING INFORMATION
FIGURE 8. Typical DAC650 Connection Diagram.
5.2V
+15V
V
BBIN
B
1
(MSB)
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
B
11
B
12
V
EE
V
EE
CLK
CLK
DNC
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
BBINT
V
BBEXT
ECL HI
IN
ECL LO
IN
V
EE
PWRGND
+15V
REF
IN
REF
OUT
REF
ADJ
REF
GND
VOS
ADJ
+5V
+5V
PWRGND
15V
15V
AGND
AGND
AGND
AGND
V
OUT
V
OUT
V
OUT
AGND
AGND
AGND
V
OUT
V
OUT
V
OUT
AGND
AGND
AGND
AGND
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
5.2V
C
11
0.01F
C
14
10F
+
C
4
10F
C
8
0.01F
15V
+
C
3
10F
C
7
0.01F +
+5V
C
1
10F
C
5
0.01F
+
C
2
10F
C
6
0.01F
+
CLK
CLK
C
9
0.01F
C
10
0.01F
5.2V
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
B
11
B
12
DAC650
DAC Out
DAC Out
(50
Optional)
NOTE: Clock and data inputs must be
terminated at source and/or package pin.
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