20k

10k

Logic

+V Out

REF

V B

OUT

V C

OUT

AGND

DGND

10V

Ref

DAC B

DAC C

DAC4815

20k

12 V D

OUT

DAC D

20k

V In

REF

BPO

V A

OUT

DAC A

10k

V Out

REF

8-Bit

Port and

Control In

DAC4815

Quad 12-Bit Digital-to-Analog Converter

(8-Bit Port Interface)

FEATURES

COMPLETE QUAD DAC --

INCLUDES INTERNAL REFERENCES AND
OUTPUT AMPLIFIERS

GUARANTEED SPECIFICATIONS

OVER TEMPERATURE

GUARANTEED MONOTONIC OVER

TEMPERATURE

HIGH-SPEED 8 + 4-BIT PARALLEL

INTERFACE

LOW POWER, 600mW (150mW/DAC)

LOW GAIN DRIFT, 5ppm/

LOW NONLINEARITY:

1/2 LSB max

BIPOLAR OUTPUT

CLEAR/RESET TO BIPOLAR ZERO

DESCRIPTION

The DAC4815 is one in a family of dual and quad
12-bit digital-to-analog converters (DACs). Serial,
8-bit, 12-bit interfaces are available.

The DAC4815 is complete. It contains CMOS logic,
switches, a high-performance buried-zener reference,
and low-noise bipolar output amplifiers. No external
components are required for bipolar

10V output

range.

The DAC4815 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each DAC. Then
both DACs are updated simultaneously. The DAC has
an asynchronous clear control for reset to bipolar zero.
This feature is useful for power-on reset or system
calibration. The DAC4815 is packaged in a 28-pin
plastic DIP rated for the 40

C to +85

C extended

industrial temperature range.

High-stability laser-trimmed thin film resistors assure
high reliability and true 12-bit integral and differential
linearity over the full specified temperature range.

International Airport Industrial Park · Mailing Address: PO Box 11400 · Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd. · Tucson, AZ 85706

Tel: (520) 746-1111 · Twx: 910-952-1111 · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

PDS-1112B

Printed in U.S.A. October, 1993

DAC4815

SPECIFICATIONS

, Guaranteed over T

= 40

C to +85

C unless otherwise specified.

ELECTRICAL

Specifications as shown for V

12V or

15V, V

= +5V, and R

= 2k

unless otherwise noted.

DAC4815AP

DAC4815BP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DIGITAL INPUTS
Resolution

Bits

(Input High Voltage)

(Input Low Voltage)

0.8

( Input Current)

= 25

= 40

C to +85

(Input Capacitance)

0.8

ACCURACY
Integral, Relative Linearity

(1)

1/2

LSB

Differential Nonlinearity

(2)

= 25

LSB

= 40

C to +85

1.5/1

LSB

Bipolar Zero Error

Gain Error

With Internal or External 10.0V Ref

0.2

0.15

Power Supply Sensitivity

(3)

11.4V to

18V

ppmFSR/V

= +4.5V to +5.5V

TEMPERATURE DRIFT
Gain Drift

ppm/

Bipolar Zero Drift

ppmFSR/

REFERENCE OUTPUT
Output Voltage

+9.980

+10

+10.020

+9.985

+10.015

Reference Drift

ppm/

Output Current

= 25

+10/5

= 40

C to +85

+5/5

Max Load Capacitance (For Stability)

500

Short Circuit Current

Load Regulation

ppm/mA

(

OUT

LOAD

)

Supply Regulation

ppm/V

(

OUT

)

REFERENCE OUTPUT, Inverter
10V Reference

10.020

9.980

10.015

9.985

10V Reference Drift

ppm/

DC Output Impedance

0.1

Output Current

Max Load Capacitance (For Stability)

200

Short Circuit Current

REFERENCE INPUT
Reference Input Resistance

1.75

2.5

Inverter Input Resistance

BPO Input Resistance

3.5

Reference Input Range

ANALOG SIGNAL OUTPUTS
Voltage Range

+ 1.4

1.4

DC Output Impedance

0.1

Output Current

Max Load Capacitance (For Stability)

OUT

500

Short Circuit Current

DYNAMIC PERFORMANCE

(4)

= 100pF

Settling Time

To 1/2 LSB of Full Scale

3.5

Slew Rate

Small-Signal Bandwidth

MHz

ANALOG GROUND CURRENT
(Code Dependent)

DIGITAL CROSSTALK

Full Scale Transition

nV-s

= 100pF

DIGITAL-TO-ANALOG
GLITCH IMPULSE

nV-s

POWER SUPPLY
+V

and V

11.4

4.5

5.5

+20

+24

25.5

Digital Inputs = 0V or +V

0.4

Digital Inputs = V

or V

Total Power, All DACs

600

753

DAC4815

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.

PACKAGE INFORMATION

PACKAGE DRAWING

MODEL

PACKAGE

NUMBER

(1)

DAC4815AP

28-Pin Plastic DIP

215

DAC4815BP

28-PIn Plastic DIP

215

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.

SPECIFICATIONS

(CONT), Guaranteed over T

= 40

C to +85

C unless otherwise specified.

ELECTRICAL

Specifications as shown for V

12V or

15V, V

= +5V, and R

= 2k

unless otherwise noted.

DAC4815AP

DAC4815BP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

TEMPERATURE RANGE
Specified

+85

Operating

+85

Thermal Resistance,

C/W

NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes effect of voltage output DAC, voltage references.
(4) Guaranteed but not tested.

PIN DESIGNATIONS

PIN

DESCRIPTOR

FUNCTION

PIN

DESCRIPTOR

FUNCTION

OUT

Analog output voltage, DAC B

Address line 2 input

OUT

Analog output voltage, DAC A

Address line 1 input

REF

Out

Negative reference voltage output (10V output)

Address line 0 input

REF

Reference voltage input

Data bit 7 input

REF

Out

Positive reference voltage output (+10V output)

Data bit 6 input

BPO

Bipolar offset input, DAC A, B, C, and D

Data bit 5 input

Negative analog power supply, 15V input

Data bit 4 input

Positive analog power supply, +15V input

Data bit 3 input

AGND

Analog common

Data bit 2 input

DGND

Digital common

Data bit 1 input

Positive logic power supply, +5V input

Data bit 0 input

OUT

Analog output voltage, DAC D

Latch data enable, DAC A, B, C, and D

OUT

Analog output voltage, DAC C

Chip select enable, DAC A, B, C, and D

CLR

Asynchronous input reset to zero

Write input, DAC A, B, C, and D

OUT

REF

Out

REF

Out

BPO

AGND

DGND

OUT

CLR

DAC4815

PIN CONFIGURATIONS

Top View

ORDERING INFORMATION

MODEL

124

2599

100+

DAC4815AP

$35.85

$28.45

$24.95

DAC4815BP

43.05

34.15

29.95

USA OEM PRICES

ORDERING INFORMATION

LINEARITY ERROR

MODEL

(LSB)

DAC4815AP

DAC4815BP

1/2

ABSOLUTE MAXIMUM RATINGS

to AGND ................................................................................. 0V, +7V

to DGND ................................................................................ 0V, +7V

to AGND .............................................................................. 0V, +18V

to AGND ............................................................................... 0V,18V

AGND to DGND ................................................................................

0.3V

Any digital input to GND ................................................. 0.3V, +V

+0.3V

Ref In to AGND ..................................................................................

25V

Ref In to DGND ..................................................................................

25V

Storage Temperature Range .......................................... 55

C to +125

Operating Temperature Range ......................................... 40

C to +85

Lead Temperature (soldering, 10s) ................................................ +300

Junction Temperature .................................................................... +155

Output Short Circuit ................................... Continuous to common or

Reference Short Circuit .............................. Continuous to common or +V

DAC4815

CROSSTALK (Bipolar Mode)

Time (500ns/div)

OUT

TYPICAL PERFORMANCE CURVES

= +25

C, V

12V or

15V, V

= +5V unless otherwise noted.

OUT

NOTE: Crosstalk is dominated by digital crosstalk/
feedthrough of LE signal.

OUT

+5V

PSRR vs FREQUENCY (Bipolar Mode)

PSRR (dB)

10k

100k

Frequency (Hz)

OUT

= +10V

OUT

= 0V

NOISE vs BANDWIDTH (Bipolar Mode)

250

200

150

100

Voltage Noise (µVrms)

100

10k

100k

Frequency (Hz)

OUT

= +10V

FFF

HEX

OUT

= 0V

800

HEX

CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR

vs TEMPERATURE

1.5E+00

1.0E+00

5.0E+00

0.0E+00

5.0E01

1.0E+00

1.5E+00

Bipolar Offset and Zero Error (mV)

+80

Temperature (°C)

1.5E02

1.0E02

5.0E03

0.0E+00

5.0E03

1.0E02

1.5E02

Gain Error (%)

100

Bipolar Offset

Gain Error

Bipolar Zero

POWER SUPPLY CURRENT vs TEMPERATURE

21.8

21.5

21.2

20.9

20.6

20.3

19.4

±I

(mA) Analog Supply

Temperature (°C)

(mA) Logic Supply

(All Logic Inputs = 2V)

(All Logic Inputs = 0V or V

)

OUTPUT VOLTAGE SWING vs RESISTOR LOAD

Load Resistance ( )

OUT

(Vp-p)

100

10k

= ±15V

= 5V

10V REF

DAC4815

FUNCTIONAL BLOCK DIAGRAM,

DAC4815 -- Quad 12-bit DAC, 8-bit Port

V Out

REF

10k

20k

V B

OUT

DAC B

BPO

V A

OUT

DAC A

12-Bit

Latch

12-Bit

Latch

Bits 0-11

CLR 14

DGND

AGND

Data In

V In

REF

+10V

Voltage

Reference

20k

13 V C

OUT

DAC C

Control

Logic

12-Bit

Latch

Bits 0-11

20k

12 V D

OUT

DAC D

12-Bit

Latch

Bits 0-11

WR 15

CS 16

LE 17

10k

8-Bit

Input

Bits 0 - 7

4-Bit

Input

Bits 8 -11

8-Bit

Input

Bits 0 - 7

4-Bit

Input

Bits 8 -11

8-Bit

Input

Bits 0 - 7

4-Bit

Input

Bits 8 -11

8-Bit

Input

Bits 0 - 7

4-Bit

Input

Bits 8 -11

+V Out

REF

DAC4815

PARAMETER

MINIMUM

--Address Valid to Write Setup Time

20ns

--Address Valid to Write Hold Time

10ns

--Data Setup Time

30ns

--Data Hold Time

10ns

--Chip Select to LE or Write

0ns

Setup Time
t

--Chip Select to LE or Write

0ns

Hold Time
t

--Write Pulse Width

40ns

--Clear Pulse Width

40ns

TIMING CHARACTERISTICS

= +5V, T

= 40

C to +85

NOTE: X = Don't care.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of

1 LSB maximum guarantees monotonicity.

BIPOLAR ZERO ERROR

The output voltage for code 800

HEX

GAIN ERROR

The deviation of the output voltage span (V

MAX

MIN

)

from the ideal span of 20V 1 LSB (bipolar mode). The gain
error is specified with and without the internal +10V refer-
ence error included.

OUTPUT SETTLING TIME

The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to

0.012% (1/2 LSB) is specified for the DAC4815.

DISCUSSION OF
SPECIFICATIONS

INPUT CODES

All digital inputs of the DAC4815 are TTL and 5V CMOS
compatible. Input codes for the DAC4815 are BOB (Bipolar
Offset Binary). See Figure 3 for

10V bipolar connection.

INTEGRAL OR RELATIVE LINEARITY

This term, also know as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.

BIPOLAR OUTPUTS FOR SELECTED INPUT

DIGITAL INPUT

BIPOLAR (BOB)

FFF

HEX

+Full Scale

800

HEX

Zero

7FF

HEX

Zero 1 LSB

000

HEX

Full Scale

LE, WR

CLR

5V
0V

NOTES: (1) All input signal rise and fall times are measured
from 10% to 90% of +5V. t = t = 5ns.

DATA

-A

(2) Timing measurement reference level is V + V .

INTERFACE LOGIC TRUTH TABLE

CLR

FUNCTION

DAC A LS input register loaded with D7-D0(LSB)

DAC A MS input register loaded with D3(MSB)-D0

DAC B LS input register loaded with D7-D0(LSB)

DAC B MS input register loaded with D3(MSB)-D0

DAC C LS input register loaded with D7-D0(LSB)

DAC C MS input register loaded with D3(MSB)-D0

DAC D LS input register loaded with D7-D0(LSB)

DAC D MS input register loaded with D3(MSB)-D0

All DAC registers updated simultaneously from input registers

All DAC registers are transparent

No data transfer

Input registers cleared = 000

HEX

, DAC registers = 800

HEX

DAC4815

D11

(MSB)

D10

(LSB)

AGND

OUT

REF

DIGITAL-TO-ANALOG GLITCH

Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.

DIGITAL CROSSTALK

Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC--see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nVs. See table of electrical specifications.

DIGITAL FEEDTHROUGH

Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs--see Typical Performance
Curves.

OPERATION

Depending on the address selected, the 4 MSBs or the 8
LSBs are written into the appropriate input register for each
DAC when the WR signal is brought low. The data are
latched in the input register when the WR goes high. Data
are then transferred from the input registers to the DAC latch
registers by bringing LE low. The data are latched in the
DAC latch registers when LE goes high. All DACs are
updated simultaneously.

When CLR is brought low, the input registers are cleared to
000

HEX

while the DAC registers = 800

HEX

. If LE is brought

low after CLR the DACs are updated with 000

HEX

resulting

in 10V (bipolar) or OV (unipolar) on the output.

CIRCUIT DESCRIPTION

Each of the four DACs in the DAC4815 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a 10V reference
are shared by all DACs.

Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V

REF

Current from the ladder is switched either to I

OUT

or AGND

by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
digital input code. This makes the resistance at V

REF

con-

stant (it can be driven by either a voltage or current refer-
ence). The reference can be either positive or negative
polarity with a range of up to

10V.

CMOS switches included in series with the ladder terminat-
ing resistor and the feedback resistor, R

, compensate for

the temperature drift of the ladder switch ON resistance.

The output op amps are connected as transimpedance ampli-
fiers to convert the DAC-cell output current into an output
voltage. They have been specially designed and compen-
sated for precision and fast settling in this application.

POWER SUPPLY CONNECTIONS

The DAC4815 is specified for operation with power sup-
plies of V

= +5V and V

= either

12V or

15V. Even with

the V

supplies at

11.4V the DACs can swing a full

10V.

Power supply decoupling capacitors (1

F tantalum) should

be located close to the DAC power supply connections.

Separate digital and analog ground pins are provided to
permit separate current returns. They should be connected
together at one point. Proper layout of the two current
returns will prevent digital logic switching currents from
degrading the analog output signal. The analog ground
current is code dependent so the impedance to the system
reference ground must be kept to a minimum. Connect
DACs as shown in Figure 2 or use a ground plane to keep
ground impedance less than 0.1

for less than 0.1LSB error.

10V OUTPUT RANGE CONNECTION

For a

10V bipolar output connect the DAC4815 as shown

in Figure 3.

CONNECTION TO DIGITAL BUS

DAC4815s can easily be connected to a

processor bus.

Decode your address lines to derive the control signals
shown in Figure 4. Only one LATCH signal is required for
a system where all DAC4815s are updated simultaneously.
If your want to update DAC4815s independently, use sepa-
rate LATCH signals. The LATCH and WRITE signals can
be brought low simultaneously to update the DAC registers
with the same processor instruction that writes the final 8-bit
data word the DAC input registers.

FIGURE 1. Simplified Circuit Diagram of DAC Cell.

DAC4815

20k

10k

V A

OUT

V D

OUT

10V

Ref

DAC A

DAC D

DAC4815

15V

1µF

+15V

1µF

+5V

20k

V C

OUT

DAC C

20k

V B

OUT

DAC B

DGND

AGND

10k

8-Bit

Port and

Control In

FIGURE 3. Analog Connections for

10V DAC Output.

FIGURE 4. Logic Connections for Multiple DAC4815
Packages.

Data In

18-25

Data

WRITE 1

DAC4815

WRITE 2

Data In

18-25

DAC4815

LATCH

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

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