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Электронный компонент: ADS2807

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ADS2807
Dual, 12-Bit, 50MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
HIGH SNR: 66dB (2Vp-p), 68dB (3Vp-p)
q
LOW POWER: 720mW
q
INTERNAL OR EXTERNAL REFERENCE
q
LOW DLE: 0.6LSB
q
FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
q
TQFP-64 POWER PACKAGE
APPLICATIONS
q
COMMUNICATIONS IF PROCESSING
q
COMMUNICATIONS BASESTATIONS
q
TEST EQUIPMENT
q
MEDICAL IMAGING
q
VIDEO DIGITIZING
q
CCD DIGITIZING
Optional External
Reference
12-Bit
Pipelined
ADC
Error
Correction
Logic
Timing
Circuitry
Internal
Reference
3-State
Outputs
T&H
D12A
D1A
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Outputs
T&H
D12B
D1B
IN
A
CM
A
+V
S
OE
A
OVR
A
OVR
B
IN
A
INT/EXT
CLK
FS
SEL
(Opt.)
IN
B
V
IN
CM
B
OE
B
IN
B
(Opt.)
ADS2807
V
IN
DESCRIPTION
The ADS2807 is a dual, high-speed, high dynamic range,
12-bit pipelined Analog-to-Digital Converter (ADC). This
converter includes a high-bandwidth track-and-hold that
gives excellent spurious performance up to and beyond the
Nyquist rate. The differential nature of this track-and-hold
and ADC circuitry minimizes even-order harmonics and
gives excellent common-mode noise immunity. The track-
and-hold can also be operated single-ended.
The ADS2807 provides for setting the full-scale range of the
converter without any external reference circuitry. The inter-
nal reference can be disabled allowing low-drive, external
references to be used for improved tracking in multichannel
systems.
The ADS2807 provides an over-range indicator flag to
indicate an input signal that exceeds the full-scale input
range of the converter. This flag can be used to reduce the
gain of front-end gain control circuitry. There is also an
output enable pin to allow for multiplexing and testability on
a PC board.
The ADS2807 employs digital error correction techniques to
provide excellent differential linearity for demanding imag-
ing applications. The ADS2807 is available in a TQFP-64
power package.
ADS2807
SBAS169B NOVEMBER 2000 REVISED MAY 2002
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS2807
2
SBAS169B
www.ti.com
ELECTRICAL CHARACTERISTICS
At T
A
= full specified temperature range, V
S
= +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted.
ADS2807Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12 Tested
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
40
+85
C
ANALOG INPUT
2V Full-Scale Input Range (Differential)
2Vp-p, INT or EXT Ref
2
3
V
2V Full-Scale Input Range (Single-Ended)
2Vp-p, INT or EXT Ref
1.5
3.5
V
3V Full-Scale Input Range (Differential)
3Vp-p, INT or EXT Ref
1.75
3.25
V
3V Full-Scale Input Range (Single-Ended)
3Vp-p, INT or EXT Ref
1
4
V
Analog Input Bias Current
1
A
Analog Input Bandwidth
270
MHz
Input Impedance
1.25 || 3
M
|| pF
CONVERSION CHARACTERISTICS
Sample Rate
10k
50M
Samples/s
Data Latency
6
Clock Cycles
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
0.6
1.0
LSB
f = 10MHz
f
S
= 40MHz
0.6
1.0
LSB
No Missing Codes
f
S
= 50MHz,T
A
= +25
C
Tested
f
S
= 40MHz, Full Temp
Tested
Integral Linearity Error, f = 1MHz
T
A
= +25
C
3.5
5.0
LSBs
Spurious-Free Dynamic Range
(1)
f = 1MHz (1dBFS input)
72
dBFS
(2)
f = 10MHz (1dBFS input)
60
70
dBFS
f = 20MHz (1dBFS input)
70
dBFS
2-Tone Intermodulation Distortion
(3)
f = 12MHz and 13MHz (7dBFS each tone)
71.8
dBc
Signal-to-Noise Ratio (SNR)
f = 1MHz (1dBFS input)
66
dBFS
f = 10MHz (1dBFS input)
60
65
dBFS
f = 20MHz (1dBFS input)
65
dBFS
f = 1MHz (1dBFS input)
3Vp-p
68
dBFS
f = 10MHz (1dBFS input)
3Vp-p
68
dBFS
+V
S
....................................................................................................... +6V
Analog Input ........................................................... (0.3V) to (+V
S
+ 0.3V)
Logic Input ............................................................. (0.3V) to (+V
S
+ 0.3V)
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +150
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS2807Y
TQFP-64
PAP
40
C to +85
C
ADS2807Y
ADS2807Y/1K5
Tape and Reel, 1500
"
"
"
"
"
ADS2807Y/250
Tape and Reel, 250
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
ADS2807
3
SBAS169B
www.ti.com
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= full specified temperature range, V
S
= +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted.
ADS2807Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS (Cont.)
Signal-to-(Noise + Distortion) (SINAD)
(4)
f = 1MHz (1dBFS input)
65
dBFS
f = 10MHz (1dBFS input)
57
64
dBFS
f = 20MHz (1dBFS input)
64
dBFS
f = 1MHz (1dBFS input)
3Vp-p
68
dBFS
f = 10MHz (1dBFS Input)
3Vp-p
68
dBFS
Channel-to-Channel Crosstalk
2Vp-p
85
dBFS
Output Noise
Input Grounded
0.2
LSBs rms
Aperture Delay Time
2
ns
Aperture Jitter
1.2
ps rms
Overvoltage Recovery Time
2
ns
DIGITAL INPUTS
Logic Family
+3V/+5V CMOS Compatible
Convert Command
Start Conversion
Rising Edge of Convert Clock
High Level Input Current
(5)
(V
IN
= 5V)
+50
A
Low Level Input Current (V
IN
= 0V)
+10
A
High Level Input Voltage
+2.4
V
Low Level Input Voltage
+1.0
V
Input Capacitance
5
pF
DIGITAL OUTPUTS
Logic Family
CMOS
Logic Coding
Straight Offset Binary
Low Output Voltage (I
OL
= 50
A)
VDRV = 5V
+0.1
V
Low Output Voltage, (I
OL
= 1.6mA)
VDRV = 5V
+0.2
V
High Output Voltage, (I
OH
= 50
A)
VDRV = 5V
+4.9
V
High Output Voltage, (I
OH
= 0.5mA)
VDRV = 5V
+4.8
V
Low Output Voltage, (I
OL
= 50
A)
VDRV = 3V
+0.4
V
High Output Voltage, (I
OH
= 50
A)
VDRV = 3V
+2.4
V
3-State Enable Time
OE = L
(5)
20
40
ns
3-State Disable Time
OE = H
(5)
2
10
ns
Output Capacitance
5
pF
ACCURACY (Internal Reference, 2Vp-p,
Unless Otherwise Noted)
Zero Error (Midscale)
at 25
C
1.0
%FS
Zero Error Drift (Midscale)
16
ppm/
C
Gain Error
(6)
at 25
C
1.5
%FS
Gain Error Drift
(6)
66
ppm/
C
Gain Error
(7)
at 25
C
1.0
%FS
Gain Error Drift
(7)
23
ppm/
C
Power-Supply Rejection of Gain
V
S
=
5%
70
dB
REFT Tolerance
2V Full-Scale
Deviation From Ideal 3.0V
10
65
mV
3V Full-Scale
Deviation From Ideal 3.25V
20
mV
REFB Tolerance
2V Full-Scale
Deviation From Ideal 2.0V
10
65
mV
3V Full-Scale
Deviation From Ideal 1.75V
20
mV
External REFT Voltage Range
REFB + 0.4
3
V
S
1.70
V
External REFB Voltage Range
1.70
2
REFT 0.4
V
Reference Input Resistance
375
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Operating
+4.75
+5.0
+5.25
V
Supply Current: +I
S
Operating
134
mA
Power Dissipation: VDRV = 5V
External Reference
720
mW
VDRV = 3V
External Reference
700
mW
VDRV = 5V
Internal Reference
740
mW
VDRV = 3V
Internal Reference
720
760
mW
Thermal Resistance,
JA
TQFP-64
21.5
C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.
(4) Effective number of bits (ENOB) is defined by as (SINAD 1.76) /6.02. (5) A 50k
pull-down resistor is inserted internally on OE pins. (6) Includes internal
reference. (7) Excludes internal reference.
ADS2807
4
SBAS169B
www.ti.com
PIN CONFIGURATION
Top View
TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
GND
+V
S
SEL
GND
+V
S
OE
A
GND
VDRV
A
OVR
A
A1 (MSB)
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
GND
+V
S
GND
+V
S
OE
B
GND
VDRV
B
OVR
B
B12 (LSB)
B11
B10
B9
B8
B7
B6
GND
IN
B
IN
B
CM
B
REFT
B
REFB
B
GND
+V
S
INT/EXT
GND
REFB
A
REFT
A
CM
A
IN
A
IN
A
GND
B5
B4
B3
B2
B1(MSB)
DV
B
GND
CLK
GND
DV
A
A12 (LSB)
A11
A10
A9
A8
A7
64
63
62
61
60
59
58
57
56
55
54
17
18
19
20
21
22
23
24
25
26
27
53
52
51
50
49
28
29
30
31
32
ADS2807Y
TIMING DIAGRAM
6 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N 6
N 5
N 4
N 3
N 2
N 1
N
N + 1
Data Out
Data Valid
Clock
Analog In
N
t
2
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
t
1
t
3
t
4
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
CONV
Convert Clock Period
20
100
s
ns
t
L
Clock Pulse LOW
9.0
t
CONV
/2
ns
t
H
Clock Pulse HIGH
9.0
t
CONV
/2
ns
t
D
Aperture Delay
2
ns
t
1
(1)
Data Hold Time, C
L
= 0pF
2.7
ns
t
2
(1)
New Data Delay Time, C
L
= 15pF max
8.2
12
ns
t
3
Data Valid Falling Edge Delay, C
L
= 15pF max
7.5
ns
t
4
Data Valid Rising Edge Delay, C
L
= 15pF max
5.6
ns
NOTE: (1) t
1
and t
2
times are valid for VDRV voltages of +2.7V to +5V.
ADS2807
5
SBAS169B
www.ti.com
PIN
I/O
DESIGNATOR
DESCRIPTION
1
GND
Ground
2
GND
Ground
3
+V
S
+5V Supply
4
GND
Ground
5
+V
S
+5V Supply
6
I
OE
B
Output Enable, Channel B
7
GND
GND
8
VDRV
B
Logic Driver Supply Voltage, Channel B
9
O
OVR
B
Over-Range Indicator, Channel B
10
O
B12 (LSB)
Data Bit 12 (D0), Channel B
11
O
B11
Data Bit 11 (D1), Channel B
12
O
B10
Data Bit 10 (D2), Channel B
13
O
B9
Data Bit 9 (D3), Channel B
14
O
B8
Data Bit 8 (D4), Channel B
15
O
B7
Data Bit 7 (D5), Channel B
16
O
B6
Data Bit 6 (D6), Channel B
17
O
B5
Data Bit 5 (D7), Channel B
18
O
B4
Data Bit 4 (D8), Channel B
19
O
B3
Data Bit 3 (D9), Channel B
20
O
B2
Data Bit 2 (D10), Channel B
21
O
B1 (MSB)
Data Bit 1 (D11), Channel B
22
O
DV
B
Data Valid, Channel B
23
GND
Ground
24
I
CLK
Clock
25
GND
Ground
26
O
DV
A
Data Valid, Channel A
27
O
A12 (LSB)
Data Bit 12 (D0), Channel A
28
O
A11
Data Bit 11 (D1), Channel A
29
O
A10
Data Bit 10 (D2), Channel A
30
O
A9
Data Bit 9 (D3), Channel A
31
O
A8
Data Bit 8 (D4), Channel A
32
O
A7
Data Bit 7 (D5), Channel A
33
O
A6
Data Bit 6 (D6), Channel A
PIN DESCRIPTIONS
PIN
I/O
DESIGNATOR
DESCRIPTION
34
O
A5
Data Bit 5 (D7), Channel A
35
O
A4
Data Bit 4 (D8), Channel A
36
O
A3
Data Bit 3 (D9), Channel A
37
O
A2
Data Bit 2 (D10), Channel A
38
O
A1 (MSB)
Data Bit 1 (D11), Channel A
39
O
OVR
A
Over-Range Indicator, Channel A
40
VDRV
A
Logic Driver Supply Voltage, Channel A
41
GND
Ground
42
I
OE
A
Output Enable, Channel A
43
+V
S
+5V Supply
44
GND
Ground
45
I
SEL
Input Range Select: HIGH = 3V, LOW = 2V
46
+V
S
+5V Supply
47
GND
Ground
48
GND
Ground
49
GND
Ground
50
I
IN
A
Analog Input, Channel A
51
I
IN
A
Complementary Analog Input, Channel A
52
O
CM
A
Common-Mode, Channel A
53
I/O
REFT
A
Top Reference/Bypass, Channel A
54
I/O
REFB
A
Bottom Reference/Bypass, Channel A
55
GND
Ground
56
I
INT/EXT
Reference Select: HIGH = External,
LOW = Internal 50k
Pull-Up Resistor
57
+V
S
+5V Supply
58
GND
Ground
59
I/O
REFB
B
Bottom Reference/Bypass, Channel B
60
I/O
REFT
B
Top Reference/Bypass, Channel B
61
O
CM
B
Common-Mode, Channel B
62
I
IN
B
Complementary Analog Input, Channel B
63
I
IN
B
Analog Input, Channel B
64
GND
Ground