BCM3212
DOCSIS
TM
1.1 ADVANCED CMTS MAC
Performs DOCSIS
TM
1.1 MAC layer functions, including:
Fragment reassembly
Deconcatenation
Payload header suppression and expansion
56-bit DES encryption and decryption
Generation and checking of HCS and CRC
MPEG encapsulation of downstream traffic
Timestamp and SYNC message generation
Supports one downstream and up to six upstream channels
simultaneously
Many other downstream-to-upstream ratios can be achieved by
connecting multiple BCM3212 devices via the seamless MAP
master/slave interface
Processes up to 400,000 packets per second in the aggregate
over all upstream and downstream channels
Direct interface to:
BCM3034 QAMLink advanced universal QAM modulator
(providing downstream data rates up to 100 Mbps)
BCM3138 QAMLink dual-channel advanced PHY burst
receiver (providing upstream data rates up to 30 Mbps per
upstream channel)
Packet port provides a high-throughput data interface to other
network equipment via the standard IEEE 802.3z GMII
Ethernet interface
PCI interface to external host CPU supports either 32-bit or 64-
bit operation at either 33 MHz or 66 MHz
PROPANE
TM
packet acceleration and SMART
SPECTRUM
TM
technologies included for increased upstream
performance
Hardware support for MAC-layer per-packet functions
including fragmentation, concatenation, and payload header
suppression offloads system CPU, giving higher overall system
performance.
Extraction of bandwidth requests and DOCSIS MAC
management messages allows software to access these
messages without examining data packets.
Class-based queuing allows traffic prioritization:
High, medium, and low priority downstream queues.
High priority, low priority, request, and MAC management
upstream queues
Support for carrier class redundancy via timestamp
synchronization across multiple BCM3212 devices.
Supports high packet rates for maximum utilization of
available cable plant bandwidth.
Out-of-band (OOB) generator for messaging to BCM3352-
based cable modems.
Can be remoted from external routing/classification engine for
distributed CMTS (mini fiber node) applications.
SPI master port controls register interface to BCM3034 and
BCM3138 devices.
Packaged in an 841-pin, thermally enhanced plastic ball grid
array.
Operates over industrial temperature range (40 to +85
degrees C) PCI bus.
F E A T U R E S
S U M M A R Y O F B E N E F I T S
Upstream
Analog Inputs
BCM3138
Dual Adv. TDMA
Receiver
BCM3138
BCM3138
Upstream
SDRAM
(keys and
reassembly.)
Upstream
SDRAM
(PHS,
output
queues)
Routing/
Classification
Engine
Ethernet
System
CPU
Memory
PCI Bus
BCM3212
Advanced CMTS MAC
Downstream
SDRAM
(PHS,
output
queues)
BCM3034
Downstream
Modulator
Downstream
Analog Inputs
WAN
Typical Application Block Diagram
O V E R V I E W
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
2004 by BROADCOM CORPORATION. All rights reserved.
3212-PB04-R
07/01/04
Broadcom
, the pulse logo, and Connecting everything
are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM3212 is a highly integrated CMTS MAC IC for use in
DOCSIS
TM
1.1 and advanced TDMA PHY-layer CMTS products. With
hardware support for concatenation parsing, fragment reassembly,
payload header suppression, and advanced TDMA PHY-layer data rates,
the BCM3212 serves as the heart of a next-generation CMTS. The
BCM3212 provides a powerful, yet cost-effective solution for a variety
of CMTS architectures.
The BCM3212 is based on sophisticated hardware processing engines
for both the upstream and downstream paths. To achieve upstream
throughput of 200 000 packets per second, the upstream processor design
is segmented and uses two banks of SDRAM to minimize latency on the
internal buses. The Upstream Processor performs DES decryption,
fragment reassembly, deconcatenation, payload header expansion,
PROPANE
TM
packet acceleration, upstream MIB statistic gathering,
and priority queuing for the resultant packets. Each upstream queue can
be independently configured to output packets to either the PCI or GMII
interface. DOCSIS MAC management messages and bandwidth requests
are extracted and queued separately from data packets so that they are
readily available to the system controller.
The downstream processor accepts packets from priority queues and
performs payload header suppression, DOCSIS header creation, DES
encryption, CRC and HCS generation, MPEG encapsulation and
multiplexing, and timestamp generation on the in-band data. The
BCM3212 also includes an out-of-band generator and TDMA PHY
interface so that the BCM3212 can communicate with the out-of-band
receiver of the BCM3352 cable modem device for control of power
management functions.
All configuration and management of the BCM3212 is done via the PCI
interface. The PCI interface accommodates either 32-bit or 64-bit hosts
operating at either 33 MHz or 66 MHz. The 100/1000 Ethernet MAC
provides a standard interface (IEEE 802.3z GMII or MII) for
transporting packets to and from the BCM3212.
A single BCM3212 supports the association of 1 downstream channel
with up to 6 upstream channels. By connecting multiple BCM3212 chips
via the seamless master/slave interface, many other ratios may be
achieved, including 2 downstream to 12 upstream (2:12) and 1
downstream to 24 upstream (1:24). In multiple downstream
configurations, upstream channels can be remotely provisioned to be
associated with 1 of 2 downstream channels to enable load shifting.
B C M 3 2 1 2
In-band D OC SIS Processo r
Post-Processing
S D R AM
co ntro ller
Fragm ent
re assem bly
controller
Payload
H ea der
Expa nd
P acket
D M A
O u tput
qu eue
m anag er
Re quest
D M A
100/100 0
Ethe rnet
M A C
PC I B us
Interface
U nit
U p stream
SD R A M 1
Up stream
SD R AM 2
Input
Qu eue
m ana ger
D ow nstream
SD R A M
Payload
H ea der
S uppress
D OC S IS
H ead er
crea tor
D ES
Encrypt
M A P
filte ring
M A P
parser
M P EG
encapsulate
D ow nstrea m
PH Y
In terfa ce
Tim estam p
gen eration
Out-of-
b and
Ge nera tor
O ut-of-
band
PH Y
Interface
In -ban d
q ueue
DM A
O u t-of-
band
q ueue
DM A
PC
I
I
n
t
e
r
f
a
c
e
U pstream
PH Y i/f
D E S
decryp t
R eque st
filterin g
Bu rst
D M A
SD R AM
con troller
SD R A M
controller
Pa
cke
t
P
o
r
t/G
M
II
Fr
o
m
B
C
M
3138
To
B
C
M
3034
Deconcatenation
PDF 
ZIP