Reference Only / Allayer Confidential
AL1032
Product Brief
12-Gigabit + 1 10-Gigabit Switching Processor
Product Description
The AL1032 is a 12-port Gigabit Ethernet switch processor chip with a 10-Gigabit backplane
uplink. It is targeted to provide high-density Gigabit port aggregation and switching. Its high
throughput and rich feature set make it an extremely powerful and flexible device.
Figure 1
System Block Diagram
Supports 12-Gigabit ports and one 10-Giga-
bit uplink in wirespeed operation, ideal for
Gigabit ports to backplane concentration
Gigabit ports support TBI (1000Base-X) or
GMII (1000Base-T) interfaces
Uplink supports XGMII interface for 10-
Gigabit
L2 search table supports 32K MAC
addresses
Jumbo Frame support (9K Bytes)
Supports 4K VLAN address and 802.1s
Multiple Spanning Tree protocol
Supports 802.1p and/or DiffServ with four
priority queues
Supports 802.3ad link aggregation control
protocol (LACP) and marker protocol
Supports selected groups in RMON and
SMON
Supports up to 32K IP multicast groups with
option to cross VLAN boundary
Supports frame trapping for CPU processing
Full-duplex & half-duplex operation with
IEEE 802.3x flow control & backpressure
On-chip packet memory with sophisticated
buffer management
Built in 32-bit, 33 MHz PCI bus interface
Flexible multiplexer modes
Packaged in 785-pin BGA
Shared Buffer
Buffer
Manager
Output
Queueing
MIB
Counters
PCI
Interface
Tx FIFO
Rx FIFO
Tx FIFO
Rx FIFO
Serial
to
Parallel
Parallel
to
Serial
10 G MAC
L2 MAC
Table
Table
Maintenance
To CPU
Tx FIFO
Rx FIFO
G MAC
10 G-Port
(12x) G-Port
VLAN
Table
Port
Manager
AL1032 Product Brief
11/00
Reference Only / Allayer Confidential
2
AL1032 Overview
The AL1032 switching processor chip supports 12-Gigabit ports and one 10-Gigabit uplink with
all ports in wirespeed operation. The AL1032 is ideal for applications such as multi-Gigabit-port
switches or aggregating multiple-Gigabit-ports to a 10-Gigabit backplane. For Gigabit ports, the
AL1032 supports PCS (802.3z, 1000Base-X) or GMII (802.3ab, 1000Base-T) interfaces with
full-duplex operation at Gigabit speed, and full- or half-duplex operation at 10/100 Mbps speed
(using 1000Base-T). For the uplink port, the AL1032 supports XGMII interface for 10-Gigabit.
For each port, there is a receiving (Rx) FIFO to interface with the Rx MAC. While the frame is in
the Rx FIFO, the pertinent information is retrieved and put into the parser registers. The L2
searching engines take the parser data from the parser registers to perform searching and
classification. The searching and classification tables are shared among all ports in a round-robin
fashion. After searching and classification, any header replacement is accomplished while the
frame is in the Rx FIFO. The maximum frame size supported is 9K bytes (Jumbo Frames).
Frames coming out of the Rx FIFO are sent to a shared buffer for storage and switching. The
width of the shared buffer is enough to provide more than 32-Gbps of switching bandwidth. The
size of the shared buffer is 1-Mbyte with half of the buffer being shared among the 12-Gigabit
ports, and the other half shared between the CPU port and uplink port.
To support Quality of Service (QoS), each output port has four priority queues and their
assignment can be based on DiffServ DS field or the 802.1p priority field. Each output port
retrieves the frames from the shared buffer based on queueing and sends them to the transmitting
(Tx) FIFO.
The device supports 32K internal MAC addresses which are shared by all ports. Multicast MAC
addresses including IP multicast can also be stored and searched. The device supports both port-
based and tagged (802.1q and 802.3ac) Virtual LAN (VLAN). The AL1032 also supports 4K
VLAN addresses with the 802.1s Multiple Spanning Tree option, and flexible and programmable
ingress and egress checking rules for VLAN processing.
The device also supports 802.3ad port aggregation. The 12-Gigabit ports can form up to 6-trunks,
with a maximum of 12-ports in a trunk. The distribution algorithm is user-selectable. The Link
Aggregation Control Protocol (LACP) frames are handled by the accompanying CPU and the
marker protocol is handled in hardware.
The device can be initialized and configured by an EEPROM or a CPU, which is also responsible
for search table updates and management functions. The CPU is a separate port to the device,
containing its own Tx FIFO and Rx FIFO. The device implements a 32-bit, 33 MHz peripheral
component interconnect (PCI) for flexible CPU selection and interface.
Other features include frame trapping and forwarding to the CPU, port monitoring, and broadcast
storm control to reduce broadcast traffic through the switch. The AL1032 also offers a flexible
Multiplexer mode in which the L2 switching functionality can be turned on and off.
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