0273HPEEPR10/04
Features
Single 2.7V - 3.6V Supply
Fast Read Access Time 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64 Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1- to 64-byte Page Write Operation
Low Power Dissipation
15 mA Active Current
20
A CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 10,000 Cycles
Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28BV256 is a high-performance Electrically Erasable and Programmable Read
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel's advanced nonvolatile CMOS technology, the device offers access
times to 200 ns with power dissipation of just 54 mW. When the device is deselected,
the CMOS standby current is less than 200
A.
256K (32K x 8)
Battery-Voltage
Parallel
EEPROMs
AT28BV256
PLCC Top View
Pin Configurations
Pin Name
Function
A0 - A14
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don't Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
A14
DC
VCC
WE
A13
PDIP, SOIC Top View
Note:
1. Note: PLCC package pins 1 and 17
are DON'T CONNECT.
TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
2
AT28BV256
0273HPEEPR10/04
The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for
external components. The device contains a 64-byte page register to allow writing of up to 64
bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are inter-
nally latched, freeing the address and data bus for other operations. Following the initiation of
a write cycle, the device will automatically write the latched data using an internal control
timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a
write cycle has been detected a new access for a read or write can begin.
Atmel's AT28BV256 has additional features to ensure high quality and manufacturability. The
device utilizes internal error correction for extended endurance and improved data retention
characteristics. An optional software data protection mechanism is available to guard against
inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identifi-
cation or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature ..................................... -65C to +150C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
3
AT28BV256
0273HPEEPR10/04
Device
Operation
READ: The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins is asserted on
the outputs. The outputs are put in the high impedance state when either CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE
high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has
been started, it will automatically time itself to completion. Once a programming operation has
been initiated and for the duration of t
WC
, a read operation will effectively be a polling
operation.
PAGE WRITE: The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be
written into the device during a single internal programming period. A page write operation is
initiated in the same manner as a byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written within 150
s (t
BLC
) of the previous
byte. If the t
BLC
limit is exceeded the AT28BV256 will cease accepting data and commence the
internal programming operation. All bytes during a page write operation must reside on the
same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition
during the page write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
DATA POLLING: The AT28BV256 features DATA Polling to indicate the end of a write cycle.
During a byte or page write cycle, an attempted read of the last byte written will result in the
complement of the written data to be presented on I/O7. Once the write cycle has been com-
pleted, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may
begin at anytime during the write cycle.
TOGGLE BIT: In addition to DATA Polling, the AT28BV256 provides another method for
determining the end of a write cycle. During the write operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin
at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transi-
tions of the host system power supply. Atmel has incorporated both hardware and software
features that will protect the memory against inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the
AT28BV256 in the following ways: (a) V
CC
power-on delay once V
CC
has reached 1.8V (typ-
ical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write
inhibit holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise fil-
ter pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been
implemented on the AT28BV256. Software data protection (SDP) helps prevent inadvertent
writes from corrupting the data in the device. SDP can prevent inadvertent writes during
power-up and power-down as well as any other potential periods of system instability.
The AT28BV256 can only be written using the software data protection feature. A series of
three write commands to specific addresses with specific data must be presented to the
device before writing in the byte or page mode. The same three write commands must begin
each write operation. All software write commands must obey the page mode write timing
4
AT28BV256
0273HPEEPR10/04
specifications. The data in the 3-byte command sequence is not written to the device; the
address in the command sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write tim-
ers. No data will be written to the device; however, for the duration of t
WC
, read operations will
effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user
for device identification. By raising A9 to 12V
0.5V and using address locations 7FC0H to
7FFFH the additional bytes may be written to or read from in the same manner as the regular
memory array.
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC programming waveforms.
3. V
H
= 12.0V 0.5V.
DC and AC Operating Range
AT28BV256-20
AT28BV256-25
Operating Temperature (Case)
Com.
0C - 70C
0C - 70C
Ind.
-40C - 85C
-40C - 85C
V
CC
Power Supply
2.7V - 3.6V
2.7V - 3.6V
Operating Modes
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Chip Erase
V
IL
V
H
(3)
V
IL
High Z
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
+ 1V
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1V
Com.
20
A
Ind.
50
A
I
CC
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
15
mA
V
IL
Input Low Voltage
0.6
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 1.6 mA
0.3
V
V
OH
Output High Voltage
I
OH
= -100 A
2.0
V
5
AT28BV256
0273HPEEPR10/04
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol
Parameter
AT28BV256-20
AT28BV256-25
Units
Min
Max
Min
Max
t
ACC
Address to Output Delay
200
250
ns
t
CE
(1)
CE to Output Delay
200
250
ns
t
OE
(2)
OE to Output Delay
0
80
0
100
ns
t
DF
(3)(4)
CE or OE to Output Float
0
55
0
60
ns
t
OH
Output Hold from OE, CE or Address, whichever
occurred first
0
0
ns
t
CE
t
OE
t
DF
t
OH
t
ACC
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