1
Features
Low-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5V) and 400 kHz (2.7V) Compatibility
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 40 Years
ESD Protection: > 4000V
Description
The AT24C128SC/256SC provides 131,072/262,144 bits of serial electrically erasable
and programmable read only memory (EEPROM) organized as 16,384/32,768 words
of 8 bits each. The devices are optimized for use in smart card applications where low-
power and low-voltage operation may be essential. The devices are available in
several standard ISO 7816 smart card modules (see Ordering Information). The entire
family is available in both high-voltage (4.5V to 5.5V) and low-voltage (2.7V to 5.5V)
versions. All devices are functionally equivalent to Atmel Serial EEPROM products
offered in standard IC packages (PDIP, SOIC, EIAJ, LAP), with the exception of the
slave address and Write Protect functions which are not required for smart card
applications.
Pin Configurations
Card Module Contact
Pad Name
Description
ISO Module Contact
VCC
Power Supply Voltage
C1
GND
Ground
C5
SCL
Serial Clock Input
C3
SDA
Serial Data Input/Output
C7
NC
No Connect
C2, C4, C6, C8
VCC
NC
2-wire Serial
EEPROM Smart
Card Modules
128K (16,384 x 8)
256K (32,768 x 8)
AT24C128SC
AT24C256SC
Rev. 1661A10/00
AT24C128SC/256SC
2
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or
open-collector devices.
Memory Organization
AT24C128SC/256SC, 128K/256K SERIAL EEPROM: The
128K/256K is internally organized as 256/512 pages of 64-
bytes each. Random word addressing requires a 14/15-bit
data word address.
Absolute Maximum Ratings*
Operating Temperature.................................. -55
C to +125C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65
C to +150C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
AT24C128SC/256SC
3
Note:
This parameter is characterized and is not 100% tested.
Note:
1. V
IL
min and V
IH
max are reference only and are not tested
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25
C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol
Test Condition
Max
Units
Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (SCL)
6
pF
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AC
= 0
C to +70C, V
CC
= +2.7V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
V
CC1
Supply Voltage
2.7
5.5
V
V
CC2
Supply Voltage
4.5
5.5
V
I
CC1
Supply Current
V
CC
= 5.0V
Read at 400 kHz
1.0
2.0
mA
I
CC2
Supply Current
V
CC
= 5.0V
Write at 400 kHz
2.0
3.0
mA
I
SB1
Standby Current
(2.7V option)
V
CC
= 2.7V
V
IN
= V
CC
or GND
0.5
A
V
CC
= 5.5V
6.0
I
SB2
Standby Current
(5.0V option)
V
CC
= 4.5 - 5.5V
V
IN
= V
CC
or GND
6.0
A
I
LI
Input Leakage Current
V
IN
= V
CC
or
GND
0.10
3.0
A
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
GND
0.05
3.0
A
V
IL
Input Low Level
(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level
(1)
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL
Output Low Level
V
CC
= 3.0V
I
OL
= 2.1 mA
0.4
V
AT24C128SC/256SC
4
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k
(2.7V, 5V),
Input pulse voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
50ns
Input and output timing reference voltages: 0.5V
CC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C128SC/256SC features a
low power standby mode which is enabled: a) upon power-
up and b) after the receipt of the STOP bit and the comple-
tion of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition as SDA is high.
AC Characteristics
Applicable over recommended operating range from T
A
= 0
C to +70C, V
CC
= +2.7V to +5.5V, CL = 100 pF (unless other-
wise noted). Test conditions are listed in Note 2.
Symbol
Parameter
2.7-volt
5.0-volt
Units
Min
Max
Min
Max
f
SCL
Clock Frequency, SCL
400
1000
kHz
t
LOW
Clock Pulse Width Low
1.3
0.6
s
t
HIGH
Clock Pulse Width High
1.0
0.4
s
t
AA
Clock Low to Data Out Valid
0.05
0.9
0.05
0.55
s
t
BUF
Time the bus must be free before a new
transmission can start
(1)
1.3
0.5
s
t
HD.STA
Start Hold Time
0.6
0.25
s
t
SU.STA
Start Set-up Time
0.6
0.25
s
t
HD.DAT
Data In Hold Time
0
0
s
t
SU.DAT
Data In Set-up Time
100
100
ns
t
R
Inputs Rise Time
(1)
0.3
0.3
s
t
F
Inputs Fall Time
(1)
300
100
ns
t
SU.STO
Stop Set-up Time
0.6
0.25
s
t
DH
Data Out Hold Time
50
50
ns
t
WR
Write Cycle Time
10
10
ms
Endurance
(1)
5.0V, 25C, Page Mode
100K
100K
Write
Cycles
AT24C128SC/256SC
5
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Note:
1. The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
t
WR
(1)
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