ASIX ELECTRONICS CORPORATION
First Released Date : Oct/02/1998
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88195P
10/100BASE Fast Ethernet MAC Controller
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
Document No.: AX195-17 / V1.7 / May. 12 '00
Features
IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
NE2000 register level compatible instruction
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides a MII port for both 10/100Mbps operation
Support EEPROM interface to store MAC address
External and internal loop-back capability
Two external 32K*8 Asynchronous SRAMs
required for packet buffer
128-pin LQFP low profile package
25MHz Operation, Dual 5V and 3.3V CMOS
process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88195 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller.
The AX88195 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80x86 series, MC68K series
CPU and ISA bus. The AX88195 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify the
design. Two low cost 32k*8 SRAM is required for packet buffer.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
CPU
LATCH
AX88195
AD BUS
Addr L
Addr H
Ctl BUS
BUFFER
SRAM
PHY/TxRx
RJ45
ASIX ELECTRONICS CORPORATION
2
AX88195 Local CPU Bus Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 4
1.1 G
ENERAL
D
ESCRIPTION
:..................................................................................................................................... 4
1.2 AX88195 B
LOCK
D
IAGRAM
: .............................................................................................................................. 4
1.3 AX88195 P
IN
C
ONNECTION
D
IAGRAM
............................................................................................................... 5
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode ................................................................................ 6
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode................................................................................... 7
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode ................................................................................ 8
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode ............................................................................... 9
2.0 SIGNAL DESCRIPTION ................................................................................................................................. 10
2.1 L
OCAL
CPU B
US
I
NTERFACE
S
IGNALS
G
ROUP
................................................................................................... 10
2.2 MII
INTERFACE SIGNALS GROUP
........................................................................................................................ 11
2.3 EEPROM S
IGNALS
G
ROUP
.............................................................................................................................. 12
2.4 SRAM I
NTERFACE PINS GROUP
......................................................................................................................... 12
2.5 M
ISCELLANEOUS PINS GROUP
............................................................................................................................ 12
2.6 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 13
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 14
3.1 EEPROM M
EMORY
M
APPING
.......................................................................................................................... 14
3.2 I/O M
APPING
................................................................................................................................................... 14
3.3 SRAM M
EMORY
M
APPING
.............................................................................................................................. 14
4.0 REGISTERS OPERATION ............................................................................................................................. 15
4.1 C
OMMAND
R
EGISTER
(CR) O
FFSET
00H (R
EAD
/W
RITE
)................................................................................... 17
4.2 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) O
FFSET
07H (R
EAD
/W
RITE
) ..................................................................... 17
4.3 I
NTERRUPT MASK REGISTER
(IMR) O
FFSET
0FH (W
RITE
) ................................................................................. 18
4.4 D
ATA
C
ONFIGURATION
R
EGISTER
(DCR) O
FFSET
0EH (W
RITE
) ....................................................................... 18
4.5 T
RANSMIT
C
ONFIGURATION
R
EGISTER
(TCR) O
FFSET
0DH (W
RITE
) ................................................................ 18
4.6 T
RANSMIT
S
TATUS
R
EGISTER
(TSR) O
FFSET
04H (R
EAD
) ................................................................................ 19
4.7 R
ECEIVE
C
ONFIGURATION
(RCR) O
FFSET
0CH (W
RITE
) .................................................................................. 19
4.8 R
ECEIVE
S
TATUS
R
EGISTER
(RSR) O
FFSET
0CH (R
EAD
) .................................................................................. 19
4.9 I
NTER
-
FRAME GAP
(IFG) O
FFSET
16H (R
EAD
/W
RITE
) ...................................................................................... 20
4.10 I
NTER
-
FRAME GAP
S
EGMENT
1(IFGS1) O
FFSET
12H (R
EAD
/W
RITE
) ............................................................... 20
4.11 I
NTER
-
FRAME GAP
S
EGMENT
2(IFGS2) O
FFSET
13H (R
EAD
/W
RITE
) ............................................................... 20
4.12 MII/EEPROM M
ANAGEMENT
R
EGISTER
(MEMR) O
FFSET
14H (R
EAD
/W
RITE
) .............................................. 20
4.13 T
EST
R
EGISTER
(TR) O
FFSET
15H (W
RITE
) ................................................................................................... 20
5.0 CPU I/O READ AND WRITE FUNCTIONS .................................................................................................. 21
5.1 ISA
BUS TYPE ACCESS FUNCTIONS
. ................................................................................................................... 21
5.2 80186 CPU
BUS TYPE ACCESS FUNCTIONS
......................................................................................................... 21
5.3 MC68K CPU
BUS TYPE ACCESS FUNCTIONS
...................................................................................................... 22
5.3 MCS-51 CPU
BUS TYPE ACCESS FUNCTIONS
. .................................................................................................... 22
6.0 ELECTRICAL SPECIFICATION AND TIMINGS........................................................................................ 23
6.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 23
6.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 23
6.3 DC C
HARACTERISTICS
..................................................................................................................................... 23
6.4 A.C. T
IMING
C
HARACTERISTICS
....................................................................................................................... 24
6.4.1 XTAL / CLOCK ........................................................................................................................................ 24
6.4.2 Reset Timing ............................................................................................................................................ 24
6.4.3 ISA Bus Access Timing............................................................................................................................. 25
6.4.4 80186 Type I/O Access Timing ................................................................................................................. 26
ASIX ELECTRONICS CORPORATION
3
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.5 68K Type I/O Access Timing .................................................................................................................... 27
6.4.6 8051 Bus Access Timing........................................................................................................................... 28
6.4.7 MII Timing............................................................................................................................................... 29
6.4.8 Asynchronous Memory I/F Access Timing ................................................................................................ 30
7.0 PACKAGE INFORMATION........................................................................................................................... 31
APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 32
A.1 U
SING
C
RYSTAL
.............................................................................................................................................. 32
A.2 U
SING
O
SCILLATOR
......................................................................................................................................... 32
A.3 D
UAL POWER
(5V
AND
3.3V/3.0V)
APPLICATION
............................................................................................. 33
A.4 S
INGLE POWER
(3.3V/3.0V)
APPLICATION
........................................................................................................ 33
A.5 D
UAL POWER
(5V
AND
3.3V)
APPLICATION WITH
3.3V PHY............................................................................. 34
APPENDIX B: APPLICATION NOTE 2 ............................................................................................................. 35
B.1 A
DVANCE
A
PPLICATION FOR
U
SING
C
RYSTAL
................................................................................................... 35
APPENDIX C: APPLICATION NOTE FOR RDY IS NOT APPLICABLE ...................................................... 36
ERRATA OF AX88195 V1..................................................................................................................................... 37
FIGURES
F
IG
- 1 AX88195 B
LOCK
D
IAGRAM
............................................................................................................................. 4
F
IG
- 2 AX88195 P
IN
C
ONNECTION
D
IAGRAM
.............................................................................................................. 5
F
IG
- 3 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
ISA B
US
M
ODE
............................................................................... 6
F
IG
- 4 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
80
X
86 M
ODE
.................................................................................. 7
F
IG
- 5 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
MC68K M
ODE
................................................................................ 8
F
IG
- 6 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
MCS-51 M
ODE
............................................................................... 9
TABLES
T
AB
- 1 L
OCAL
CPU
BUS INTERFACE SIGNALS GROUP
.................................................................................................. 11
T
AB
- 2 MII
INTERFACE SIGNALS GROUP
..................................................................................................................... 11
T
AB
- 3 EEPROM
BUS INTERFACE SIGNALS GROUP
..................................................................................................... 12
T
AB
- 4 SRAM I
NTERFACE PINS GROUP
...................................................................................................................... 12
T
AB
- 5 M
ISCELLANEOUS PINS GROUP
......................................................................................................................... 13
T
AB
- 6 P
OWER ON
C
ONFIGURATION
S
ETUP
T
ABLE
..................................................................................................... 13
T
AB
- 7 I/O A
DDRESS
M
APPING
................................................................................................................................. 14
T
AB
- 8 L
OCAL
M
EMORY
M
APPING
............................................................................................................................ 14
T
AB
- 9 P
AGE
0
OF
MAC C
ORE
R
EGISTERS
M
APPING
.................................................................................................. 15
T
AB
- 10 P
AGE
1
OF
MAC C
ORE
R
EGISTERS
M
APPING
................................................................................................ 16
ASIX ELECTRONICS CORPORATION
4
AX88195 Local CPU Bus Fast Ethernet MAC Controller
1.0 Introduction
1.1 General Description:
The AX88195 provides industrial standard NE2000 registers level compatable instruction set. Various drivers
are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to
various embedded system with no pain and tears
The AX88195 Fast Ethernet Controller is a high performance local CPU bus Ethernet Controller. The AX88195
supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80x86 series, MC68K series CPU
and ISA bus. The AX88196 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify
the design.
AX88195 use 128-pin LQFP low profile package, 25MHz operation, dual 5V and 3.3V CMOS process with 5V
I/O tolerance or pure 3.3V operation.
1.2 AX88195 Block Diagram:
Fig - 1 AX88195 Block Diagram
MAC
Core
SRAM
Arbiter
Remote
DMA
FIFOs
NE2000
Registers
Host Interface
STA
SEEPROM
I/F
SD[15:0]
SA[9:0]
Ctl BUS
MII I/F
MEMD[15:0]
MEMA[15:1]
EECS
EECK
EEDI
EEDO
ASIX ELECTRONICS CORPORATION
5
AX88195 Local CPU Bus Fast Ethernet MAC Controller
1.3 AX88195 Pin Connection Diagram
The AX88195 is housed in the 128-pin plastic light quad flat pack. Fig - 2 shows the AX88195 pin
connection diagram.
Fig - 2 AX88195 Pin Connection Diagram
123
118
122
78
70
54
41
32
24
12
8
MEMD[0]
LVDD
117
75
57
42
26
31
21
SA[1]
VSS
107
105
66
65
63
60
25
16
13
3
7
VSS
LCLK/XTALIN
HVDD
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
28
22
9
HVDD
NC
126
119
110
121
79
74
80
72
46
29
52
10
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
VSS
40
37
50
18
14
AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
103
104
82
91
81
86
93
94
84
87
95
96
90
88
92
85
89
83
98
97
99
100
102
101
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3] RXD[2]
RXD[1]
RXD[0]
LVDD
RX_CLK
CRS
COL
RX_DV
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
MEMD[14]
MEMD[15]
MEMA[1]
RX_ER
MEMA[2]
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
MEMA[15]
/MEMRD
/MEMWR
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
/IOWR
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
RESET
/BHE
TXD[0]
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
LVDD
LVDD
VSS
VSS
VSS
VSS
HVDD
VSS
/RESET
RDY/DTACK
IRQ
/CS
SAL[0]
SAL[1]
SAL[2]
SAH[1]
SAH[2]
/IOCS16
AEN/PSEN
/IORD
R/W
/LDS
SAX[0]
SAX[1]
SAX[3]
SAX[2]
/UDS
64
CLKO25M
SAH[0]
NC
NC
NC
/IRQ
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