Document Outline

• ARM940T Technical Reference Manual
  • Preface
    • About this document
    • Further reading
    • Feedback
  • 1 Introduction
    • 1.1 About the ARM940T
    • 1.2 Processor functional block diagram
  • 2 Programmer�s Model
    • 2.1 About the programmer�s model
    • 2.2 About the ARM9TDMI programmer�s model
      • 2.2.1 Data Abort model
      • 2.2.2 Instruction set extension spaces
    • 2.3 CP15 register map summary
      • 2.3.1 Accessing CP15 registers
      • 2.3.2 Register 0, ID code
      • 2.3.3 Register 0, cache type
      • 2.3.4 Register 1, control register
      • 2.3.5 Register 2, instruction and data cachable registers
      • 2.3.6 Register 3, write buffer control register
      • 2.3.7 Register 4, reserved
      • 2.3.8 Register 5, instruction and data space protection registers
      • 2.3.9 Register 6, protection region base and size registers
      • 2.3.10 Register 7, cache operations register
      • 2.3.11 Register 8, reserved
      • 2.3.12 Register 9, instruction and data lockdown registers
      • 2.3.13 Registers 10 to 14, reserved
      • 2.3.14 Register 15, test/debug register
  • 3 Protection Unit
    • 3.1 About the protection unit
    • 3.2 Enabling the protection unit
    • 3.3 Memory regions
      • 3.3.1 Region base address
      • 3.3.2 Region size
      • 3.3.3 Partition attributes
    • 3.4 Overlapping regions
      • 3.4.1 Background regions
  • 4 Caches and Write Buffer
    • 4.1 Cache architecture
    • 4.2 ICache
      • 4.2.1 Enabling and disabling the ICache
      • 4.2.2 ICache operation
      • 4.2.3 ICache validity
    • 4.3 DCache
      • 4.3.1 Enabling and disabling the DCache
      • 4.3.2 Operation of the GCd bit and GBd bit
      • 4.3.3 DCache operation
      • 4.3.4 DCache validity
      • 4.3.5 DCache clean and flush
    • 4.4 The write buffer
      • 4.4.1 Write buffer operation
      • 4.4.2 Enabling and disabling the write buffer
      • 4.4.3 Buffered writes
      • 4.4.4 Drain write buffer
    • 4.5 Cache lockdown
      • 4.5.1 Locking down the caches
  • 5 Clock Modes
    • 5.1 About ARM940T clocking
    • 5.2 FastBus mode
    • 5.3 Synchronous mode
    • 5.4 Asynchronous mode
  • 6 Bus Interface Unit
    • 6.1 About the ARM940T bus interface
    • 6.2 ASB transfers
      • 6.2.1 Noncached LDRs and noncached fetches
      • 6.2.2 Noncached LDM
      • 6.2.3 Noncached LDM crossing a 4KB boundary
      • 6.2.4 Buffered and nonbuffered STR
      • 6.2.5 Buffered and nonbuffered STM
      • 6.2.6 NCNB STM crossing a 4KB boundary
      • 6.2.7 Cached LDR, cached LDM, and cached fetch
      • 6.2.8 Dirty data eviction, write-back of 4 words
      • 6.2.9 Swap
      • 6.2.10 AMBA ASB slave transfers
    • 6.3 External aborts
    • 6.4 Memory access order
  • 7 Coprocessor Interface
    • 7.1 About the coprocessor interface
      • 7.1.1 User-assignable coprocessor numbers
      • 7.1.2 External coprocessors
    • 7.2 LDC or STC
      • 7.2.1 Coprocessor handshake encoding
    • 7.3 MCR/MRC
    • 7.4 Interlocked MCR
    • 7.5 CDP
    • 7.6 Privileged instructions
    • 7.7 Busy-waiting and interrupts
  • 8 Debug Support
    • 8.1 About debug support
    • 8.2 Debug systems
      • 8.2.1 Debug host
      • 8.2.2 Protocol converter
      • 8.2.3 Debug target (ARM940T)
    • 8.3 Debug interface signals
      • 8.3.1 Entry into debug state on breakpoint
      • 8.3.2 Breakpoints and exceptions
      • 8.3.3 Watchpoints
      • 8.3.4 Watchpoints and exceptions
      • 8.3.5 Debug request
      • 8.3.6 Actions of the ARM940T in debug state
    • 8.4 Scan chains and JTAG interface
    • 8.5 The JTAG state machine
      • 8.5.1 Reset
      • 8.5.2 Pull-up resistors
      • 8.5.3 Instruction register
      • 8.5.4 Public instructions
    • 8.6 Test data registers
      • 8.6.1 Bypass register
      • 8.6.2 ARM940T device identification (ID) code register
      • 8.6.3 Instruction register
      • 8.6.4 Scan chain select register
      • 8.6.5 Scan chains 0, 1, 2, 3, 4, 5, and 15
    • 8.7 ARM940T core clocks
      • 8.7.1 Clock switching during debug
      • 8.7.2 Clock switching during test
    • 8.8 Determining the core and system state
      • 8.8.1 Determining the core state
      • 8.8.2 Determining system state
      • 8.8.3 Instructions that can have the SYSSPEED bit set
    • 8.9 Exit from debug state
    • 8.10 The behavior of the program counter during debug
      • 8.10.1 Breakpoint
      • 8.10.2 Watchpoint
      • 8.10.3 Watchpoint with another exception
      • 8.10.4 Watchpoint and breakpoint
      • 8.10.5 Debug request
      • 8.10.6 System speed accesses
      • 8.10.7 Summary of return address calculations
    • 8.11 EmbeddedICE unit
      • 8.11.1 Register map
      • 8.11.2 Using the mask register
      • 8.11.3 Control registers
      • 8.11.4 Debug control register
      • 8.11.5 Debug status register
      • 8.11.6 Vector catch register
    • 8.12 Vector catching
    • 8.13 Single-stepping
    • 8.14 Debug communications channel
      • 8.14.1 Debug comms channel registers
      • 8.14.2 Communication using the comms channel
      • 8.14.3 Software polling communication
      • 8.14.4 Interrupt driven communications
    • 8.15 The debugger view of the cache
      • 8.15.1 Scan access to the CP15 registers
      • 8.15.2 Scan access to the caches
  • 9 TrackingICE
    • 9.1 About TrackingICE
    • 9.2 Timing requirements
    • 9.3 TrackingICE outputs
  • 10 Test Support
    • 10.1 About test support
      • 10.1.1 ARM9TDMI
      • 10.1.2 ARM940T macrocell
    • 10.2 Scan chain 0 bit order
  • 11 Instruction Cycle Summary and Interlocks
    • 11.1 About the instruction cycle summary
    • 11.2 Instruction cycle times
      • 11.2.1 Multiplier cycle counts
    • 11.3 Interlocks
  • 12 AC Characteristics
    • 12.1 ARM940T timing diagrams
    • 12.2 ARM940T timing parameters
    • A.1 AMBA signals
      • A.1.1 AMBA bus specification
    • A.2 Coprocessor interface signals
    • A.3 JTAG and TAP controller signals
    • A.4 Debug signals
    • A.5 Miscellaneous signals
    • Index
      • A
      • B
      • C
      • D
      • E
      • F
      • I
      • J
      • L
      • M
      • N
      • O
      • P
      • R
      • S
      • T
      • W
  • Appendix A ARM940T Signal Descriptions
    • A.1 AMBA signals
    • A.2 Coprocessor interface signals
    • A.3 JTAG and TAP controller signals
    • A.4 Debug signals
    • A.5 Miscellaneous signals
  • Glossary
  • Index