Voice Recording & Playback Device
16 Minute Duration
2002/5/10 Page 1
APR6016
Features
Multi-level analog storage
- High quality audio recording and playback
Dual mode storage of analog and/or digital data
- Eliminates the need for separate digital memory
Advanced, non-volatile Flash memory technology
- No battery backup required
SPI interface
- Allows any commercial microcontroller to control
the device
Programmable Sampling Clock
- Allows user to choose quality and duration levels
Single 3V power supply
Low power consumption
- Playback operating current: 15 mA typical
- Standby current: 1 uA maximum
- Automatic power-down
Multiple package options available
- CSP, PDIP, Bare Die
On-board clock prescaler
- Eliminates the need for external clock dividers
Automatic squelch circuit
-
Reduces background noise during quiet passages
General Description
The APR6016 offers non-volatile storage of voice and/or data
in advanced Multi-Level Flash memory. Up to
16
minutes of
audio recording and playback can be accommodated. A max-
imum of 30K bits of digital data can be stored.
devices can be cascaded for longer duration recording or
greater digital storage. Device control is accomplished
through an industry standard SPI interface that allows a
microcontroller to manage message recording and playback.
This flexible arrangement allows for the widest variety of
messaging options. The
APR6016
is ideal for use in cellular
and cordless phones, telephone answering devices, personal
digital assistants, personal voice recorders, and voice pag-
ers.
APLUS
Integrated
achieves this high level of storage capabi-
lity
by using a proprietary analog multi-level storage te chnol -
logy
i mplemented in an advanced non-volatile Flash memory
process. Each memory cell can typically store 256 voltage
levels. This allows the
APR6008
voice
to
reproduce audio
signals in their natural form, eliminating the need for enco-
ding
and compression which can introduce distortion.
Figure 1 APR6016 Pinout Diagrams
/C S
D I
D O
V S S D
N C
N C
N C
A N A O U T -
A N A O U T +
N C
/R E S E T
V S S A
A U D O U T
S Q L C A P
S C L K
V C C D
E X T C L K
/IN T
S A C
V S S A
N C
/B U S Y
N C
N C
V C C A
A N A IN +
A N A IN -
/S Q L O U T
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
11
1 2
1 3
1 4
28 pin DIP
APLUS INTEGRATED CIRCUITS INC.
APR6016
Preliminary
APR6016 Data Sheet
Page 2
Voice Recording & Playback Device
Revision 1.0
Functional Description
The EXTCLK pin allows the use of an external sampling
clock. This input can accept a wide range of frequencies
depending on the divider ratio programmed into the divider
that follows the clock. Alternatively, the programmable inter-
nal oscillator can be used to supply the sampling clock. The
Mux following both signals automatically selects the EXTCLK
signal if a clock is present, otherwise the internal oscillator
source is chosen. Detailed information on how to program the
divider and internal oscillator can be found in the explanation
of the PWRUP command, which appears in the OpCode
Command Description section. Guidance on how to choose
the appropriate sample clock frequency can be found in the
Sampling Rate & Voice Quality section.
The audio signal containing the content you wish to record
should be fed into the differential inputs ANAIN-, and
ANAIN+. After pre-amplification the signal is routed into the
anti-aliasing filter. The anti-aliasing filter automatically adapts
its response based on the sample rate being used. No exter-
nal anti-aliasing filter is therefore required.
After passing through the anti-alias filter, the signal is fed into
the sample and hold circuit which works in conjunction with
the Analog Write Circuit to store each analog sample in a
flash memory cell.
When a read operation is desired the Analog Read Circuit
extracts the analog data from the memory array and feeds
the signal to the Internal Low Pass Filter. The low pass filter
converts the individual samples into a continuous output. The
output signal then goes to the squelch control circuit and dif-
ferential output driver. The differential output driver feeds the
ANAOUT+ and ANAOUT- pins. Both differential output pins
swing around a 1.23V potential.
The squelch control circuit automatically reduces the output
signal by 6 dB during quiet passages. A copy of the squelch
control signal is present on the /SQLOUT pin to facilitate
reducing gain in the external amplifier as well. For more infor-
mation, refer to the Squelch section.
After passing through the squelch circuit the output signal
goes to the output amplifier. The output amplifier drives a sin-
gle ended output on the AUDOUT pin. The single ended out-
put swings around a 1.23V potential.
All SPI control and hand shaking signals are routed to the
Master Control Circuit. This circuit decodes all the SPI signals
and generates all the internal control signals. It also contains
the status register used for examining the current status of
the APR6016.
Figure 2
APR6016 Block Diagram
SAC
Low Pass
Master Control Circuit
Amp
SCLK
/CS
DI
DO
/INT
/RESET
AUDOUT
/SQLOUT
Squelch
Amp
A N A O U T +
A N A O U T -
/BUSY
SQLCAP
R
o
w De
c
o
d
e
r
Column Decoder
Column Address
Row
Address
Single Analog
Memory Cell
3.84 Mcell Memory Array
Write Circuit
Low Pass
Read Circuit
Analog input/output
to Memory array
Pre-
Amp
ANAIN+
ANAIN-
Programmable Internal
Oscillator
Mux
EXTCLK
Programmable
Divider
Preliminary
APR6016 Data Sheet
Voice Recording & Playback Device
Page 3
Revision 1.0
Memory Organization
The APR6016 memory array is organized to allow the great-
est flexibility in message management and digital storage.
The smallest addressable memory unit is called a "sector".
The APR6016
contains 1280 sectors.
Figure 3 Memory Map.
Sectors 0 through 1279 can be used for analog storage. Dur-
ing audio recording one memory cell is used per sample
clock cycle. When recording is stopped an end of data (EOD)
bit is programed into the memory. This prevents playback of
silence when partial sectors are used. Unused memory that
exists between the EOD bit and the end of the sector can not
be used.
Sectors 0 through 9 are tested and guaranteed for digital
storage. Other sectors, with the exception of sector 1279, can
store data but have not been tested, and are thus not guaran-
teed to provide 100% good bits. This can be managed with
error correction or forward check-before-store methods.
Once a write cycle is initiated all previously written data in the
chosen sector is lost.
Mixing audio signals and digital data within the same sector is
not possible.
Note: There are a total of 15bits reserved for addressing. The
APR6016 only requires 11 bits.
The additional 4 bits are used
for larger device within the APR60XX family.
SPI Interface
All memory management is handled by an external host pro-
cessor. The host processor communicates with the APR6016
through a simple Serial Peripheral Interface (SPI) Port. The
SPI port can run on as little as three wires or as many as
seven depending on the amount of control necessary. This
section will describe how to manage memory using the
APR6016's
SPI Port and associated OpCode commands.
This topic is broken down into the following sections:
Sending Commands to the Device
OpCode Command Description
Receiving Device Information
Current Device Status (CDS)
Reading the Silicon Identification (SID)
Writing Digital Data
Reading Digital Data
Recording Audio Data
Playing Back Audio Data
Handshaking Signals
Sending Commands to the Device
This section describes the process of sending OpCodes to
the APR6016. All Opcodes are sent in the same way with the
exception of the DIG_WRITE and DIG_READ commands.
The DIG_WRITE and DIG_READ commands are described
in the Writing Digital Data and Reading Digital Data sections
that follow. The minimum SPI configuration needed to send
commands uses the DI, /CS, and SCLK pins. The device will
accept inputs on the DI pin whenever the /CS pin is low.
OpCode commands are clocked in on the rising edge of the
SPI clock. Figure 4 shows the timing diagram for shifting
OpCode commands into the device. Figure 5 is a description
of the OpCode stream.
You must wait for a command to finish executing before send-
ing a new command. This is accomplished by monitoring the
/BUSY pin. You can substitute monitoring of the busy pin by
inserting a fixed delay between commands. The required
delay is specified as T
next1
,T
nex t2
,T
next3
o r T
next4
. Figure 6
shows the timing diagram for sending consecutive com-
mands. Table 1 describes which T
nex t
specification to use.
Sector 0
Sector 1
Sector 1279
Can Not be Used for Digital Data
SAC Trigger Point
Preliminary
APR6016 Data Sheet
Page 4
Voice Recording & Playback Device
Revision 1.0
Figure 4 Sending SPI Commands
Figure 5 OpCode Format
Figure 6 Opcode Stream Timing
Op4
Op3
Op2
Op1
T
suDI
A1
A2
T
fCS
T
rCS
~
~
~
~
~
~
T
hDI
/CS
SCLK
DI
~~
~
~
~
~
A0
T
pSCLK
T
loSCLK
T
hiSCLK
T
next1
, T
next2
, T
next3
, T
next4
O p4 O p3
O p1 O p0 A14 A13 A12 A11 A10
A9
A8
A7
A6
O p2
{
{
F irst b it sh ifte d in
L a st b it s h ifted in
A5
A4
A3
A2
A1
O pC ode C om m a nd
O p Code Param eter
A0
C urre nt C om m and
N ext C om m and
T
next1
,T
next2
,T
next3
,T
next4
/CS
SC LK
DI
Preliminary
APR6016 Data Sheet
Voice Recording & Playback Device
Page 5
Revision 1.0
Table 1
Sequential Command Timing
OpCode Command Description
Designers have access to a total of 14 OpCodes. These
OpCodes are listed in Table 2. The name of the Opcode
appears in the left hand column. The following two columns
represent the actual binary information contained in the 20 bit
data stream. Some commands have limits on which com-
mand can follow them. These limits are shown in the "Allow-
able Follow on Commands" column. The last column
summarizes each command.
Combinations of OpCodes can be used to accommodate
almost any memory management scheme.
Table 2
APR6016 Operational Codes
Current Command
Next command
Timing Symbol
NOP
SID
Any Command
T
next1 5u SEC
PWRUP
Any Command
T
next2 5m SEC
STOP_PWDN
PWRUP
T
next2 5m SEC
SET_REC
REC
STOP, STOP_PWDN, SET_REC, REC,NOP
Within SAC Low Time
SET_PLAY
PLAY
STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP
SET_FWD
FWD
SET_FWD, FWD, STOP, STOP_PWDN
DIG_WRITE
DIG_READ
DIG_ERASE
Any Digital Command, STOP, STOP_PWDN
Note: For partial DIG_READ T
next3
is measured from the extra clock low that follows the 8K sampling rate: 376m SEC
4K sampling rate: 752m SEC
rise of /CS, not from the rise of /CS
T
next3
STOP
Any Command
T
next4 470m SEC
Instruction
Name
OpCode
(5 bits)
Opcode Parameters (15bits)
Allowable Follow
on Commands
Summary
[Op4 - Op0]
[Address MSB - Address LSB]
[Address 14 - Address 0]
NOP
[00000]
[Don't Care]
All Commands
No Operation
SID
[00001]
[Don't care]
All Commands
Causes the silicon ID to be read.
SET_FWD
[00010]
Sector Address
[A14 - A0]
SET_FWD,
FWD, STOP,
STOP_PWDN
Starts a fast forward operation from the
sector address specified.
FWD
[00011]
[Don't care]
SET_FWD,
FWD, STOP,
STOP_PWDN
Starts a fast forward operation from the
current sector address.
PWRUP
[00100]
[A14-A10]: all zeros
[A9-A2]: EXTCLK divider ratio
[A1-A0]: Sample Rate Frequency
All Commands
Resets the device to initial conditions.
Sets the sample frequency and divider
ratios.
STOP
[00110]
[Don't care]
All Commands
Stops the current operation.
STOP_PWDN
[00111]
[Don't care]
PWRUP
Stops the current operation. Causes the
device to enter power down mode.
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