ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Synchronous Buck PWM Controller

Single 12V Power Supply Required

Fast Transient Response
- 0~90% Duty Ratio

0.8V Reference with 1% Accuracy

Shutdown Function by Controlling

COMP Pin Voltage

Internal Soft-Start (3.4ms) Function

Voltage Mode PWM Control Design

Under-Voltage Protection

Over-Current Protection
- Sense Low Side MOSFET's R

DS(ON)

300KHz Fixed Switching Frequency

SOP-8 Package

Lead Free Available (RoHS Compliant)

Features

Applications

General Description

The APW7065 uses fixed 300KHz switching frequency,
voltage mode, synchronous PWM controller which
drives dual N-channel MOSFETs. The device integrates
the control, monitoring and protection functions into a
single package, provides one controlled power output
with under-voltage and over-current protections.

The APW7065 provides excellent regulation for output
load variation. The internal 0.8V temperature-
compensated reference voltage is designed to meet
the requirement of low output voltage applications. An
built-in digital soft-start with fixed soft-start interval
prevents the output voltage from overshoot as well as
limiting the input current.

The APW7065 with excellent protection functions:
POR, OCP and UVP. The Power-On Reset (POR)
circuit can monitor VCC supply voltage exceeds its
threshold voltage while the controller is running, and a
built-in digital soft-start provides output with controlled
voltage rise. The Over-Current Protection (OCP)
monitors the output current by using the voltage drop
across the lower MOSFET's R

DS(ON)

, comparing with

internal V

OCP

(0.27V), when the output current reaches

the trip point, the controller will run the soft-start
function until the fault events are removed. The Under-
Voltage Protection (UVP) monitors the voltage of FB
pin for short-circuit protection, when the V

is less

than 50% of V

REF

(0.4V), the controller will shutdown

the IC directly.

Pinouts

SOP-8

Graphics Card

Mother Board

PHASE

COMP

VCC

BOOT

UGATE

GND

LGATE

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

APW 7065

Handling Code

Temp. Range

Package Code

Package Code
K : SOP-8
Operating Ambient Temp. Range
E : -20 to 70 C
Handling Code
TU : Tube TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device

APW7065 K :

APW7065

XXXXX

XXXXX - Date Code

Lead Free Code

Ordering and Marking Information

Block Diagram

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.

Gate Control

Oscillator

Digital

Soft Start

Power-On

Reset

PHASE

LGATE

GND

VCC

BOOT

UGATE

50%V

REF

Error Amp

PWM

Comparator

U.V.P

Comparator

Sawtooth

Wave

COMP

0.27V

O.C.P

Comparator

REF

OSC

300KHz

Sense Low Side

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

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Application Circuit

Symbol

Parameter

Rating

Unit

VCC

VCC to GND

-0.3 ~ 16

BOOT

BOOT to PHASE

-0.3 ~ 16

UGATE

UGATE to PHASE

<400nS pulse width

>400nS pulse width

-5 ~ BOOT+5

-0.3 ~ BOOT+0.3

LGATE

LGATE to GND

<400nS pulse width

>400nS pulse width

-5 ~ VCC+5

-0.3 ~ VCC+0.3

PHASE

PHASE to GND

<400nS pulse width

>400nS pulse width

-5 ~ 21

-0.3 ~ 16

COMP, FB

COMP, FB to GND

-0.3 ~ 7

Junction Temperature Range

-20 ~ 150

STG

Storage Temperature

-65 ~ 150

SDR

Maximum Soldering Temperature, 10 Seconds

300

ESD

Minimum ESD Rating (Human Body Mode) (Note 2)

Absolute Maximum Ratings

OUT

470uFx2

VCC

BOOT

UGATE

PHASE

LGATE

GND

12V

COMP

0.1uF

APM2509

APM2506

1uF

1uH

470uF

1uH

470uFx2

18R

68nF

8.2nF

33nF

2.7K

2.2R

1N4148

2N7002

(12V)

(1.2V)

ON/OFF

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: The device is ESD sensitive. Handling precautions are recommended.

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

Symbol

Parameter

Range

Unit

VCC

VCC Supply Voltage

10.8 ~ 13.2

OUT

Converter Output Voltage

0.8 ~ 5

Converter Input Voltage

2.9 ~ 13.2

OUT

Converter Output Current

0 ~ 20

Ambient Temperature Range

-20 ~ 70

Junction Temperature Range

-20 ~ 125

Recommended Operating Conditions

Electrical Characteristics

Unless otherswise specified, these specifications apply over VCC=12V, and T

=-20~70

C. Typlcal values are at

=25

APW7065

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

SUPPLY CURRENT

VCC

VCC Nominal Supply Current

UGATE and LGATE Open

VCC Shutdown Supply Current UGATE, LGATE = GND

POWER-ON RESET

Rising VCC Threshold

9.5

Falling VCC Threshold

7.5

8.5

COMP Shutdown Threshold

1.2

COMP Shutdown Hysteresis

0.1

OSCILLATOR

OSC

Free Running Frequency

255

300

345

kHz

OSC

Ramp Amplitude

1.6

P-P

REFERENCE VOLTAGE

REF

Reference Voltage

Measured at FB Pin

0.8

Accuracy

=-20~70

-1.0

+1.0

ERROR AMPLIFIER

Gain Open Loop Gain

=10k, C

=10pF(Note3)

GBWP Open Loop Bandwidth

=10k, C

=10pF(Note3)

MHz

Slew Rate

=10k, C

=10pF(Note3)

V/us

FB Input Current

= 0.8V(Note3)

0.1

COMP

COMP High Voltage

5.5

COMP

COMP Low Voltage

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

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APW7065

Symbol

Parameter

Test Conditions

Min Typ Max

Unit

ERROR AMPLIFIER (Cont.)

COMP

COMP Source Current

COMP

=2V

COMP

COMP Sink Current

COMP

=2V

GATE DRIVERS

UGATE

Upper Gate Source Current

BOOT = 12V, V

UGATE

-V

PHASE

= 2V

2.6

UGATE

Upper Gate Sink Current

BOOT = 12V, V

UGATE

-V

PHASE

= 2V

1.05

LGATE

Lower Gate Source Current

VCC = 12V, V

LGATE

= 2V

4.9

LGATE

Lower Gate Sink Current

VCC = 12V, V

LGATE

= 2V

1.4

UGATE

Upper Gate Source Impedance BOOT = 12V, I

UGATE

= 0.1A

UGATE

Upper Gate Sink Impedance

BOOT = 12V, I

UGATE

= 0.1A

1.6

2.4

LGATE

Lower Gate Source Impedance VCC = 12V, I

LGATE

= 0.1A

1.3 1.95

LGATE

Lower Gate Sink Impedance

VCC = 12V, I

LGATE

= 0.1A

1.25 1.88

Dead Time

PROTECTIONS

OCP

Over-Current Reference Voltage T

=-20~70

0.23 0.27 0.31

UVP

Under-Voltage Threshold
Trip Point

Percent of V

REF

SOFT-START

Soft-Start Interval

3.4

Electrical Characteristics (Cont.)

Unless otherswise specified, these specifications apply over VCC=12V and T

=-20~70

C. Typlcal values are

at T

=25

Functional Pin Description

BOOT (Pin 1)

A bootstrap circuit with a diode connected to VCC is
used to create a voltage suitable to drive a logic-level
N-channel MOSFET.

UGATE (Pin 2)

Connect this pin to the high-side N-channel MOSFET's
gate. This pin provides gate drive for the high-side
MOSFET.

GND (Pin 3)

The GND terminal provides return path for the IC's bias
current and the low-side MOSFET driver's pull-low
current. Connect the pin to the system ground via very
low impedance layout on PCBs.

LGATE (Pin 4)

Connect this pin to the low-side N-channel MOSFET's
gate. This pin provides gate drive for the low-side
MOSFET.

Note 3: Guaranteed by design.

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

Functional Pin Description (Cont.)

VCC (Pin 5)

Connect this pin to a 12V supply voltage. This pin
provides bias supply for the control circuitry and the
low-side MOSFET driver. The voltage at this pin is
monitored for the Power-On Reset (POR) purpose. It
is recommended that a decoupling capacitor (1 to
10uF) be connected to GND for noise decoupling.

FB (Pin 6)

This pin is the inverting input of the internal error
amplifier. Connect this pin to the output (V

OUT

) of the

converter via an external resistor divider for closed-
loop operation. The output voltage set by the resistor
divider is determined using the following formula :

where R1 is the resistor connected from V

OUT

to FB ,

and R2 is the resistor connected from FB to GND. The

FB pin is also monitored for under voltage events.

COMP (Pin 7)

This pin is the output of PWM error amplifier. It is used

to set the compensation components. In addition, if

the pin is pulled below 1.2V, it will disable the device.

PHASE (Pin 8)

This pin is the return path for the upper gate driver.
Connect this pin to the upper MOSFET source. This
pin is also used to monitor the voltage drop across the
MOSFET for over-current protection.

Typical Characteristics

Power On

Power Off

CH1

CH2

CH3

CH1

CH2

CH3

CH4

0.8

OUT

VCC=12V, Vin=12V
Vo=1.2V, L=1uH

CH1: VCC (5V/div)
CH2: V

(1V/div)

CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div

CH1: VCC (5V/div)
CH2: V

(1V/div)

CH3: Vo (1V/div)
CH4: Ug (20/Vdiv)
Time: 10ms/div

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

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Typical Characteristics (Cont.)

Shutdown

UGATE Rising

UGATE Falling

CH1

CH2

CH3

CH1

CH2

CH3

CH1

CH2

CH3

CH1

CH2

CH3

CH4

CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ns/div

VCC=12V, Vin=12V
Vo=1.2V, L=1uH

VCC=12V, Vin=12V
Vo=1.2V, L=1uH
Iout=5A

CH1: V

COMP

(2V/div)

CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 5ms/div

CH1: V

COMP

(2V/div)

CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10Vdiv)
Time: 20us/div

CH1: IL (10A/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg(10V/div)
Time: 100us/div

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

Typical Characteristics (Cont.)

Load Transient Response

Under Voltage Protection

Over Current Protection

Short Test

CH1

CH2

CH1

CH2

CH3

CH1

CH2

CH3

CH1

CH2

CH3

CH4

VCC=12V, Vin=12V
Vo=1.2V, L=4.7uH

CH4

CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 2ms/div

CH4

CH1: IL (10A/div)
CH2: Vo (2V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 5ms/div

CH1: IL (10A/div)
CH2: Vo (1V/div)
CH3: Ug (20V/div)
CH4: Lg (10V/div)
Time: 100us/div

VCC=12V, Vin=12V
Vo=1.2V, L=1uH

CH1: Vo (500mV/div,AC)
CH2:Io (5A/div)
Time: 1ms/div

10A

VCC=12V, Vin=12V,Vo=1.2V, L=1uH,

L_side: APM2023, Rds(on)=17m

VCC=12V, Vin=12V
Vo=1.2V, L=1uH

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

0.5

1.5

2.5

3.5

0.5

1.5

2.5

0.792

0.794

0.796

0.798

0.8

0.802

0.804

-40

-20

100

120

275

280

285

290

295

300

305

310

-40 -20

80 100 120

Typical Characteristics (Cont.)

Switching Frequency vs. Junction Temperature

Reference Voltage vs. Junction Temperature

Junction Temperature (

C )

Switching Frequency(KHz)

Junction Temperature (

C )

Reference Voltage(V)

UGATE Source Current vs. UGATE Voltage

UGATE Sink Current vs. UGATE Voltage

UGATE Voltage (V)

UGATE Source Current (A)

UGATE Voltage (V)

UGATE Sink Current (A)

VBOOT=12V

VCC=12V

PHASE=2V

ANPEC Electronics Corp.

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APW7065

www.anpec.com.tw

0.5

1.5

2.5

3.5

Functional Description

Power On Reset (POR)

The Power-On Reset (POR) function of APW7065
continually monitors the input supply voltage (VCC)
and the COMP pin. The supply voltage (VCC) must
exceed its rising POR threshold voltage. The POR
function initiates soft-start operation after VCC and
COMP voltages exceed their POR thresholds. For
operation with a single +12V power source, V

and

VCC are equivalent and the +12V power source must
exceed the rising VCC threshold. The POR function
inhibits operation at disabled status (V

COMP

is less

than 1.2V). With both input supplies above their POR
thresholds, the device initiates a soft-start interval.

Soft-Start

The APW7065 has a built-in digital soft-start to con-
trol the output voltage rise and limit the current surge
during the start-up. In Figure 1, when VCC exceeds
rising POR threshold voltage, it will delay 2048/Fosc

Typical Characteristics (Cont.)

LGATE Source Current vs. LGATE Voltage

LGATE Sink Current vs. LGATE Voltage

LGATE Voltage (V)

LGATE Source Current (A)

LGATE Sink Current (A)

LGATE Voltage (V)

VCC=12V

Figure 2. shows more detail of the FB voltage ramp.
The FB voltage soft-start ramp is formed with many
small steps of voltage. The voltage of one step is about
12.5mV in FB, and the period of one step is about 16/
F

OSC

. This method provides a controlled voltage rise

1024/F

OSC

start

soft

048

OSC

delay

seconds and then begin soft start. During soft-start,
an internal ramp connected to the one of the positive
inputs of the Gm amplifier rises up from 0V to 2V to
replace the reference voltage (0.8V) until the ramp
voltage reaches the reference voltage. The soft-start
interval is decided by the oscillator frequency
(300kHz). The formulation is given by:

ANPEC Electronics Corp.

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APW7065

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Functional Description (Cont.)

Soft-Start (Cont.)

Figure 2.

Voltage(V)

12.5mV

16/Fosc

Time

Over-Current Protection

The over-current protection monitors the output current
by using the voltage drop across the lower MOSFET's
R

DS(ON)

and this voltage drop will be compared with the

internal 0.27V reference voltage. If the voltage drop
across the lower MOSFET's R

DS(ON)

is larger than

0.27V, an over-current condition is detected. The
threshold of the over current limit is given by:

)

(

Limit

For the over-current is never occurred in the normal
operating load range; the variation of all parameters in
the above equation should be determined.

and prevents the large peak current to charge output
capacitor.

Voltage(V)

Time

VCC

OUT

- The MOSFET's R

DS(ON)

is varied by temperature and

gate to source voltage, the user should de-
termine the maximum R

DS(ON)

in manufacturer's

datasheet.

- The minimum Vocset should be used in the above

equation.

Application Information

Output Voltage Selection

The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive
divider is recommended. The FB pin is the inverter
input of the error amplifier, and the reference voltage
is 0.8V. The output voltage is determined by:

Figure 1.

- Note that the I

LIMIT

is the current flow through the

lower MOSFET; I

LIMIT

must be greater than maxi-

mum output current add the half of inductor ripple
current.

Shutdown and Enable

Pulling the COMP voltage to GND by an open drain
transistor, shown in typical application circuit,
shutdown the APW7065 PWM controller. In shutdown
mode, the UGATE and LGATE turn off and pull to
PHASE and GND respectively.

Under Voltage Protection

The FB pin is monitored during converter operation by
the internal Under Voltage (UV) comparator. If the FB
voltage drops below 50% of the reference voltage (50%
of 0.8V = 0.4V), a fault signal is internally generated,
and the device turns off both high-side and low-side
MOSFET and the converter's output is latched to be
floating.

GND

OUT

0.8

Where R

OUT

is the resistor connected from V

OUT

to FB

and R

GND

is the resistor connected from FB to GND.

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

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Application Information (Cont.)

Output Inductor Selection

The inductor value determines the inductor ripple
current and affects the load transient response. Higher
inductor value reduces the inductor's ripple current and
induces lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:

OUT

RIPPLE

ESR

RIPPLE

OUT

where F

is the switching frequency of the regulator.

Although increase of the inductor value reduces the
ripple current and voltage, a tradeoff will exist between
the inductor's ripple current and the regulator load
transient response time.

A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
current. The maximum ripple current occurs at the
maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30%
of the maximum output current. Once the inductance
value has been chosen, select an inductor that is ca-
pable of carrying the required peak current without
going into saturation. In some types of inductors, es-
pecially core that is made of ferrite, the ripple current
will increase abruptly when it saturates. This will re-
sult in a larger output ripple voltage.

Output Capacitor Selection

Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is
intended for switching regulator applications. In some
applications, multiple capacitors have to be parallel to
achieve the desired ESR value. A small decoupling
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
capacitors also must be considered. If tantalum

capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.

Input Capacitor Selection

The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is
approximately I

OUT

/2, where I

OUT

is the load current.

During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer. For high frequency decoupling, a ceramic
capacitor 1uF can be connected between the drain of
upper MOSFET and the source of lower MOSFET.

MOSFET Selection

The selection of the N-channel power MOSFETs are
determined by the R

DS(ON)

, reverse transfer capacitance

RSS

) and maximum output current requirement. There

are two components of loss in the MOSFETs:
conduction loss and transition loss. For the upper
and lower MOSFET, the losses are approximately
given by the following:

UPPER

= I

OUT

(1+ TC)(R

DS(ON)

)D + (0.5)( I

OUT

)(V

)( t

LOWER

= I

OUT

(1+ TC)(R

DS(ON)

)(1-D)

Where I

OUT

is the load current

TC is the temperature dependency of R

DS(ON)

is the switching frequency

is the switching interval

D is the duty cycle

Note that both MOSFETs have conduction loss while
the upper MOSFET include an additional transition
loss. The switching internal, t

, is a function of the

reverse transfer capacitance C

RSS

. The (1+TC) term is

ANPEC Electronics Corp.

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APW7065

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to factor in the temperature dependency of the R

DS(ON)

and can be extracted from the "R

DS(ON)

vs Temperature"

curve of the power MOSFET.

PWM Compensation

The output LC filter of a step down converter introduces
a double pole, which contributes with -40dB/decade
gain slope and 180 degrees phase shift in the control
loop. A compensation network among COMP, FB and
V

OUT

should be added. The compensation network is

shown in Fig. 6. The output LC filter consists of the
output inductor and output capacitors. The transfer
function of the LC filter is given by:

Application Information (Cont.)

MOSFET Selection (Cont.)

The poles and zero of this transfer functions are:

OUT

ESR

The F

is the double poles of the LC filter, and F

ESR

the zero introduced by the ESR of the output capacitor.

PHASE

OUTPUT

OUT

ESR

Figure 3. The Output LC Filter

ESR

-40dB/dec

-20dB/dec

Frequency(Hz)

GAIN (dB)

The PWM modulator is shown in Figure 5. The input
is the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM
modulator is given by:

Figure 5. The PWM Modulator

Output of

Error Amplifier

OSC

PWM

Comparator

Driver

PHASE

OSC

The compensation network is shown in Figure 6. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:

sC3

R1//

sC2

sC1

GAIN

OUT

COMP

AMP

OSC

PWM

GAIN

ESR

GAIN

OUT

Figure 4. The LC Filter GAIN and Frequency

(

)

ANPEC Electronics Corp.

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APW7065

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The poles and zeros of the transfer function are:

(

)

Application Information (Cont.)

PWM Compensation (Cont.)

The closed loop gain of the converter can be written
as:

GAIN

X GAIN

PWM

X GAIN

AMP

Figure 7. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help
to design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.

1.Choose a value for R1, usually between 1K and 5K.

2.Select the desired zero crossover frequency F

(1/5 ~ 1/10) X F

ESR

Use the following equation to calculate R2:

3.Place the first zero F

before the output LC filter

double pole frequency F

= 0.75 X F

0.75

4.Set the pole at the ESR zero frequency F

ESR

= F

ESR

Calculate the C1 by the equation:

ESR

5.Set the second pole F

at the half of the switching

frequency and also set the second zero F

at the

output LC filter double pole F

. The compensation

gain should not exceed the error amplifier open loop
gain, check the compensation gain at F

with the

capabilities of the error amplifier.

= 0.5 X F

= F

Combine the two equations will get the following
component calculations:

OSC

Frequency(Hz)

I
N

(
d

)

20log

(R2/R1)

20log

OSC

)

ESR

PWM & Filter

Gain

Converter

Gain

Compensation

Gain

Figure 7. Converter Gain and Frequency

REF

OUT

COMP

Figure 6. Compensation Network

Calculate the C2 by the equation:

ANPEC Electronics Corp.

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APW7065

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Layout Considerations

In any high switching frequency converter, a correct
layout is important to ensure proper operation of the
regulator. With power devices switching at 300KHz,
the resulting current transient will cause voltage spike
across the interconnecting impedance and parasitic
circuit elements. As an example, consider the turn-off
transition of the PWM MOSFET. Before turn-off, the
MOSFET is carrying the full load current. During
turn-off, current stops flowing in the MOSFET and is
free-wheeling by the lower MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates
a large voltage spike during the switching interval. In
general, using short, wide printed circuit traces
should minimize interconnecting impedances and
the magnitude of voltage spike. And signal and power
grounds are to be kept separate till combined using
ground plane construction or single point grounding.
Figure 8. illustrates the layout, with bold lines indicating
high current paths; these traces must be short and
wide. Components along the bold lines should be
placed lose together. Below is a checklist for your
layout:

- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
possible.

- The traces from the gate drivers to the MOSFETs
(UG, LG) should be short and wide.

- Place the source of the high-side MOSFET and
the drain of the low-side MOSFET as close
possible. Minimizing the impedance with wide
layout plane between the two pads reduces the
voltage bounce of the node.

- Decoupling capacitor, compensation component,

Application Information (Cont.)

Figure 8.Layout Guidelines

the resistor dividers, and boot capacitors should
be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placed near the drain).

- The input capacitor should be near the drain of
the upper MOSFET; the output capacitor should
be near the loads. The input capacitor GND should
be close to the output capacitor GND and the lower
MOSFET GND.

- The drain of the MOSFETs (V

and PHASE

nodes) should be a large plane for heat sinking.

VCC

BOOT

PHASE

UGATE

LGATE

OUT

L
O
A
D

APW7065

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

t 25 C to Peak

Ramp-up

Ramp-down

Preheat

Tsmax

Tsmin

Temperature

Time

Critical Zone

to T

Physical Specifications

Terminal Material

Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn

Lead Solderability

Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.

Reflow Condition

(IR/Convection or VPR Reflow)

Classificatin Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly

Pb-Free Assembly

Average ramp-up rate
(T

to T

)

C/second max.

Preheat

Temperature Min (Tsmin)

Temperature Max (Tsmax)

Time (min to max) (ts)

100

150

60-120 seconds

150

200

60-180 seconds

Time maintained above:

Temperature (T

)

Time (t

)

183

60-150 seconds

217

60-150 seconds

Peak/Classificatioon Temperature (Tp)

See table 1

See table 2

Time within 5

C of actual

Peak Temperature (tp)

10-30 seconds

20-40 seconds

Ramp-down Rate

C/second max.

Time 25

C to Peak Temperature

6 minutes max.

8 minutes max.

Notes: All temperatures refer to topside of the package .Measured on the body surface.

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

Carrier Tape & Reel Dimensions

Test item

Method

Description

SOLDERABILITY

MIL-STD-883D-2003

245

C, 5 SEC

HOLT

MIL-STD-883D-1005.7

1000 Hrs Bias @125

PCT

JESD-22-B,A102

168 Hrs, 100

RH, 121

TST

MIL-STD-883D-1011.9

-65

C~150

C, 200 Cycles

ESD

MIL-STD-883D-3015.7

VHBM > 2KV, VMM > 200V

Latch-Up

JESD 78

10ms, 1

> 100mA

Reliability Test Program

Table 1. SnPb Entectic Process Package Peak Reflow Temperature s

Package Thickness

Volume mm

<350

Volume mm

350

<2.5 mm

240 +0/-5

225 +0/-5

2.5 mm

225 +0/-5

Table 2. Pb-free Process Package Classification Reflow Temperatures

Package Thickness

Volume mm

<350

Volume mm

350-2000

Volume mm

>2000

<1.6 mm

260 +0

C *

260 +0

1.6 mm 2.5 mm

260 +0

250 +0

C *

245 +0

2.5 mm

250 +0

245 +0

C *

245 +0

*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and

including the stated classification temperature (this means Peak reflow temperature +0

For example 260

C+0

C) at the rated MSL level.

Classification Reflow Profiles (Cont.)

ANPEC Electronics Corp.

Rev. A.1 - Feb., 2006

APW7065

www.anpec.com.tw

Customer Service

Reel Dimensions

Application

330

1 62 +1.5 12.75+ 0.15 2

0.5 12.4

0.2 2

0.2

0. 3 8

0.1 1.75

0.1

SOP- 8

5.5

1 1.55 +0.1 1.55+ 0.25 4.0

0.1 2.0

0.1 6.4

0.1 5.2

0. 1 2.1

0.1 0.3

0.013

Cover Tape Dimensions

Application

Carrier Width

Cover Tape Width

Devices Per Reel

SOP- 8

9.3

2500

Carrier Tape & Reel Dimensions (Cont.)

(mm)

Anpec Electronics Corp.
Head Office :

No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :

7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369

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