Copyright
ANPEC Electronics Corp.
Rev.P.1 - Mar., 2001
APW7025
www.anpec.com.tw
1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Advanced PWM and Dual Linear Power Control
Features
General Description
3 Regulated Voltage are provided
Switching Power for VTT(1.25V)
Linear1 Regulator for FBVDDQ(2.5V)
Linear2 Regulator for NVVDD(2.05V)
Simple Single-Loop Control Design
Voltage-Mode PWM Control
Excellent Output Voltage Regulation
PWM Output
:
1%
Linear Output
:
3%
Fast Transient Response
High-Bandwidth Error Amplifier
Full 0% to 100% Duty Ratio
Power-Good Output Voltage Monitor
Over-Voltage and Over-Current Fault Monitors
Small Converter Size
Constant Frequency Operation(200kHz)
Programmable Oscillator from 50kHz to 1MHz
Reduce External Component Count
Motherboard Power Regulation for Computers
Low-Voltage Distributed Power Supplies
VGA Card Power Regulation
Applications
The APW7025 integrates a PWM controller and Dual
linear controller, as well as the monitoring and pro-
tection functions into a single package , which pro-
vides three controlled power outputs with over-volt-
age and over-current protections. The PWM control-
ler regulates the DDR reference voltage with a syn-
chronous-rectified buck converter. The linear control-
ler regulates power for microprocessor core voltage
and Memory Voltage.
The precision reference and voltage-mode PWM
control provide
2% static regulation. The linear
controller drives an external N-channel MOSFET to
provide adjustable voltage.
The APW7025 monitors all the output voltages , and
a single Power Good signal is issued when the PWM
Voltage is within 10% of the 1.25V setting and the
other output levels are above their under-voltage
thresholds. Additional built-in over-voltage protec-
tion for the PWM output uses the lower MOSFET to
prevent output voltages above 115% of the 1.25V
setting. The PWM over-current function monitors
the output current by using the voltage drop across
the upper MOSFET's R
DS(ON)
, eliminating the need
for a current sensing resistor.
Pin Description
VCC
DRIVE2
NC
NC
LGATE
OCSET
VSEN1
NC
NC
PGOOD
VSEN2
PGND
FB
COMP
VSEN3
GND
1
2
3
4
5
6
7
8
12
11
UGATE
10
9
16
15
14
13
17
18
19
20
24
23
22
21
VAUX
DRIVE3
PHASE
NC
SS
FAULT
NC
SOP24
Copyright
ANPEC Electronics Corp.
Rev. P.1 - Mar., 2001
APW7025
www.anpec.com.tw
2
Ordering Information
APW7025
Package Code
K : SOP - 24
Temp. Range
C : 0 to 70 C
Handling Code
TU : Tube TR : Tape & Reel
Handling Code
Temp. Range
Package Code
Block Diagram
Absolute Maximum Ratings
PGOOD
Power-on
Reset
(POR)
VCC
200
A
1.10
SOFT
START &
FAULT
LOGIC
+
-
GATE
CONTROL
+
-
PWM
COMP1
SYNCH
DRIVE
OV
UGATE
PHASE
V
CC
LGATE
PGND
COMP
FB
SS
OCSET
VSEN1
ERROR
AMP1
PWM1
VCC
INHIBIT
OC1
DRIVER1
VAUX
LUV
LINEAR
UNDER-
VOLTAGE
DRIVE3
-
+
+
-
-
+
+
-
+
-
+
-
OSCILLATOR
FAULT
0.90
1.15
V
CC
4.5V
28
A
FAULT
INHIBIT
VAUX
DRIVE2
VSEN2
GND
VSEN3
1.26V
+
-
0.75
+
-
+
-
1.5V
+
-
1.25V
+
-
Symbol
Parameter
Rating
Unit
V
CC
Supply Voltage
15
V
V
I
, V
O
Input , Output or I/O Voltage
GND -0.3 V to V
CC
+0.3
V
T
A
Operating Ambient Temperature Range
0 to 70
C
T
J
Junction Temperature Range
0 to 125
C
T
STG
Storage Temperature Range
-65 to +150
C
T
S
Soldering Temperature
300 ,10 seconds
C
Copyright
ANPEC Electronics Corp.
Rev. P.1 - Mar., 2001
APW7025
www.anpec.com.tw
3
Electrical Characteristics
Thermal Characteristics
Symbol
Parameter
Value
Unit
R
JA
Thermal Resistance in Free Air
SOIC
SOIC (with 3in
2
of Copper)
75
65
C/W
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic
APW7025
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Supply Current
I
CC
Nominal Supply Current
UGATE, LGATE, DRIVE2,
DRIVE3 open
9
mA
Power-on Reset
Rising VCC Threshold
Vocset=4.5V
10.4
V
Falling VCC Threshold
Vocset=4.5V
8.2
V
Rising VAUX Threshold
Vocset=4.5V
2.5
V
VAUX Threshold Hysteresis
Vocset=4.5V
0.5
V
Rising V
OCSET
Threshold
1.26
V
Oscillator
F
OCS
Free Running Frequency
RT= Open
185
200
215
kHz
V
OSC
Ramp Amplitude
RT= Open
1.9
V
P-P
DAC and Bandgap Reference
DAC Voltage accuracy
-1.0
+1.0
%
V
BG
Bandgap Reference Voltage
1.265
V
Bandgap Reference Tolerance
-2.5
+2.5
%
Linear Regulators (OUT2, OUT3)
Regulation (All Linears)
3
%
Output Drive Current (All Liners) VAUX-V
DRIVE
>0.6V
20
40
mA
Synchronous PWM Controller Error Amplifier
DC Gain
88
dB
GBWP Gain-Bandwidth Product
15
MHz
SR
Slew Rate
COMP=10pF
6
V/
s
PWM Controller Gate Driver
I
UGATE
UGATE Source
V
CC
=12V, V
UGATE
=6V
1
A
R
UGATE
UGATE Sink
V
UGATE1-PHASE
=1V
3.5
I
LGATE
LGATE Source
V
CC
=12V, V
LGATE
=1V
1
A
R
LGATE
LGATE Sink
V
LGATE
= 1V
3
Copyright
ANPEC Electronics Corp.
Rev. P.1 - Mar., 2001
APW7025
www.anpec.com.tw
4
Electrical Characteristics Cont.
APW7025
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Protection
VSEN1 Over-Voltage
(VSEN1/DACOUT)
VSEN1 Rising
115
120
%
I
OVP
FAULT Souring Current
V
FAULT/RT
=2.0V
8.5
mA
I
OCSET
OCSET Current Source
V
OCSET
= 4.5V
DC
170
200
230
A
I
SS
Soft Start Current
28
A
Power Good
VSEN1
Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108
110
%
VSEN1
Under Voltage
(VSEN1/DACOUT)
VSEN1 Rising
92
94
%
VSEN1
Hysteresis (VSEN1
/DACOUT)
Upper /Lower Threshold
2
%
V
PGOOD
PGOOD Voltage Low
I
PGOOD
= -4mA
0.8
V
Functional Pin Description
VCC (Pin 1)
Provide a 12V bias supply for the IC to this pin. This
pin also provides the gate bias charge for all the
MOSFETs controlled by the IC. The voltage at this
pin is monitored for Power-On Reset (POR) purposes.
DRIVE2 (Pin 2)
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the NVVDD regulator's
pass transistor.
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate
the status of the output voltages. This pin is pulled
low when the synchronous regulator output is not
within
10% of the DACOUT reference voltage or
when any of the other outputs are below their under-
voltage thresholds.
VSEN2 (Pin 9)
Connect this pin to a resistor divider to set the linear
regulator (NVVDD) output voltage.
SS (Pin 10)
Connect a capacitor from this pin to ground. This
capacitor, along with an internal 28
A current source,
sets the soft-start interval of the converter.
FAULT (Pin 11)
This pin provides oscillator switching frequency
adjustment. By placing a resistor (R
T
) from this pin to
GND, the nominal 200kHz switching frequency is in-
creased according to the following equation:
Fs =200kHz + 5
10
6
/ R
T
(k
)
(R
T
to GND)
Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the fol-
lowing equation:
Fs =200kHz + 4
10
7
/ R
T
(k
)
(R
T
to 12V)
Nominally, the voltage at this pin is 1.26V. In the event
of an over-voltage or over-current condition, this pin
Copyright
ANPEC Electronics Corp.
Rev. P.1 - Mar., 2001
APW7025
www.anpec.com.tw
5
is internally pulled to VCC.
VAUX (Pin 13)
This pin provides boost current for the linear
regulator's output drives in the event bipolar NPN tran-
sistors (instead of N-channel MOSFETs) are em-
ployed as pass elements. The voltage at this pin is
monitored for power-on reset purposes.
GND (Pin 14)
Signal ground for the IC. All voltage levels are mea-
sured with respect to this pin.
DRIVE3 (Pin 15)
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the FBVDDQ
regulator's pass transistor.
VSEN3 (Pin 16)
Connect this pin to a resistor divider to set the linear
regulator (FBVDDQ) output voltage.
COMP and FB (Pin 17, and 18)
COMP and FB are the available external pins of the
PWM converter error amplifier. The FB pin is the in-
verting input of the error amplifier. Similarly, the COMP
pin is the error amplifier output. These pins are used
to compensate the voltage-mode control feedback
loop of the synchronous PWM converter.
VSEN1 (Pin 19)
This pin is connected to the PWM converter's output
voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for
over- voltage
protection.
OCSET (Pin 20)
Connect a resistor from this pin to the drain of the
respective upper MOSFET. This resistor, an internal
200
A current source, and the upper MOSFET's on-
resistance set the converter over-
current trip point. An over-current trip cycles the soft-
start function.
The voltage at this pin is monitored for power-on re-
set (POR) purposes and pulling this pin low with an
open drain device will shutdown the IC.
PGND (Pin 21)
This is the power ground connection. Tie the syn-
chronous PWM converter's lower MOSFET source
to this pin.
LGATE (Pin 22)
Connect LGATE to the PWM converter's lower
MOSFET gate. This pin provides the gate drive for
the lower MOSFET.
PHASE (Pin 23)
Connect the PHASE pin to the PWM converter's up-
per MOSFET source. This pin represents the gate
drive return current path and is used to monitor the
voltage drop across the upper MOSFET for over-cur-
rent protection.
UGATE (Pin 24)
Connect UGATE pin to the PWM converter's upper
MOSFET gate. This pin provides the gate drive for
the upper MOSFET.
Functional Pin Description Cont.
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