Copyright
ANPEC Electronics Corp.
Rev. A.2 - May, 2001
APW6020
www.anpec.com.tw
1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Advanced Dual PWM and Dual Linear Power Controllers
Features
General Description
4 Regulated Voltages are provided
-
Microprocessor Core (1.3V to 3.5V)
-
AGP Bus (1.5V or 3.3V)
-
Memory (1.8V) , GTL Bus (1.5V)
Simple Single-Loop Control Designs
Voltage-Mode PWM Control
Fast PWM Converter Transient Response
High-Bandwidth Error Amplifiers
-
Full 0% to 100% Duty Ratios
Excellent Output Voltage Regulation
-
Core PWM Output :
1% Over Temperature
-
Other Outputs :
3% Over Temperature
TTL-Compatible 5- Bit DAC Microprocessor
Core Output Voltage Selection
-
Wide Range - 1.3V
DC
to 3.5 V
DC
Power-Good Output Voltage Monitor
Over-Voltage and Over-Current Fault Monitors
Small Converter Size
-
Constant Frequency Operation
-
200kHz Free-Running Oscillator ; Program-
mable From 50kHz to Over 800kHz
-
Small External Component Count
Applications
The APW6020 provides the power control and pro-
tection for four output voltages in high-performance ,
graphics intensive microprocessor and computer
applications. The IC integrates two voltage-mode
PWM controllers and two linear controllers , as well
as the monitoring and protection functions into a single
package. One PWM controller regulates the micro-
processor core voltage with a synchronous-rectified
buck converter. The second PWM controller sup-
plies the computer's AGP 1.5V or 3.3V bus power
with a standard Buck converter. The linear control-
lers requlate the power for the 1.5V GTL bus , and
the 1.8V power for the North/South Bridge core volt-
age and/or cache memory circuits. The APW6020
includes an Intel-compatible , TTL 5-input digital-to-
analog converter (DAC) that adjusts the core PWM
output voltage from 1.3 V
DC
to 2.05 V
DC
in 0.05V steps
and from 2.1 V
DC
to 3.5 V
DC
in 0.1V increments. The
precision reference and voltage-mode control provide
1% static regulation. The second PWM controller's
output is user-selectable , through a TTL-compatible
signal applied at the SELECT pin , for levels of 1.5V
or 3.3V with
3% accuracy. The two linear regula-
tors provide fixed output voltages of 1.5V
3% (V
OUT3
) and 1.8V
3% (V
OUT4
).
The APW6020 monitors all the output voltages. A
single Power Good signal is issued when the core is
within
10% of the DAC setting and all other outputs
are above their under-voltage levels. Additional built-
in over-voltage protection for the core output uses
the lower MOSFET to prevent output voltages above
115% of the DAC setting. The PWM controller's over-
current function monitors the output current by using
the voltage drop across the upper MOSFET's r
DS(ON)
.
Motherboard Power Regulation for Computers
Copyright
ANPEC Electronics Corp.
Rev. A.2 - May, 2001
APW6020
www.anpec.com.tw
2
Pin Description
Ordering Information
APW6020
Package Code
K : SOP - 28
Temp. Range
C : 0 to 70 C
Handling Code
TU : Tube TR : Tape & Reel
Handling Code
Temp. Range
Package Code
Block Diagram
VCC
FAULT/ RT
1
2
3
4
5
6
7
8
OCSET2
12
11
10
9
SS
16
15
13
14
17
18
19
20
24
23
22
21
28
27
26
25
LGATE1
OCSET1
VSEN1
PGND
FB1
COMP1
UGATE1
PHASE1
DRIVE3
GND
VAUX
DRIVE4
VID4
VID3
VID0
VID1
VID2
UGATE2
PHASE2
PGOOD
VSEN2
SELECT
VSEN4
VSEN3
PGOOD
Power-on
Reset (POR)
VCC
200
A
1.10
SOFT START &
FAULT LOGIC
+
-
GATE
CONTROL
PWM
COMP1
SYNCH
DRIVE
OV
DACOUT
UGATE1
PHASE1
VCC
LGATE1
PGND
COMP1
SS
OCSET1
VSEN1
ERROR
AMP1
PWM1
VCC
OC1
DRIVER1
VAUX
LUV
LINEAR
UNDER-
VOLTAGE
-
+
DRIVE3
DRIVE4
+
-
VID0
TTL D/A
CONVERTER
(DAC)
VID1 VID2 VID3 VID4
+
-
1.26V
+
-
+
-
OSCILLATOR
FAULT/ RT
0.90
1.15
VCC
4.5V
28
A
FAULT
INHIBIT
0.75
VCC
VSEN4
VSEN2
SELECT
GND
0.75
VSEN3
+
-
+
-
+
-
GATE
CONTROL
+
-
+
-
-
+
+
-
PHASE2
UGATE2
+
-
OCSET2
FB1
VCC
DRIVE2
INHIBIT
PWM2
PWM
COMP2
ERROR
AMP2
1.5V
or
3.3V
200
A
Copyright
ANPEC Electronics Corp.
Rev. A.2 - May, 2001
APW6020
www.anpec.com.tw
3
Absolute Maximum Ratings
Thermal Characteristics
Symbol
Parameter
Rating
Unit
V
CC
Supply Voltage
15
V
V
I
, V
O
Input , Output or I/O Voltage
GND -0.3 V to V
CC
V
T
A
Operating Ambient Temperature Range
0 to 70
C
T
J
Junction Temperature Range
0 to 125
C
T
STG
Storage Temperature Range
-65 to +150
C
T
S
Soldering Temperature
300 ,10 seconds
C
Symbol
Parameter
Value
Unit
R
JA
Thermal Resistance in Free Air
SOIC
SOIC (with 3in
2
of Copper)
75
65
C/W
Electrical Characteristics
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic
APW6020
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Supply Current
I
CC
Nominal Supply Current
UGATE1, LGATE1,
UGATE2, DRIVE3, and
DRIVE4 open
9
mA
Power-on Reset
Rising VCC Threshold
Vocset=4.5V
10.4
V
Falling VCC Threshold
Vocset=4.5V
8.2
V
Rising VAUX Threshold
Vocset=4.5V
2.5
V
VAUX Threshold Hysteresis
Vocset=4.5V
0.5
V
Rising V
OCSET1
Threshold
1.26
V
Oscillator
F
OCS
Free Running Frequency
RT= Open
185
200
215
kHz
V
OSC
Ramp Amplitude
RT= Open
1.9
V
P-P
DAC and Standard Buck Regulator Reference
DAC(VID0-VID4) Input Low
Voltage
0.8
V
Copyright
ANPEC Electronics Corp.
Rev. A.2 - May, 2001
APW6020
www.anpec.com.tw
4
Electrical Characteristics Cont.
APW6020
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Unit
DAC and Standard Buck Regulator Reference
DAC(VID0-VID4) Input High Voltage
2.0
V
DACOUT Voltage accuracy
-1.0
+1.0
%
V
REG2
PWM2 Reference Voltage
SELECT<0.8V
1.5
V
V
REG2
PWM2 Reference Voltage
SELECT>2.0V
3.3
V
PWM2 Reference Voltage Tolerance
3
%
Linear Regulators (V
OUT3
and V
OUT4
)
Regulation (All Linears)
3
%
VREG
3
VSEN3 Regulation Voltage
1.5
V
VREG
4
VSEN4 Regulation Voltage
1.8
V
VSEN
UV
Under-Voltage Level (VSEN/ VREG)
VSEN Rising
75
%
Under-Voltage Hysteresis (VSEN/ VREG) VSEN Falling
7
%
Output Drive Current (All Liners)
V
DRIVE
=4.0V
20
40
mA
Synchronous PWM Controller Error Amplifier
DC Gain
88
dB
GBWP Gain-Bandwidth Product
15
MHz
SR
Slew Rate
COMP1=10pF
6
V/
s
PWM Controllers Gate Drivers
I
UGATE
UGATE1,2 Source
V
CC
=12V, V
UGATE 1,2
=6V
1
A
R
UGATE
UGATE1,2 Sink
V
UGATE1,2
=1V
3.5
I
LGATE
LGATE1 Source
V
CC
=12V, V
LGATE 1
=1V
1
A
R
LGATE
LGATE1 Sink
V
LGATE1
= 1V
3
Protection
VSEN1 Over-Voltage (VSEN1/DACOUT) VSEN1 Rising
115
120
%
I
OVP
FAULT Souring Current
V
FAULT/RT
=2.0V
8.5
mA
I
OCSET
OCSET1,2 Current Source
V
OCSET
= 4.5V
DC
170
200
230
A
I
SS
Soft Start Current
28
A
Power Good
VSEN1
Upper Threshold
(VSEN1/DACOUT)
VSEN1 Rising
108
110
%
VSEN1
Under Voltage (VSEN1/DACOUT) VSEN1 Rising
92
94
%
VSEN1
Hysteresis
(VSEN1 DACOUT)
Upper /Lower Threshold
2
%
V
PGOOD
PGOOD Voltage Low
I
PGOOD
= -4mA
0.8
V
Copyright
ANPEC Electronics Corp.
Rev. A.2 - May, 2001
APW6020
www.anpec.com.tw
5
Functional Pin Description
UGATE2 (Pin 1)
Connect UGATE2 pin to the standard BUCK PWM
converter's MOSFET gate. This pin provides the gate
drive for the MOSFET.
PHASE2 (Pin 2)
Connect the PHASE2 pin to the standard BUCK PWM
converter's MOSFET source. This pin is used to
monitor the voltage drop across the MOSFET for
over-current protection.
VID0 , VID1 , VID2 , VID3 , VID4 (Pins 7, 6 , 5 , 4 and
3)
VID0-4 are the TTL-compatible input pins to the 5-bit
DAC. The logic states of these five pins program the
internal voltage reference (DACOUT). The level of
DACOUT sets the microprocessor core converter
output voltage , as well as the coresponding PGOOD
and OVP thresholds.
PGOOD (Pin 8)
PGOOD is an open drain output used to indicate the
status of the output voltages. This pin is pulled low
when the synchronous regulator output is not within
10% of the DACOUT reference voltage or when any
of the other outputs are below their under-voltage
thresholds.
The PGOOD output is open for `11111' VID code.
OCSET2 (Pin 9)
Connect a resistor (R
OCSET
) from this pin to the drain
of the standard BUCK converter's MOSFET. R
OCSET
,
an internal 200
A current source (I
OCSET
) , and the
MOSFET's on-resistance(r
DS(ON)
) set the converter
over-current (OC) trip point according to the follow-
ing equation :
I
PEAK
=
An over-current trip cycles the soft-start function.
VSEN2 (Pin 10)
Connect this pin to the output of the standard Buck
PWM converter. The voltage at this pin is regulated
to the level predetermined by the logic-level status of
the SELECT pin. This pin is also monitored by the
PGOOD comparator circuit.
SELECT (Pin 11)
This pin determines the output voltage of the AGP
bus switching regulator. A low TTL input sets the
output voltage to 1.5V , while a high input sets the
output voltage to 3.3V.
SS (Pin 12)
Connect a capacitor from this pin to ground. This
capacitor , along with an internal 28
A current source
, sets the soft-start interval of the converter.
FAULT / RT (Pin 13)
This pin provides oscillator switching frequency
adjustment. By placing a resistor (R
T
) from this pin
to GND , the nominal 200kHz switching frequency is
increased. Conversely , connecting a pull-up resis-
tor (R
T
) from this pin to VCC reduces the switching
frequency.
Nominally , the voltage at this pin is 1.26V. In the
event of an over-voltage or over-current condition ,
this pin is internally pulled to VCC.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V
regulator. This pin is monitored for under-voltage
events.
DRIVE4 (Pin 15)
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the 1.8V regulator's
pass transistor.
VAUX (Pin 16)
The +3.3V input voltage at this pin is monitored for
I
OCSET
* R
OCSET
r
DS(ON)
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