Dual Synchronous DC/DC Controllers with Current Sharing Control
Copyright
ANPEC Electronics Corp.
Rev. A.3 - July., 2003
APW1175
www.anpec.com.tw
1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Pin Description
Features
Graphics Cards
DDR Memory
SSTL-2 Termination
Power Supply Requiring Two Outputs
Two Operation Modes
- Independent Operation
- Two-Phase Operation with Current Sharing
Driving N-Channel MOSFETs
300kHz Constant Frequency Operation
Built-in Feedback Compensation
- Voltage-Mode PWM Control
- Fast Transient Response
1% VREF Accuracy Over Temperature
Adjustable Output Voltage by an External Resistor
Divider
Phase-Shifted Switchers to Minimize Ripple
Current Limit with 50% Fold-Back
Soft-Start and Enable Function
Power-ON Reset (POR) Monitor
Power Good Monitor for Outputs
Applications
The APW1175 is a two-phase, synchronous, and voltage
mode PWM controller to provide dual channel or single
outputs in two distinct operation modes. In independent
mode, the two PWM converters supply two independently
regulated voltages by converting a common or two differ-
ent power inputs. In two-phase mode, the two PWM con-
verters supply one regulated voltage with programmable
current sharing control by converting a common or two
different power inputs. The two-phase mode can supply
the larger power than that provided each single channel.
APW1175 features an internal 300KHz oscillator, VCC
Power-On-Reset (POR), an external adjustable soft-start
and the programmable output current limit with 50% fold-
back. The two PWM controllers are 180
o
out of phase to
minimize the input ripple (common power input) and the
output ripple (two-phase mode).
4
5
6
7
8
9
10
1
2
3
VREF
+IN2
-IN2
VCC
CL2-
CL2+
BST2
DH 2
DL2
PGN D
17
16
15
14
13
12
11
20
19
18
GN D
PW RGD
-IN1
SS/ENA
CL1-
CL1+
BST1
DH 1
DL1
BSTC
)29 %#
Handling Code
Tem p. Range
Package Code
Package Code
K : SOP-20
Tem p. Range
C : 0 to 70C
Handling Code
TU : Tube TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Orginal Device
APW 1175 K :
APW 1175
XXXXX
XXXXX - Date Code
Lead Free Code
Ordering and Marking Information
General Description
Copyright
ANPEC Electronics Corp.
Rev. A.3 - July., 2003
APW1175
www.anpec.com.tw
2
Block Diagram
soft-start
control
PWRGD
SS/ENA
DH2
-IN2
4V
0.125V
0.125V
0.125V
+IN2
R
Q
S
S
Q
R
DL2
GND
DL1
DH1
BST1
BST2
PGND
VCC
VREF
-IN1
CL1-
CL1+
300KHZ
Slave Error
Amplifier
Master Error
Amplifier
OSC
V
CL1
CL2-
CL2+
V
CL2
BSTC
POWER-ON
RESET(POR)
R
Q
S
V
REF
1.25V
25uA
Absolute Maximum Ratings
Operating Conditions
VCC to GND . . . . . . . . . . . . . -0.3V ~ 15V
PGND to GND . . . . . . . . . . . . 1V
BST to GND . . . . . . . . . . . . . -0.3V ~ 22V
Junction Temperature . . . . . . . 150
o
C
Storage Temperature . . . . . . . -65
o
C ~ 150
o
C
Soldering Temperature . . . 300
o
C , 10 Seconds
Minimum ESD Rating . . . . . . . 3kV
VCC . . . . . . . . . . . . . . . . . . . . 4.2V ~ 15V
BST. . . . . . . . . . . . . . . . . . . . . 5V ~ 17V
Ambient Temperature Range . . . 0
o
C to 85
o
C
Junction Temperature Range. . . . 0
o
C to 125
o
C
Thermal Characteristics
Symbol
Parameter
Rating
Unit
R
JA
Thermal Resistance in Free Air
SOIC
SOIC(with 3in
of Copper)
75
65
C/W
Copyright
ANPEC Electronics Corp.
Rev. A.3 - July., 2003
APW1175
www.anpec.com.tw
3
Electrical Characteristics
APW 1175
Sym bol
Param eter
Test Conditions
M in
Typ
M ax
Unit
SUPPLY CURRENT
I
CC
V
CC
Supply C urrent
V
CC
=5~15V, F
OSC
=300kH z
9
m A
I
BSTC
BSTC Supply C urrent
BSTC =5V, D L1,2=O pen,
F
OSC
=300kH z
2.8
m A
I
BST1,2
BST1,2 Supply C urrent
BST1,2=10V, D H 1,2=O pen,
F
OSC
=300kH z
1.6
m A
PO W ER-O N RESET
V
CC
PO R Threshold Voltage V
CC
R ising
3.6
4.2
V
O SCILLATO R
F
OSC
O scillator Frequency
270
300
330
KH z
80
90
M axim um D uty C ycle
D H 1
D H 2
100
%
V
O SC
R am p Am plitude
1.1
V
ERRO R AM PLIFIER
A
OL
Error Am plifier Voltage G ain
35
dB
Input Bias C urrent
(-IN 1, +IN 2, -IN 2)
Input Voltage = 1.25V
0.5
1
A
REFERENCE VO LTAG E
V
REF
R eference Voltage
M easure Pin 1
1.238
1.250
1.262
V
V
REF
Load R egulation
I
REF
= 1m A
3.5
m V
V
REF
Line R egulation
V
CC
= 5~15V
0.5
%
PW M CO NTRO LLERS G AT E DRIVERS
D H Source
BSTH -D H =5V
BSTH -D H =2 .5V
1
0.5
A
D H Sink
D H -PG N D =3.5V
D H -PG N D =1.75V
1
0.5
A
D L Source
BSTL-D L=5V
BSTL-D L=2.5V
1
0.5
A
D L Sink
D L-PG N D =3.5V
D L-PG N D =1.75V
1
0.5
A
D ead Tim e
50
200
nS
CURRENT LIM IT PRO TEC TIO N
V
CL
C urrent Lim it Voltage
60
70
80
m V
Fold Back C urrent V
OUT
=0V (refer to application
circuit)
50%
I
LIM
Fold Back Voltage Knee
I=I
LIM
(refer to application circuit) 1.25
V
OUT
V
SO FT-START
I
SS
Soft-Start C urrent
V
SS
=1V
25
A
Soft-Start Transition
Synchronous PW M
3.3
V
Unless otherwise specified, these specifications apply over VCC=4.75~5.25V, GND=PGND=0V, and T
)
=0~85
C.
Typical values refer to T
)
=25
C.
Copyright
ANPEC Electronics Corp.
Rev. A.3 - July., 2003
APW1175
www.anpec.com.tw
4
APW1175
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
POWER GOOD
Upper -IN1 Threshold
110%
V
REF
Lower IN1 Threshold
90%
V
REF
Upper IN2 Threshold
V
+IN2
+0.1V
REF
V
Lower IN2 Threshold
90%
V
REF
PWRGD Voltage Low
I
PWRGD
=-5mA
0.8
V
Electrical Characteristics Cont.
VREF (Pin 1)
Internal 1.25V reference voltage . This pin is internally
connected to the positive input of the master channel
error amplifier.
+IN2 (Pin 2)
Positive input of the slave channel error amplifier. Con-
nect this pin to 1.25V reference (Pin 1) for the two
independent channel configuration.
-IN2, -IN1 (Pin 3, 18)
Negative inputs of the slave and master error amplifier.
VCC (Pin 4)
Connect this pin to 5V~15 V power to provides the
bias for the control circuitry. Need a 1uF multi-layer
ceramic decoupling capacitor to GND (Pin 20). The
voltage at this pin is also monitored for Power-On
Reset (POR) purpose.
CL2-, CL2+, CL1+, CL1- (Pin 5,6,15,16)
Current sense input pins. Connect the positive and
negative inputs to output current sense resistor for
each channel. A current limit comparator for each
channel to limit the output current while the difference
voltage between the positive and negaive inputs is
greater than the 75mV reference.
A RC filter is required for noise rejection.
BST2,BST1 (Pin 7,14)
Power inputs to the high-side MOSFET drivers. A boot-
strap circuit may be used to pump a boot voltage .
Functional Pin Description
DH2, DH1 (Pin 8,13)
High-side MOSFET drivers to provide strong drive current
to drive each high-side MOSFET. A small series resistor
to the gate of the MOSFET maybe required for each pin.
DL2, DL1 (Pin 9,12)
Low-side MOSFET drivers to provide strong drive current
to drive each low-side MOSFET. A small series resistor
to the gate of the MOSFET maybe required for each pin.
PGND (Pin 10)
Power ground connection. The pin provide the path for
return of gate drive currents.
BSTC (Pin 11)
This pin provide supply voltage to the low-side MOSFET
drivers.
SS/ENA (Pin 17)
Connect a capacitor from this pin to ground.This
capacitor, along with an internal 25uA current source,
sets the soft-start interval, preventing the outputs from
overshoot as well as limiting the input current. Pull this
pin to below 1.4V to shutdown the outputs
PWRGD (Pin 19)
Power good signal output pin. This pin is an open collec-
tor output, which is pulled low if the output voltage is out-
side the power good window.
GND (Pin 20)
Signal ground for the control circuitry. All voltage levels
are measured with respect to this pin.
Copyright
ANPEC Electronics Corp.
Rev. A.3 - July., 2003
APW1175
www.anpec.com.tw
5
Typical Application
1. Independent Operation
G N D
P W R G D
- IN 1
S S /E N A
C L 1 -
C L 1 +
B S T 1
D H 1
D L 1
B S T C
V R E F
+ IN 2
- IN 2
V C C
C L 2 -
C L 2 +
B S T 2
D H 2
D L 2
P G N D
+1
2
V
+5
V
+5
V
PW
R
O
K
2.
5
V
/
6
A
1.
8
V
/
6
A
C1
100
uF
16V
C2
100
uF
16V
C3
100
uF
16V
C1
8
150
uF
6V
C1
9
150
uF
6V
C2
0
150
uF
6V
C1
5
150
uF
6V
C1
6
150
uF
6V
C1
7
150
uF
6V
C1
2
150
uF
6V
C1
3
150
uF
6V
C1
4
150
uF
6V
R1
2.
2
R2
2.
2
R1
3
2.
2
R1
4
2.
2
R1
5
2.
2
R1
1
100
R1
2
6m
R1
0
100
R9
220
R8
124
R7
124
R6
6m
R5
100
R4
2.
2
R3
2.
2
C5
1uF
C2
2
1uF
C2
3
1nF
C1
1
10n
F
C8
10n
F
C9
10n
F
C1
0
0.
22u
F
C2
1
1uF
C4
0.
22u
F
D1
1N
414
8
D2
1N
414
8
Q1
A
P
M
441
6
Q2
A
P
M
441
6
L1
7.
5uH
L2
4.
7uH
C7
0.
22u
F
C6
10n
F
Q4
A
P
M
441
6
Q3
A
P
M
441
6
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