LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
(August, 2004, Version 3.2)
AMIC Technology, Corp.
Document Title
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History Issue
Date Remark
2.0 Change
V
CC
max
from 3.3V to 3.6V
January 25, 2002
Final
Add product family and 55ns specification
3.0
Add product family and 32-pin TSSOP reverse type package
April 16, 2003
3.1
Add 32-pin Pb-Free TSSOP forward package type
May 6, 2004
3.2
Add Pb-Free package type for all parts
August 9, 2004
LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
(August, 2004, Version 3.2)
1
AMIC Technology, Corp.
Features
Power supply range: 2.7V to 3.6V
Access times: 55ns / 70ns (max.)
Current:
Very low power version: Operating: 30mA (max.)
Standby: 10
A (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2V (min.)
Available in 32-pin TSOP/TSSOP 36-ball CSP package
General Description
The LP62S4096E-T is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words by 8
bits and operates on a low power supply range: 2.7V to 3.3V. It
is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for
direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2V.
CE2 pin for CSP package only
Product Family
Power Dissipation
Product
Family
Operating
Temperature
VCC
Range
Speed
Data
Retention
(I
CCDR
, Typ.)
Standby
(I
SB1
, Typ.)
Operating
(I
CC2
, Typ.)
Package Type
LP62S4096E-T
-25
C ~ +85
C
2.7V~3.6V
55ns / 70ns
0.08
A 0.3
A
5mA
32L TSOP
32L TSSOP
(Forward type)
32L TSSOP
(Reverse type)
36B CSP
1. Typical values are measured at VCC = 3.0V, T
A
= 25
C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
TSOP/(TSSOP)
TSSOP
CSP (Chip Size Package)
(forward type)
(reverse type)
36-pin Top View
LP62S4096EV-T
(LP62S4096EX-T)
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
A17
A15
VCC
A18
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
A0
I/O
5
I/O
6
GND
VCC
I/O
7
I/O
8
A9
A10
OE
A11
CE1
A12
A13
A14
A16
A18
A17
A15
I/O
4
I/O
3
I/O
2
I/O
1
GND
VCC
A1
A2
CE2
WE
NC
A5
A4
A3
A6
A7
A8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
LP62S4096EXR-T
16
1
32
17
LP62S4096E-T Series
(August, 2004, Version 3.2)
2
AMIC Technology, Corp.
Block Diagram
ROW
DECODER
1024 X 4096
MEMORY ARRAY
INPUT DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
I/O
8
I/O
1
A18
A17
A16
A0
VCC
GND
CE1
CE2
OE
WE
Pin Description
Symbol Description
A0 - A18
Address Inputs
I/O
1
- I/O
8
Data
Input/Outputs
GND Ground
CE1, CE2
Chip Enable
OE
Output Enable
WE
Write Enable
VCC
Power Supply
Recommended DC Operating Conditions
(T
A
= -25
C to + 85
C)
Symbol
Parameter Min.
Typ.
Max.
Unit
VCC Supply
Voltage
2.7 3.0 3.6 V
GND Ground
0
0
0 V
V
IH
Input High Voltage
2.2 -
VCC
+ 0.3
V
V
IL
Input Low Voltage
-0.3
0
+0.6
V
C
L
Output
Load
- - 30 pF
TTL Output
Load
-
- 1 -
LP62S4096E-T Series
(August, 2004, Version 3.2)
3
AMIC Technology, Corp.
Absolute Maximum Ratings*
VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -25
C to + 85
C
Storage Temperature, Tstg --------------- -55
C to + 125
C
Temperature Under Bias, Tbias ---------- -10
C to + 85
C
Power Dissipation, P
T
---------------------------------------- 0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
(T
A
= -25
C to + 85
C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter LP62S4096E-55LLT / 70LLT
Unit
Conditions
Min.
Typ.
Max.
I
LI
Input Leakage Current
-
-
1
A
V
IN
= GND to VCC
I
LO
Output Leakage Current
-
-
1
A
CE1= V
IH
, CE2= V
IL
or
OE = V
IH
WE =V
IL
V
I/O
= GND to VCC
I
CC
Active Power Supply Current
-
-
5
mA
CE1= V
IL
, CE2= V
IH
I
I/O
= 0mA
I
CC1
Dynamic Operating Current
-
20
30
mA
Min. Cycle, Duty = 100%,
CE1= V
IL
CE2= V
IH
, I
I/O
= 0mA
I
CC2
Dynamic Operating Current
-
5
15
mA
CE1= V
IL
, CE2= V
IH,
V
IH
= VCC
V
IL
= 0V, f = 1MH
Z
I
I/O
= 0mA
I
SB
Standby
Power
-
-
1 mA
VCC
3.3V
CE1= V
IH,
CE2= V
IL
I
SB1
Supply
Current
-
0.3 10
A VCC
3.3V
CE1
VCC - 0.2V, or CE2
0.2V
V
IN
0.2V
V
OL
Output Low Voltage
-
-
0.4
V
I
OL
= 2.1mA
V
OH
Output High Voltage
2.2
-
-
V
I
OH
= -1.0mA
Truth Table
Mode
CE1
CE2
OE
WE
I/O Operation
Supply Current
Standby H
X
X
X
High
Z I
SB
, I
SB1
Standby
X L X X
High
Z
I
SB
, I
SB1
Output Disable
L
H
H
H
High Z
I
CC,
I
CC1,
I
CC2
Read L
H
L
H
D
OUT
I
CC,
I
CC1,
I
CC2
Write L
H
X
L
D
IN
I
CC,
I
CC1,
I
CC2
Note: X = H or L
LP62S4096E-T Series
(August, 2004, Version 3.2)
4
AMIC Technology, Corp.
Capacitance
(T
A
= 25
C, f = 1.0MHz)
Symbol Parameter Min.
Max.
Unit
Conditions
C
IN
* Input
Capacitance
6 pF V
IN
= 0V
C
I/O
* Input/Output
Capacitance 8 pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= -25
C to + 85
C, VCC = 2.7V to 3.6V)
Symbol Parameter
LP62S4096E-55LLT
LP62S4096E-70LLT
Unit
Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time
55
-
70
-
ns
t
AA
Address Access Time
-
55
-
70
ns
t
ACE1,
t
ACE2
Chip Enable Access Time
-
55
-
70
ns
t
OE
Output Enable to Output Valid
-
30
35
ns
t
CLZ1,
t
CLZ2
Chip Enable to Output in Low Z
10
-
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ1,
t
CHZ2
Chip Disable to Output in High Z
0
20
0
25
ns
t
OHZ
Output Disable to Output in High Z
0
20
0
25
ns
t
OH
Output Hold from Address Change
5
-
5
-
ns
White Cycle
t
WC
Write Cycle Time
55
-
70
-
ns
t
CW1
Chip Enable to End of Write
50
-
60
-
ns
t
AS
Address Setup Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
50
-
60
-
ns
t
WP
Write Pulse Width
40
-
50
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
25
0
25
ns
t
DW
Data to Write Time Overlap
25
-
30
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
Notes: t
CHZ,
t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
LP62S4096E-T Series
(August, 2004, Version 3.2)
5
AMIC Technology, Corp.
Timing Waveforms
Read Cycle 1
(1)
t
RC
Address
t
AA
t
OE
t
OLZ5
t
OH
OE
t
OHZ5
D
OUT
t
ACE1 ,
t
ACE2
t
CHZ1 ,
t
CHZ2
t
CLZ1 ,
t
CLZ2
CE1
CE2
Read Cycle 2
(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
Read Cycle 3
(1, 3, 4)
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE1 = V
IL
or
CE2=
V
IH.
3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.
4.
OE = V
IL
.
5. Transition is measured
500mV from steady state. This parameter is sampled and not 100% tested.
t
ACS1 ,
t
ACS2
D
OUT
CS2
CS1
t
CHZ1 ,
t
CHZ2
t
CLZ1 ,
t
CLZ2
LP62S4096E-T Series
(August, 2004, Version 3.2)
6
AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
(4)
t
cw1
,t
cw2
t
AW
t
WR3
D
IN
t
OW7
t
DH
t
DW
t
WHZ7
t
WP2
t
AS1
D
OUT
WE
CE2
CE1
Write Cycle 2
(6)
(Chip Enable Controlled)
t
WC
Address
t
AW
t
WR3
(4)
t
CW1 ,
t
CW2
t
AS1
D
IN
t
DW
t
WHZ7
D
OUT
t
DH
t
WP2
WE
CE2
CE1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low CE1 or high CE2 , and a low WE .
3.
t
WR
is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the Write
cycle.
4.
If
the
CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition,
outputs remain in a high impedance state.
5.
t
CW
is measured from the later of CE1 going low or CE2 going high to the end of Write.
6.
OE level is high or low.
7. Transition is measured
500mV from steady state. This parameter is sampled and not 100% tested.
LP62S4096E-T Series
(August, 2004, Version 3.2)
7
AMIC Technology, Corp.
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
30pF
* Including scope and jig.
* Including scope and jig.
C
L
TTL
5pF
C
L
TTL
Figure 1. Output Load
Figure 2. Output Load for t
CLZ
,
t
OHZ
, t
OL
, t
CHZ
, t
WHZ
, and t
OW
Data Retention Characteristics
(T
A
= -25
C to 85
C)
Symbol Parameter Min.
Typ.
Max.
Unit
Conditions
V
DR
VCC for Data Retention
2.0
-
3.6
V
CE1
VCC - 0.2V, or
CE2
0.2V
VCC = 2.0V,
I
CCDR
Data Retention Current
LL-Version
-
0.08
3*
A
CE1
VCC - 0.2V, or
CE2
0.2V
V
IN
0V
t
CDR
Chip Disable to Data Retention Time
0
-
-
ns
t
R
Operation Recovery Time
t
RC
-
-
ns
See Retention Waveform
t
VR
VCC Rising Time from Data Retention Voltage to
Operating Voltage
5 - - ms
* LP62S4096E-55LLT / 70LLT
I
CCDR
: max. 1
A at T
A
= 0
C to + 40
C
LP62S4096E-T Series
(August, 2004, Version 3.2)
8
AMIC Technology, Corp.
Low VCC Data Retention Waveform (1) (
CE1 Controlled)
VCC
t
CDR
V
IH
2.7V
t
R
V
IH
2.7V
DATA RETENTION MODE
V
DR
2V
CE1
V
DR
- 0.2V
t
VR
CE1
Low VCC Data Retention Waveform (2) (CE2 Controlled)
VCC
CE2
t
CDR
V
IL
2.7V
t
R
V
IL
2.7V
DATA RETENTION MODE
t
VR
V
DR
2V
0.2V
CE2
LP62S4096E-T Series
(August, 2004, Version 3.2)
9
AMIC Technology, Corp.
Ordering Information
Part No.
Access Time
(ns)
Operating Current
Max.(mA)
Standby Current
Max.(uA)
Package
LP62S4096EV-55LLT
32L TSOP
LP62S4096EV-55LLTF
32L Pb-Free TSOP
LP62S4096EX-55LLT
32L TSSOP (Forward)
LP62S4096EX-55LLTF
32L Pb-Free TSSOP (Forward)
LP62S4096EXR-55LLT
32L TSSOP (Reverse)
LP62S4096EXR-55LLTF
32L Pb-Free TSSOP (Reverse)
LP62S4096EU-55LLT
36L CSP
LP62S4096EU-55LLTF
55 30
10
36L Pb-Free CSP
LP62S4096EV-70LLT
32L TSOP
LP62S4096EV-70LLTF
32L Pb-Free TSOP
LP62S4096EX-70LLT
32L TSSOP (Forward)
LP62S4096EX-70LLTF
32L Pb-Free TSSOP (Forward)
LP62S4096EXR-70LLT
32L TSSOP (Reverse)
LP62S4096EXR-70LLTF
32L Pb-Free TSSOP (Reverse)
LP62S4096EU-70LLT
36L CSP
LP62S4096EU-70LLTF
70 30
10
36L Pb-Free CSP
LP62S4096E-T Series
(August, 2004, Version 3.2)
10
AMIC Technology, Corp.
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
e
L
E
L
GAUGE PLANE
A
A
2
c
0.
25
BSC
Detail "A"
D y
Detail "A"
S
A
1
b
H
D
D
E
0.10(0.004)
M
12.0
Symbol
Dimensions in inches
Dimensions in mm
A
0.047 Max.
1.20 Max.
A
1
0.0040.002
0.100.05
A
2
0.0390.002
1.000.05
b 0.0080.001
0.200.03
c 0.0060.001
0.150.02
D 0.7240.004
18.400.10
E 0.3150.004
8.000.10
e
0.020 TYP.
0.50 TYP.
H
D
0.7870.007
20.000.20
L 0.0200.004
0.500.10
L
E
0.031 TYP.
0.80 TYP.
S
0.0167 TYP.
0.425 TYP.
Y
0.004 Max.
0.10 Max.
0
~ 6
0
~ 6
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference
only.
4. Dimension S includes end flash.
LP62S4096E-T Series
(August, 2004, Version 3.2)
11
AMIC Technology, Corp.
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Forward Type)
unit: inches/mm
e
Detail "A"
D
0.10MM
Detail "A"
S
b
D
1
E
D
L
E
L
GAUGE PLANE
A
A
2
c
0.
25
BSC
Detail "A"
A
1
SEATING PLANE
12.0
1
16
17
32
Symbol
Dimensions in inches
Dimensions in mm
A
0.049 Max.
1.25 Max.
A
1
0.002 Min.
0.05 Min.
A
2
0.0390.002
1.000.05
b 0.0080.001
0.200.03
c 0.0060.0003
0.150.008
E 0.3150.004
8.000.10
e
0.020 TYP.
0.50 TYP.
D 0.5280.008
13.400.20
D
1
0.4650.004
11.800.10
L 0.020.008
0.500.20
L
E
0.0266 Min.
0.675 Min.
S
0.0109 TYP.
0.278 TYP.
y
0.004 Max.
0.10 Max.
0
~ 6
0
~ 6
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference
only.
4. Dimension S includes end flash.
LP62S4096E-T Series
(August, 2004, Version 3.2)
12
AMIC Technology, Corp.
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Reverse Type)
unit: inches/mm
e
D
1
E
D
L
E
L
GAUGE PLANE
A
A
2
c
0.
25
BSC
Detail "A"
A
1
12.0
S
b
D
0.10MM
Detail "A"
SEATING PLANE
1
16
17
32
Symbol
Dimensions in inches
Dimensions in mm
A
0.049 Max.
1.25 Max.
A
1
0.002 Min.
0.05 Min.
A
2
0.0390.002
1.000.05
b 0.0080.001
0.200.03
c 0.0060.0003
0.150.008
E 0.3150.004
8.000.10
e
0.020 TYP.
0.50 TYP.
D 0.5280.008
13.400.20
D
1
0.4650.004
11.800.10
L 0.020.008
0.500.20
L
E
0.0266 Min.
0.675 Min.
S
0.0109 TYP.
0.278 TYP.
y
0.004 Max.
0.10 Max.
0
~ 6
0
~ 6
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e
1
is for PC Board surface mount pad pitch design
reference
only.
4. Dimension S includes end flash.
LP62S4096E-T Series
(August, 2004, Version 3.2)
13
AMIC Technology, Corp.
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C
SEATING PLANE
//
0.
25
C
A
(
0
.
36)
A
B
C
D
E
F
G
H
1 2 3 4 5 6
1
2
3
4
5
6
C
0.10
C
S
0.25
S
A B
b (36X)
BOTTOM VIEW
Ball*A1 CORNER
E
E
1
e
B
e
D
1
D
A
0.20(4X)
0.
10
C
Dimensions in mm
Symbol
MIN.
NOM.
MAX.
A 1.00
1.10
1.20
A
1
0.16
0.21
0.26
A
2
0.48
0.53
0.58
D 5.80
6.00
6.20
E 7.80
8.00
8.20
D
1
---
3.75
---
E
1
---
5.25
---
e ---
0.75
---
b 0.25
0.30
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS
0.25mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS
0.25mm (NSMD)
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