LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
(August, 2002, Version 2.1)
AMIC Technology, Inc.
Document Title
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
2.0
Add product family and 32-pin TSSOP package
May 9, 2002
Final
2.1
Add 36 ball BGA package type
August 22, 2002
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
(August, 2002, Version 2.1)
1
AMIC Technology, Inc.
Features
General Description
n
Single +3.3V power supply
n
Access times: 12/15 ns (max.)
n
Current: Operating: 170mA (max.)
Standby: 10mA (max.)
n
Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL compatible
n
Common I/O using three-state output
n
Output enable and two chip enable inputs for easy
application
n
Data retention voltage: 2.0V (min.)
n
Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32-
pin TSSOP and 36-pin CSP packages
The LP61L1024 is a low operating current 1,048,576-bit
static random access memory organized as 131,072 words
by 8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
Product Family
Power Dissipation
Product
Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(I
CCDR
, Typ.)
Standby
(I
SB1
, Typ.)
Operating
(I
CC1
, Typ.)
Package
Type
LP61L1024
0
C ~ 70
C
3V ~ 3.6V
12/15 ns
0.4mA
0.5mA
130mA
32L SOJ
32L TSOP
32L TSSOP
36B
BGA
1. Typical values are measured at VCC = 3.0V, T
A
= 25
C and not 100% tested.
2. Data retention current VCC = 2.0V.
LP61L1024
(August, 2002, Version 2.1)
2
AMIC Technology, Inc.
Pin Configurations
n
n
SOJ
n
n
TSOP / TSSOP
n
n
CSP (Chip Size Package)
36-pin Top View
Block Diagram
VCC
GND
DECODER
256 X 4096
MEMORY ARRAY
INPUT
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
A0
A14
A15
A16
I/O
1
I/O
8
CE2
CE1
OE
WE
Pin Description
Pin No.
Symbol
Description
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
29
WE
Write Enable
24
OE
Output Enable
22
CE1
Chip Enable
30
CE2
Chip Enable
1
NC
No Connection
13 - 15, 17 - 21
I/O
1
- I/O
8
Data Input/Outputs
32
VCC
Power Supply
16
GND
Ground
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
CE1
A10
OE
A9
A8
A13
WE
CE2
A15
VCC
A11
LP61L1024S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LP61L1024V(X)
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
CE2
A15
VCC
NC
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
A0
I/O
4
I/O
5
GND
VCC
I/O
6
I/O
7
A9
A10
OE
A11
CE1
A12
A13
A14
A16
NC
NC
A15
I/O
3
I/O
2
I/O
1
I/O
0
GND
VCC
A1
A2
NC
WE
NC
A5
A4
A3
A6
A7
A8
6
5
4
3
2
1
A
B
C
D
E
F
G
H
LP61L1024
(August, 2002, Version 2.1)
3
AMIC Technology, Inc.
Recommended DC Operating Conditions
(T
A
= 0
C to + 70
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
VCC + 0.3
V
V
IL
Input Low Voltage
-0.3
0
+0.8
V
C
L
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
Absolute Maximum Ratings*
VCC to GND .............................................. -0.5V to +7.0V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0
C to +70
C
Storage Temperature, Tstg..................... -55
C to +125
C
Temperature Under Bias, Tbias................ -10
C to +85
C
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260
C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics
(T
A
= 0
C to + 70
C, VCC = 3.3V + 10%, GND = 0V)
Symbol
Parameter
LP61L1024-12/15
Unit
Conditions
Min.
Max.
I
LI
Input Leakage Current
-
2
A
V
IN
= GND to VCC
I
LO
Output Leakage Current
-
2
A
CE1 = V
IH
or CE2 = V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= GND to VCC
I
CC1
(1)
Dynamic Operating Current
-
170
mA
CE1 = V
IL
, CE2 = V
IH
I
I/O
= 0 mA
I
SB
-
30
mA
CE1 = V
IH
or CE2 = V
IL
I
SB1
Standby Power
Supply Current
-
10
mA
CE1
VCC - 0.2V,
CE2
VCC - 0.2V,
V
IN
0.2V or V
IN
VCC - 0.2V
I
SB2
-
10
mA
CE1
0.2V, CE2
0.2V
V
IN
0.2V or V
IN
VCC - 0.2V
V
OL
Output Low Voltage
-
0.4
V
I
OL
= 8 mA
V
OH
Output High Voltage
2.4
-
V
I
OH
= -4 mA
Note: 1. I
CC1
is dependent on output loading, cycle rates, and Read/Write patterns
LP61L1024
(August, 2002, Version 2.1)
4
AMIC Technology, Inc.
Truth Table
Mode
CE1
CE2
OE
WE
I/O Operation
Supply Current
Standby
H
X
X
X
High Z
I
SB
, I
SB1
X
L
X
X
High Z
I
SB
, I
SB2
Output Disable
L
H
H
H
High Z
I
CC1
Read
L
H
L
H
D
OUT
I
CC1
Write
L
H
X
L
D
IN
I
CC1
Note: X = H or L
Capacitance
(T
A
= 25
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
8
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
10
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0
C to +70
C, VCC = 3.3V + 10, GND = 0V)
Symbol
Parameter
LP61L1024-12
LP61L1024-15
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
12
-
15
-
ns
t
AA
Address Access Time
-
12
-
15
ns
t
ACE1
Chip Enable Access Time
CE1
-
12
-
15
ns
t
ACE2
CE2
-
12
-
15
ns
t
OE
Output Enable to Output Valid
-
7
-
9
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
3
-
5
-
ns
t
CLZ2
CE2
3
-
5
-
ns
t
OLZ
Output Enable to Output in Low Z
2
-
2
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
-
7
-
10
ns
t
CHZ2
CE2
-
7
-
10
ns
t
OHZ
Output Disable to Output in High Z
2
7
2
9
ns
t
OH
Output Hold from Address Change
3
-
5
-
ns
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