A8351601 Series

Bar Code Reader

(July, 2002, Version 1.0)

AMIC Technology, Inc.

Document Title

Bar Code Reader

Revision History

Rev. No. History

Issue Date

Remark

0.0

Initial issue

June 5, 2000

Preliminary

0.1

Change document title from "Bar Code Reader" to

June 22, 2000

"8 Bit Microcontroller"

Error correction:

(1) Delete single-step operation description

(2) Delete "the only exit from power down is a hardware

reset" on page 32

0.2

Modify 44L QFP package outline drawing and dimensions

November 15, 2000

0.3

Modify PWM function

January 17, 2001

(1) Add PWM3 delay control bits D0, D1 and D2

(2) Add PWM4 output control bit PWM1.7

0.4

Error correction:

June 6, 2001

Delete Functional Description

0.5

Change document title from "8 Bit Microcontroller" to

October 16, 2001

"Bar Code Reader"

0.6

Modify AC, DC Electrical Characteristics:

February 19, 2002

Add 3V

�

10% condition

1.0

SFR Map address has some typewriting errors

July 12, 2002

Final

Modify DC and AC Electrical Characteristics

Final version release

A8351601 Series

Bar Code Reader

(July, 2002, Version 1.0)

AMIC Technology, Inc.

Features

80C32 CPU core

Build in 64K byte OTP ROM

Build in 8K byte external SRAM (0000H - 1FFFH), can
be disable by SFR

Fully pin compatible with standard 8051 family interface

Instruction set compatible with 8051 family

Option frequency 4.5V-5.5V:0-40MHz, 2.7V-3.3V:0-16MHz

Power saving operation:

Idle is compatible with 8051 family
Power down can be wake up by external interrupt

Port0~Port3 with internal pull-up

Four channel PWM output for PLCC & QFP package

Capture function with T2EX reversed mode

Operation temperature: -10

�

C~70

�

ESD > 3KV

Double frequency selected by SFR

General Description

The AMIC A8351601 is a high-performance 8-bit
microcontroller. It is compatible with the industry standard
80C52 microcontroller series.
The A8351601 contains a on chip 256 byte RAM, 64K byte
OTP ROM, 8K byte external data SRAM, four 8-bit

bidirectional parallel ports, three 16-bit timer/counters, a
serial port and six interrupt sources with two priority levels.
The A8351601 has supports 64KB external data memory.

A8351601 Series

(July, 2002, Version 1.0)

AMIC Technology, Inc.

T2,P1.0

T2EX,P1.1

P1.2

TXD,P3.1

XTAL2
XTAL1

GND

P0.2,AD2

P0.1,AD1

P0.0,AD0

VCC

A8351601

P0.3,AD3

P1.3
P1.4

P1.6

P1.7
RST

RXD,P3.0

T1,P3.5

INT0,P3.2

P1.5

PSEN

ALE

P0.7,AD7

P0.6,AD6

P0.5,AD5

P0.4,AD4

16
17

13
14
15

A8351601L

P1.5

P1.4

INT1,P3.3

T0,P3.4

WR,P3.6

RD,P3.7

P2.7,A15
P2.6,A14
P2.5,A13
P2.4,A12
P2.3,A11
P2.2,A10
P2.1,A9
P2.0,A8

P1.3

P1.2

P1.1,T2EX

P1.0,T2

PWM1

VCC

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

P1.6
P1.7

RST

RXD,P3.0

PWM2

TXD,P3.1

INT0, P3.2

INT1,P3.3

T0,P3.4

T1,P3.5

P0.4,AD4

EA
PWM4
ALE

PSEN

P2.7,A15
P2.6,A14
P2.5,A13

39
38
37

36
35

34
33

32
31

30
29

7
8

9
10

13
14

15
16
17

P0.5,AD5
P0.6,AD6
P0.7,AD7

WR,P3.6

RD,P3.7

XTAL2

XTAL1

GND

PWM3

P2.0,A8

P2.1,A9

P2.2,A10

P2.3,A11

P2.4,A12

Pin Configurations

P-DIP

PLCC

QFP

A8351601F

P1.5

P1.4

P1.3

P1.2

P1.1,T2EX

P1.0,T2

PWM1

VCC

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

P1.6
P1.7

RST

RXD,P3.0

PWM2

TXD,P3.1

INT0, P3.2

INT1,P3.3

T0,P3.4

T1,P3.5

P0.4,AD4

EA
PWM4
ALE

PSEN
P2.7,A15
P2.6,A14
P2.5,A13

32
31

30
29

28
27

26
25

24
23

1
2

3
4

7
8

9
10
11

P0.5,AD5
P0.6,AD6
P0.7,AD7

WR,P3.6

RD,P3.7

XTAL2

XTAL1

GND

PWM3

P2.0,A8

P2.1,A9

P2.2,A10

P2.3,A11

P2.4,A12

A8351601 Series

(July, 2002, Version 1.0)

AMIC Technology, Inc.

Pin Description

Pin No.

Symbol

P-DIP

PLCC

QFP

I/O

Description

ALE

Address Latch Enable: Output pulse for latching the low
byte of the address during an address to the external
memory. In normal operation, ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory.

External Access enable:

must be externally held low

to enable the device to fetch code from external program
memory locations 0000H to FFFFH. If

is held high, the

device executes from internal program memory.

P0.0-P0.7

32-39

36-43

30-37

I/O

Port 0: Port 0 is an 8-bit bidirectional I/O port with internal
pullups. Port 0 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.

1-8

2-9

40-44

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current because of the internal pullups. (See DC
Characteristics: I

The Port 1 output buffers can sink/source four TTL inputs.

T2 (P1.0): Timer/Counter 2 external count input.

P1.0-P1.7

T2EX (P1.1): Timer/Counter 2 trigger input.

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current because of the internal pullups. (See DC
Characteristics: I

Port 2 emits the high order address byte during fetches
from external program memory and during accesses to
external data memory that used 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]),
Port 2 emits the contents of the P2 Special Function
Register.
Port 2 also receives the high-order bits and some control
signals during ROM verification.

Электронный компонент: A8351601