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A64E06161
Preliminary
1M X 16 Bit Low Voltage Super RAM
Document Title
1M X 16 Bit Low Voltage Super RAM
Revision History
Rev. No. History Issue
Date Remark
0.0 Initial
issue
October 12, 2003
Preliminary
0.1
Change VCC range and VCCQ range
November 30, 2004
Change page access time from 20ns to 25ns
Change operation current (I
CC1
) from 25mA to 15mA(-70)
Change operation current (I
CC1
) from 20mA to 12mA(-85)
Change standby current (I
SB1
) from 80uA to 100uA
Delete reduce memory size 16M, partial array refresh 16M
Change operation current (I
CC2
) form 5mA to 3mA(-70, -85)
Change PAR current 12Mb=90uA, 8Mb=80uA, 4Mb=70uA
Change TCR current +85
C=100uA +70C=90uA
Change TCR current +45
C=85uA +15C=75uA
PRELIMINARY
(November, 2004, Version 0.1)
AMIC Technology, Corp.
A64E06161
Preliminary
1M X 16 Bit Low Voltage Super RAM
Features
Operating voltage:
VCC: 1.7V to 1.95V
VCCQ: 1.7V to VCC
Access times: t
AA
= 70ns (max.)
Page Access times: t
PAA
= 25ns (max)
Current:
A64E06161 series:
Operating Current (Icc1) : 15mA (max.)
Standby Current (Isb1) : 100uA (max)
Deep Power Down Standby Current (I
ZZ
) : 10
A (max.)
4-word page length
Support 4 distinct operation modes for reducing standby
power :
Deep Power Down (DPD) mode
Reduce Memory Size (RMS) mode (4M, 8M, 12M)
Partial Array Refresh (PAR) mode (4M,8M,12M)
Temperature Compensated Refresh (TCR) mode
Industrial operating temperature range: -25
C to +85C
for I
Available in 48-ball Mini BGA (6X8) package.
General Description
The A64E06161 is a low operating current 16,777,216-bit
super RAM organized as 1,048,576 word by 16bit and
operated on low power supply voltage from 1.7V to 1.95V.
It is built using AMIC's high performance CMOS DRAM
process.
Using hidden refresh technique, the A64E06161 provides a
compatible asynchronous interface and data can be read in
4-word page mode for fast access times. The A64E06161
has an internal register named the Configuration Register
(CR) that controls the operation. The A64E06161 is
designed for reducing current consumption during hidden
self refresh and operating through following mode: Deep
Power Down (DPD) mode, Reduce Memory Size (RMS)
mode, Partial Array Refresh (PAR) mode and Temperature
Compensated refresh (TCR) mode.
This A64E06161 is suited for low power application such as
mobile phone and PDA or other battery-operated handheld
device.
Pin Configuration
Mini BGA (6X8) Top View
1 2 3 4 5 6
A
LB
OE
A0 A1 A2 ZZ
B
I/O
8
HB
A3 A4 CE
I/O
0
C
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
D
VSSQ
I/O
11
A17
A7 I/O
3
VCC
E
VCCQ
I/O
12
NC A16
I/O
4
VSS
F
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
G
I/O
15
A19
A12
A13
WE
I/O
7
H
A18
A8
A9
A10
A11
NC
A64E06161G
PRELIMINARY
(November, 2004, Version 0.1)
1
AMIC Technology, Corp.
A64E06161
Block Diagram
DECODER
16,777,216
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
VCC
VCCQ
I/O
7
I/O
0
A19
A18
A0
WE
HB
INPUT
DATA
CIRCUIT
I/O
8
I/O
15
ZZ
LB
OE
CE
VSS
VSSQ
Pin Description
Symbol Description
A0 - A19
Address Inputs
CE
Chip Enable Input
ZZ
Sleep Enable Input
(When
ZZ
is low, the CR register can be
loaded or the device can enter DPD mode or
PAR mode).
I/O
0
- I/O
15
Data
Input/Outputs
WE
Write Enable Input
LB
Byte Enable Input (I/O
0
to I/O
7
)
HB
Byte Enable Input (I/O
8
to I/O
15
)
OE
Output Enable Input
VCC Power
VSS Ground
VCCQ
Provide isolated power to I/O for improved
noise immunity
VSSQ
Provide isolated / Ground to I/O for improved
noise immunity
NC
No Connection or VSSQ
PRELIMINARY
(November, 2004, Version 0.1)
2
AMIC Technology, Corp.
A64E06161
Recommended DC Operating Conditions
(T
A
= 0
C to + 70C or -25C to 85C)
Symbol Parameter Min.
Max.
Unit
VCC Supply
Voltage
1.7 1.95
V
VSS Ground
0
0
V
VCCQ
Supply Voltage I/O only
1.7
VCC
V
VSSQ
Ground I/O only
0
0
V
V
IH
Input High Voltage
1.4
VCCQ + 0.2
V
V
IL
Input Low Voltage
-0.2
+0.4
V
C
L
Output
Load
- 30 pF
Absolute Maximum Ratings*
VCC to VSS . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
VCCQ to VSSQ . . . . . . . . . . . . . . . -0.3V to VCCQ+0.3V
IN, IN/OUT Volt to GND . . . . . . . . -0.3V to VCCQ + 0.3V
Storage Temperature, Tstg . . . . . . . . -55
C to +125C
Power Dissipation, P
T
. . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260
C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(T
A
= 0
C to + 70C or -25C to 85C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V)
Symbol Parameter
-70
-85
Unit Conditions
Min. Max. Min. Max.
I
LI
Input Leakage Current
- 1 - 1
A
V
IN
= GND to VCCQ
I
LO
Output Leakage
Current
- 1 - 1
A
CE
= V
IH
or
ZZ
= V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= GND to VCCQ
I
CC1
-
15
-
12
mA
Min. Cycle, Duty = 100%
CE
= V
IL
,
ZZ
= V
IH
V
IH
= VCCQ, V
IL
= 0V,
I
I/O
= 0mA
I
CC2
Dynamic Operating
Current
- 3 - 3
mA
CE
= V
IL
,
ZZ
= V
IH
V
IH
= VCCQ, V
IL
= 0V,
f = 1MHz, I
I/O
= 0mA
I
SB1
Standby Power
Supply Current
- 100 - 100
A
CE
VCCQ - 0.2V
ZZ
VCCQ - 0.2V
V
IN
0V
V
OL
Output Low Voltage
-
0.2
-
0.2
V
I
OL
= 0.2 mA
V
OH
Output High Voltage
VCCQ-0.2
-
VCCQ-0.2
-
V
I
OH
= -0.2mA
PRELIMINARY
(November, 2004, Version 0.1)
3
AMIC Technology, Corp.
A64E06161
Deep Power Down Specifications and Conditions
Symbol Description
Conditions
Typ. Max.
Units
I
ZZ
Deep Power-Down
V
IN
= VCCQ or 0V; +25
C
ZZ
=
LOW
CR[4] = 0
10
A
Partial Array Refresh Specifications Conditions
Symbol Description
Conditions Density
Array
Partition
Typ. Max.
Units
12Mb
3/4
90
A
8Mb 1/2 80
A
I
PAR
Partial Array Refresh
Current
V
IN
= VCCQ or 0V
ZZ
= LOW
CR[4] = 1
4Mb 1/4 70
A
Note:
I
PAR
(MAX) values measured with TCR set to 85
C
Temperature Compensated Refresh Specifications Conditions
Symbol Description
Conditions Density
Max Case
Temperatures
Typ. Max.
Units
+85
C
100
A
+70
C
90
A
+45
C
80
A
I
TCR
Temperature
Compensated Refresh
Standby Current
V
IN
= VCCQ or 0V
Chip Disabled
16Mb
+15
C
70
A
Note:
1. I
TCR
(MAX) values measured with FULL ARRAY refresh.
2. This device assumes a standby mode if the chip is disabled (
CE
HIGH).
Truth Table
CE
ZZ
OE
WE
LB
HB
I/O
0
to I/O
7
Mode
I/O
8
to I/O
15
Mode
VCC Current
H H X X X X
Not
selected Not
selected I
SB1
H L X X X X
Not
selected Not
selected I
ZZ
*2
H L X X X X
Not
selected Not
selected IPAR*2
L
L
X
L
X
X
Not selected
Not selected
Load CR Register
L L
Read
Read
I
CC1
, I
CC2
L H L H L H
Read
High
-
Z
I
CC1
, I
CC2
H
L
High
-
Z
Read
I
CC1
, I
CC2
L L
Write
Write
I
CC1
, I
CC2
L
H
X
L
L
H
Write
Not Write/Hi - Z
I
CC1
, I
CC2
H
L
Not
Write/Hi
-
Z
Write
I
CC1
, I
CC2
L
H
H
H
X
X
High - Z
High - Z
ICC1, ICC2
Note: 1. X = H or L
2. DPD is enable when CR register A4 is "0"; otherwise, PAR is enable
PRELIMINARY
(November, 2004, Version 0.1)
4
AMIC Technology, Corp.
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