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A43L4616
4M X 16 Bit X 4 Banks Synchronous DRAM
(September, 2004, Version 0.0)
AMIC Technology, Corp.
Document Title
4M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No. History Issue
Date Remark
0.0
Initial issue
September, 2004
A43L4616
4M X 16 Bit X 4 Banks Synchronous DRAM
(September, 2004, Version 0.0)
1
AMIC Technology, Corp.
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 143MHz @ CL=3, 133Mhz @ CL=2
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
54 Pin TSOP (II)
General Description
The A43L4616 is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 X 4,194,304 words by
16 bits, fabricated with AMIC's high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
TSOP (II)
A43L4616V
54 53 52 51 50 49 48 47 46 45
43
44
42 41 40 39 38 37 36 35 34 33 32 31 30
1
2
3
4 5
6
7
8
9 10
12
11
13 14 15 16 17 18 19 20 21 22 23 24 25
VS
S
DQ
15
VSSQ
DQ
14
DQ
13
VD
DQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
VDDQ
DQ
8
VSS
UD
Q
M
CK
CK
E
A12
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ
0
VD
DQ
DQ
1
DQ
2
VS
SQ
DQ
3
DQ
4
VD
DQ
DQ
5
DQ
6
VSSQ
DQ
7
VD
D
LD
Q
M
WE
CA
S
RA
S
CS
A1
0
/
A
P
BS
1
BS
0
A0
A1
A2
26 27
28
29
A3
VDD
A1
1
NC
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Block Diagram
Bank Select
Ro
w B
u
ff
er
Ref
r
es
h
C
o
un
t
e
r
Add
r
es
s Re
g
i
st
e
r
Row Decod
e
r
Col
u
mn Bu
ffe
r
LCBR
LRAS
CLK
ADD
Timing Register
Data Input Register
4M X 16
Se
nse AM
P
Column Decoder
Latency & Burst Length
Programming Register
LRAS
LCAS
LRAS
LCBR
LWE
LWCBR
DQM
CLK
CKE
CS
RAS
CAS
WE
DQM
I/
O
Co
n
t
r
o
l
O
u
t
p
ut
Bu
ff
er
LWE
DQM
DQi
4M X 16
4M X 16
4M X 16
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Pin Descriptions
Symbol Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
A0~A12 Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA12, Column address: CA0~CA8
BS0, BS1
Bank Select Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power
Supply/Ground
Power Supply: +3.3V
0.3V/Ground
VDDQ/VSSQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU No
Connection
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
C to +150
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if "Absolute Maximum
Ratings" are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (T
A
=25
C, f=1MHz)
Parameter Symbol
Condition
Min
Typ
Max
Unit
Input Capacitance
CI1
A0 to A12, BS0, BS1
2.5
3.8
pF
CI2
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
DQM
2.5 3.8
pF
Data Input/Output Capacitance
CI/O
DQ0 to DQ15
4
6.5
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, T
A
= 0C to +70C )
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply
Voltage
VDD,VDDQ
3.0 3.3 3.6 V
Input High Voltage
V
IH
2.0 3.0
VDD+0.3
V
Input Low Voltage
V
IL
-0.3 0 0.8 V Note
1
Output High Voltage
V
OH
2.4 -
- V
I
OH
= -2mA
Output Low Voltage
V
OL
- - 0.4 V
I
OL
= 2mA
Input Leakage Current
I
IL
-5 - 5
A
Note 2
Output Leakage Current
I
OL
-5 - 5
A
Note 3
Output Loading Condition
See Figure 1
Note:
1. V
IL
(min) = -1.5V AC (pulse width
5ns).
2. Any input 0V
VIN
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
Vout
VDD
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
C
DC1
0.1 + 0.01
F
Decoupling Capacitance between VDDQ and VSSQ
C
DC2
0.1 + 0.01
F
Note:
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C )
Speed
Symbol Parameter
Test
Conditions
-7
Unit
Notes
I
cc1
Operating Current
(One Bank Active)
Burst Length = 1
t
RC
t
RC
(min), t
CC
t
CC
(min
)
, I
OL
= 0mA
80
mA
1
I
cc2
P
CKE
V
IL
(max), t
CC
= 15ns
2
I
cc2
PS
Precharge Standby Current
in power-down mode
CKL
VIL(max), t
CC
=
1
mA
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
40
I
CC2
NS
Precharge Standby Current
in non power-down mode
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable.
15
mA
I
CC3
N
Active Standby current in
non power-down mode
(One Bank Active)
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
60 mA
I
CC4
Operating Current
(Burst Mode)
I
OL
= 0mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
100
mA
1
I
CC5
Refresh
Current
t
RC
t
RC
(min)
170
mA
2
I
CC6
Self Refresh Current
CKE
0.2V
3 mA
Note:
1. Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2. Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
AC Operating Test Conditions
(VDD = 3.3V
0.3V, T
A
= 0
C to +70
C )
Parameter Value
AC input levels
V
IH
/V
IL
= 2.4V/0.4V
Input timing measurement reference level
1.4V
Input rise and all time (See note3)
tr/tf = 1ns/1ns
Output timing measurement reference level
1.4V
Output load condition
See Fig.2
Output
870
1200
(Fig. 1) DC Output Load Circuit
Z
O
=50
OUTPUT
50
V
TT
=1.4V
50pF
(Fig. 2) AC Output Load Circuit
3.3V
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
AC Characteristics
(AC operating conditions unless otherwise noted)
-7
Symbol Parameter CAS
Latency
Min Max
Unit Note
3 7
t
CC
CLK cycle time
2 7.5
1000 ns 1
t
SAC
CLK to valid
Output delay
- 5.4
ns
1,2
t
OH
Output data hold time
3
-
ns
2
t
CH
CLK high pulse width
2.5
-
ns
3
t
CL
CLK low pulse width
2.5
-
ns
3
t
SS
Input setup time
1.5
-
ns
3
t
SH
Input hold time
1
-
ns
3
t
SLZ
CLK to output in Low-Z
1
-
ns
2
t
SHZ
CLK to output In Hi-Z
2,3
- 6
ns
*All AC parameters are measured from half to half.
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e.,
[
(tr + tf)/2-1
]
ns should be added to the parameter.
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(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol Parameter CAS
Latency
-7
Unit Note
t
RRD(min)
Row active to row active delay
15
ns
1
t
RCD(min)
RAS to
CAS
delay
15 ns
1
t
RP(min)
Row precharge time
20
ns
1
t
RAS(min)
40 ns
1
t
RAS(max)
Row active time
100
s
t
RC(min)
Row cycle time
60
ns
1
t
CDL(min)
Last data in new col. Address delay
7
ns
2
t
RDL(min)
Last data in row precharge
14
ns
2
t
BDL(min)
Last data in to burst stop
7
ns
2
t
CCD(min)
Col. Address to col. Address delay
2,3
7 ns
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Simplified Truth Table
Command CKEn-1 CKEn CS
RAS
CAS
WE
DQM BS0
BS1
A10
/AP
A9~A0,
A11,A12
Notes
Register
Mode Register Set
H X L
L L L X OP
CODE
1,2
Auto Refresh
H
3
Entry
H
L
L L L H X
X
3
L H H H
3
Refresh
Self
Refresh
Exit L
H
H X X X
X X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Addr.
4
Auto Precharge Disable
L
4
Read &
Column Addr. Auto Precharge Enable
H X L
H
L H
X
V
H
Column
Addr.
4,5
Auto Precharge Disable
L
4
Write &
Column Addr. Auto Precharge Enable
H X L
H
L L X
V
H
Column
Addr.
4,5
Burst Stop
H
X
L
H
H
L
X
X
Bank Selection
V
L
Precharge
Both Banks
H X L
L
H L X
X H
X
L H H H
Entry
H L
H X X X
X
Clock Suspend or
Active Power Down
Exit L
H
X
X
X
X
X
X
L H H H
Entry H L
H X X X
X
L V V V
Precharge Power Down Mode
Exit L H
H X X X
X
X
DQM H
X
V
X
6
L H H H
No Operation Command
H
X
H X X X
X X
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low)
Note :
1. OP Code: Operand Code
A0~A12, BS0, BS1: Program keys. (@MRS)
2. MRS can be issued only when all banks are at precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only when all banks are at precharge state.
4. BS0, BS1 : Bank select address.
If both BS1 and BS0 are "Low" at read, write, row active and precharge, bank A is selected.
If both BS1 is "Low" and BS0 is "High" at read, write, row active and precharge, bank B is selected.
If both BS1 is "High" and BS0 is "Low" at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BS1 and BS0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
A43L4616
(September, 2004, Version 0.0)
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AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address BS0,
BS1 A12,
A11,
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function
RFU
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 1)
(Note 2)
Test Mode
CAS Latency
Burst Type
Burst Length
A8 A7
Type
A6 A5 A4 Latency A3
Type
A2 A1 A0 BT=0
BT=1
0 0 Mode
Register
Set 0 0 0 Reserved
0
Sequential 0
0
0
1
1
0 1
0 0 1
-
1
Interleave
0
0
1
2
2
1 0
0 1 0
2
0
1
0
4
4
1 1
Vendor
Use
Only
0 1 1
3
0
1
1
8
8
Write Burst Length
1 0 0 Reserved
1
0
0 Reserved Reserved
A9 Length 1 0 1 Reserved
1
0
1 Reserved Reserved
0 Burst 1
1
0
Reserved
1
1
0
Reserved
Reserved
1 Single
Bit 1
1
1
Reserved
1
1
1 256(Full) Reserved
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200
s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note :
1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
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AMIC Technology, Corp.
Burst Sequence (Burst Length = 4)
Initial address
A1 A0
Sequential Interleave
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
Burst Sequence (Burst Length = 8)
Initial address
A2 A1 A0
Sequential Interleave
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
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AMIC Technology, Corp.
Device Operations
Clock (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock for proper functionality and ICC specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time
same as other inputs), the internal clock is suspended from
the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least "t
SS
+ 1
CLOCK
" before the high going edge of the
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.
Bank Select (BS0, BS1)
This SDRAM is organized as 4 independent banks of
4,194,304 words X 16 bits memory arrays. The BS0, BS1
inputs is latched at the time of assertion of RAS and
CAS
to select the bank to be used for the operation. The bank
select BS0, BS1 is latched at bank activate, read, write mode
register set and precharge operations.
Address Input (A0 ~ A12)
The 22 address bits required to decode the 4,194,304 word
locations are multiplexed into 12 address input pins
(A0~A12). The 13 bit row address is latched along with
RAS , BS0 and BS1 during bank activate command. The 9
bit column address is latched along with
CAS
,
WE
, BS0
and BS1during read or write command.
NOP and Device Deselect
When RAS ,
CAS
and
WE
are high, the SDRAM performs
no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS ,
CAS
and
WE
, and all
the address inputs are ignored.
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause
of 200 microseconds is required with inputs in NOP
condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SDRAM useful for variety of
different applications. The default value of the mode register
is not defined, therefore the mode register must be written
after power up to operate the SDRAM. The mode register is
written by asserting low on CS , RAS ,
CAS
,
WE
(The
SDRAM should be in active mode with CKE already high
prior to writing the mode register). The state of address pins
A0~A11, BS0 and BS1 in the same cycle as
CS ,RAS ,
CAS
,
WE
going low is the data written in the
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A11,A12, BS0 and BS1 are used for vendor specific
options or test mode. And the write burst length is
programmed using A9. A7~A8, A11,A12, BS0 and BS1 must
be set to low for normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
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AMIC Technology, Corp.
Device Operations (continued)
Bank Activate
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and
CS
with
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
t
RCD
(min) from the time of bank activation. t
RCD
(min) is an
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
t
RCD
(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SDRAM has 4
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of all banks simultaneously. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies to recover before the
other bank can be sensed reliably. t
RRD
(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to t
RCD
specification.
The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by t
RAS
(min) specification before a
precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by t
RAS
(max). The number of cycles for both
t
RAS
(min) and t
RAS
(max) can be calculated similar to t
RCD
specification.
Burst Read
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
CS
and
CAS
with
WE
being high on the positive edge of
the clock. The bank must be active for at least t
RCD
(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does not
start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of
the burst, unless a new burst read was initiated to keep the
data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or
the other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.
Burst Write
The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on
CS
,
CAS
and
WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing may not have been completed yet. The burst
write can be terminated by issuing a burst read and DQM for
blocking data inputs or burst write in the same or the other
active bank. The burst stop command is valid only at full
page burst length where the writing continues at the end of
burst and the burst is wrap around. The write burst can also
be terminated by using DQM for blocking data and
precharging the bank "t
RDL
" after the last data input to be
written into the active row. See DQM OPERATION also.
DQM Operation
The DQM is used to mask input and output operation. It
works similar to
OE
during read operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in the read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock, therefore the masking occurs for
a complete cycle. The DQM signal is important during burst
interrupts of write with read or precharge in the SDRAM. Due
to asynchronous nature of the internal write, the DQM
operation is critical to avoid unwanted or incomplete writes
when the complete burst write is not required.
Precharge
The precharge operation is performed on an active bank by
asserting low on
CS
,
RAS
,
WE
and A10/AP with valid BA
of the bank to be precharged. The precharge command can
be asserted anytime after t
RAS
(min) is satisfied from the bank
activate command in the desired bank. "t
RP
" is defined as the
minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing "t
RP
" with clock cycle
time and rounding up to the next higher integer. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by t
RAS
(max). Therefore, each bank has to be
precharged within t
RAS
(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in idle
state.
A43L4616
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AMIC Technology, Corp.
Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
RAS
(min) and "t
RP
" for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands are possible to that particular bank
until the bank achieves idle state.
Four Banks Precharge
All banks can be precharged at the same time by using
Precharge all command. Asserting low on
CS
,
RAS
and
WE
with high on A10/AP after both banks have satisfied
t
RAS
(min) requirement, performs precharge on both banks. At
the end of tRP after performing precharge all, both banks are
in idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on
CS
,
RAS
and
CAS
with high on CKE and
WE
. The auto refresh command can only be asserted with
both banks being in idle state and the device is not in power
down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified
by "t
RC
(min)". The minimum number of clock cycles required
can be calculated by driving "t
RC
" with clock cycle time and
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP's until the auto refresh
operation is completed. Both banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 8192 auto refresh
cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
CS
,
RAS
,
CAS
and CKE with high on
WE . Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's
for a minimum time of "t
RC
" before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 8192 auto refresh cycles immediately after exiting self
refresh.
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AMIC Technology, Corp.
1) Click Suspended During Write (BL=4)
Masked by CKE
Q0
Q1
Q3
Q0
Q2
Q3
Suspended Dout
2) Clock Suspended During Read (BL=4)
WR
Masked by CKE
D0
D1
D2
D3
D0
D1
D2
D3
Not Written
DQ(CL3)
DQ(CL2)
Internal
CLK
CKE
CMD
CLK
RD
Q2
Q1
Note: CLK to CLK disable/enable=1 clock
Basic feature And Function Descriptions
1. CLOCK Suspend
2. DQM Operation
* Note :
1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE "L".
2. DQM masks both data-in and data-out.
1) Write Mask (BL=4)
Masked by CKE
Q0
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
WR
Masked by CKE
D0
D1
D3
D0
D1
D3
DQM to Data-in Mask = 0CLK
DQ(CL3)
DQ(CL2)
DQM
CMD
CLK
RD
Hi-Z
Hi-Z
Q0
Q2
Q4
2) Read Mask (BL=4)
RD
Hi-Z
Hi-Z
Hi-Z
Q6
Q7
Q8
Hi-Z
Q1
Q3
Hi-Z
Hi-Z
Q5
Q6
Q7
CLK
CMD
CKE
DQM
DQ(CL2)
DQ(CL3)
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AMIC Technology, Corp.
3. CAS Interrupt (I)
Note : 1. By "Interrupt", It is possible to stop burst read/write by external command before the end of burst.
By "
CAS
Interrupt", to stop burst read/write by
CAS
access; read, write and block write.
2. t
CCD
:
CAS
to
CAS
delay. (=1CLK)
3. t
CDL
: Last data in to new column address delay. (= 1CLK).
1) Read interrupted by Read (BL=4)
Note 1
RD
RD
A
B
QA0
QB0
QB1 QB2
QB3
QA0
QB0 QB1
QB2 QB3
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
t
CCD
Note2
2) Write interrupted by Write (BL =2)
WR
WR
A
B
CLK
CMD
ADD
t
CCD
Note2
DA0
DB0
DB1
t
CDL
Note3
DQ
3) Write interrupted by Read (BL =2)
WR
RD
A
B
t
CCD
Note2
DA0
QB0
QB1
t
CDL
Note3
DQ(CL2)
QB0
QB1
DQ(CL3)
DA0
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AMIC Technology, Corp.
4. CAS Interrupt (II) : Read Interrupted Write & DQM
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
RD
WR
D0
D1
D2
D3
RD
WR
D0
D1
D2
D3
WR
RD
Hi-Z
Hi-Z
D0
D1
D2
D3
RD
WR
D0
D1
D2
D3
Q0
Hi-Z
Note 1
RD
WR
D0
D1
D2
D3
RD
WR
D0
D1
D2
D3
WR
RD
Hi-Z
D0
D1
D2
D3
RD
WR
D0
D1
D2
Q0
Hi-Z
Note 2
D0
D1
D2
D3
RD
WR
WR
(1) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
(2) CL=3, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
v) CMD
DQM
DQ
D3
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AMIC Technology, Corp.
5. Write Interrupted by Precharge & DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
7. Auto Precharge
* Note : 1. The row active command of the precharge bank can be issued after t
RP
from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,
CAS
interrupt of the same/another bank is illegal.
WR
PRE
D0
D1
D2
D3
CLK
CMD
DQ
1) Normal Write (BL=4)
t
RDL
RD
PRE
Q0
Q1
Q2
Q3
CLK
CMD
DQ(CL2)
2) Read (BL=4)
Q0
Q1
Q2
Q3
DQ(CL3)
WR
D0
D1
D2
D3
CLK
CMD
DQ
1) Normal Write (BL=4)
Note 1
RD
Q0
Q1
Q2
Q3
CLK
CMD
DQ(CL2)
2) Read (BL=4)
Q0
Q1
Q2
Q3
DQ(CL3)
Auto Precharge Starts
Note 1
Auto Precharge Starts
WR
PRE
Note 2
Note 1
D0
D1
D2
D3
Masked by DQM
CLK
CMD
DQM
DQ
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AMIC Technology, Corp.
8. Burst Stop & Interrupted by Precharge
WR
D0
D1
D2
D3
CLK
CMD
DQM
DQ
1) Normal Write (BL=4)
PRE
t
RDL
Note 1
WR
D0
D1
D2
D3
CLK
CMD
DQM
DQ
2) Write Burst Stop (BL=8)
STOP
t
BDL
Note 2
D4
D5
RD
Q0
Q1
CLK
CMD
DQ(CL2)
1) Read Interrupted by Precharge (BL=4)
PRE
Note 3
DQ(CL3)
Q0
Q1
1
2
RD
Q0
Q1
CLK
CMD
DQ(CL2)
4) Read Burst Stop (BL=4)
STOP
DQ(CL3)
Q0
Q1
1
2
9. MRS
Note : 1. t
RDL
: 1CLK
2.
t
BDL
: 1CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.
4. PRE: All banks precharge if necessary.
MRS can be issued only when all banks are in precharged state.
PRE
MRS
Note 1
CLK
CMD
Mode Register Set
2CLK
ACT
t
RP
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AMIC Technology, Corp.
10
. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During t
RC
from auto refresh command, other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
During t
RC
from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (8K cycles ) is recommended.
2) Self Refresh
CLK
CMD
1) Auto Refresh
CKE
Internal
CLK
CLK
CMD
SR
CKE
PRE
Note 4
PRE
AR
CMD
Note 5
~~
~ ~
~~
~~
t
RP
t
RC
Note 3
Note 6
~~
CMD
~~
Note 4
t
RP
t
RC
~~
~~
~~
2) Power Down (=Precharge Power Down) Exit
Note 1
CLK
CMD
1) Clock Suspend (=Active Power Down) Exit
RD
t
SS
CKE
Internal
CLK
Note 2
CLK
CMD
ACT
CKE
Internal
CLK
t
SS
NOP
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AMIC Technology, Corp.
12. About Burst Type Control
Sequential counting
At MRS A3="0". See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
Basic
MODE
Interleave counting
At MRS A3=" 1". See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Random
MODE
Random column Access
t
CCD
= 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
13. About Burst Length Control
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010"
Basic
MODE
8
At MRS A2,1,0 = "011".
Special
MODE
BRSW
At MRS A9="1".
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
RAS Interrupt
(Interrupted by Precharge)
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t
RDL
=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Interrupt
MODE
CAS
Interrupt
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge,
CAS
interrupt can not be issued.
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AMIC Technology, Corp.
Power On Sequence & Auto Refresh
KEY
Ra
BS
Ra
High level is necessary
High level is necessary
High-Z
t
RP
t
RC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Regiser Set
Row Active
(A-Bank)
: Don't care
~ ~
~~
~ ~
~ ~
~ ~
~ ~
~~
~ ~
~ ~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
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AMIC Technology, Corp.
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
Rb
High
t
RCD
t
RP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
A10/AP
WE
DQM
DQ
Row Active
Read
Write
Row Active
: Don't care
t
CH
t
CL
t
CC
Ra
Ca
Cb
Cc
BS
BS
BS
BS
BS
BS
Ra
Rb
Qa
Db
Qc
t
RA
S
t
RC
t
SH
t
SS
*Note 1
t
SH
t
SS
t
CCD
t
SH
t
SS
t
SH
t
SS
t
SS
t
SH
*Note 2
*Note 2,3
*Note 2,3
*Note 2,3
*Note 4
*Note 2
*Note 3
*Note 3
*Note 3
*Note 4
t
SH
t
SS
t
SH
t
SS
t
SH
t
SS
t
RA
C
t
SA
C
t
SLZ
t
OH
t
SHZ
Read
Precharge
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AMIC Technology, Corp.
* Note : 1. All inputs can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BS0, BS1.
BS1
BS0
Active & Read/Write
0 0
Bank
A
0 1
Bank
B
1 0
Bank
C
1 1
Bank
D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP
BS1 BS0
Operation
0
0
Disable auto precharge, leave bank A active at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
0
1
1
Disable auto precharge, leave bank D active at end of burst.
0
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
1
1
Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.
A10/AP
BS1 BS0
Precharge
0 0 0
Bank
A
0 0 1
Bank
B
0 1 0
Bank
C
0 1 1
Bank
D
1 X X
All
Banks
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AMIC Technology, Corp.
Read & Write Cycle at Same Bank @Burst Length=4
High
t
RC
t
RCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0
WE
DQM
DQ
(CL = 2)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note 1
*Note 2
Ra
Ca0
Rb
Cb0
Ra
Rb
A10/AP
Qa0
t
OH
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
RAC
t
SAC
*Note 3
t
SHZ
*Note 4
Qa0
t
OH
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
RAC
t
SAC
*Note 3
t
SHZ
*Note 4
t
RDL
Write
(A-Bank)
DQ
(CL = 3)
BS1
t
RDL
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after t
SHZ
from the clock.
3. Access time from Row address. t
CC
*(t
RCD
+ CAS latency-1) + t
SAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
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AMIC Technology, Corp.
Page Read & Write Cycle at Same Bank @Burst Length=4
t
RDL
High
t
RCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0
WE
DQM
DQ
(CL=2)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note 2
Ra
Ca
Cb
Cc
Ra
A10/AP
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Write
(A-Bank)
Cd
t
CDL
*Note1
*Note3
Dc0
Dc1
Dd0
Dd1
Read
(A-Bank)
Write
(A-Bank)
DQ
(CL=3)
BS1
Qb2
Qb1
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
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Page Read Cycle at Different Bank @Burst Length = 4
Read
(C-Bank)
Row Active
(D-Bank)
Read
(B-Bank)
Read
(A-Bank)
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(B-Bank)
: Don't care
RAa
RBb
A10/AP
CBb
Row Active
(C-Bank)
*Note 1
*Note 2
CAa
RAa
WE
DQM
QBb2
QBb1
QAa0 QAa1 QAa2
QBb0
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QBb2
QBb1
QAa0 QAa1 QAa2
QBb0
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Read
(D-Bank)
Precharge
(C-Bank)
Precharge
(D-Bank)
DQ
(CL=2)
DQ
(CL=3)
BS0
RBb
RCc
RDd
Precharge
(A-Bank)
Precharge
(B-Bank)
RCc
CCc
RDd
CDd
* Note : 1.
CS
can be don't care when
RAS
,
CAS
and
WE
are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
A43L4616
(September, 2004, Version 0.0)
27
AMIC Technology, Corp.
Page Write Cycle at Different Bank @Burst Length=4
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(B-Bank)
: Don't care
A10/AP
Write
(A-Bank)
WE
DBb1
DBb0
DAa0 DAa1 DAa2
DAa3
DBb2 DBb3 DCc0 DCc1
Write
(C-Bank)
Precharge
(All Banks)
DQM
DQ
t
CDL
DDd0 DDd1
*Note 2
t
RDL
*Note 1
Write
(D-Bank)
Write
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
RAa
RBb
CBb
CAa
RCc
RDd
CCc
CDd
RAa
BS0
RBb
RCc
RDd
CDd2
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
A43L4616
(September, 2004, Version 0.0)
28
AMIC Technology, Corp.
Read & Write Cycle at Different Bank @Burst Length=4
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Read
(A-Bank)
: Don't care
RAa
CAa
A10/AP
RDb
Precharge
(A-Bank)
CDb
CBc
RAa
WE
QAa2
QAa1
QAa0
QAa3
DDb0
Write
(D-Bank)
Read
(B-Bank)
DQM
QBc0 QBc1
RBc
RBC
RDb
t
CDL
*Note 1
QAa3
QAa2
QAa0
QAa1
DDb0 DDb1
QBc0
DDb2 DDb3
QBc1 QBc2
DQ
(CL=2)
DDb1 DDb2 DDb3
DQ
(CL=3)
Row Active
(B-Bank)
Row Active
(D-Bank)
BS0
* Note : t
CDL
should be met to complete write.
A43L4616
(September, 2004, Version 0.0)
29
AMIC Technology, Corp.
Read & Write Cycle with Auto Precharge @Burst Length=4
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
Row Active
(D-Bank)
: Don't care
RAa
RBb
A10/AP
CAa
Auto Precharge
Start Point
(A-Bank/CL=2)
RAa
WE
QAa2
QAa1
QAa0
QAa3
DDb0
Auto Precharge
Start Point
(D-Bank)
DQM
CBb
QAa3
QAa2
QAa0
QAa1
DDb0 DDb1 DDb2 DDb3
DQ
(CL=2)
DDb1 DDb2 DDb3
DQ
(CL=3)
Write with
Auto Precharge
(D-Bank)
RBb
Read with
Auto Precharge
(A-Bank)
BS0
Auto Precharge
Start Point
(A-Bank/CL=3)
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
A43L4616
(September, 2004, Version 0.0)
30
AMIC Technology, Corp.
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
: Don't care
Ra
A10/AP
Ca
Ra
WE
DQM
Qa1
Qb0
Qb1
Dc0
DQ
Clock
Suspension
Read
Bank 0
Cb
Read
Bank 0
Qa0
Dc2
* Note 1
Qa2
Cc
Clock
Suspension
t
SHZ
Qa3
t
SHZ
Write
DQM
Write
Bank 0
Read DQM
BS0
* Note : DQM needed to prevent bus contention.
A43L4616
(September, 2004, Version 0.0)
31
AMIC Technology, Corp.
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full Page
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
WE
QAa3
QAa2
QAa1
QAa4
QAb0
DQM
QAa4
QAa3
QAa1
QAa2
QAb0 QAb1 QAb2 QAb3
DQ
(CL=2)
QAb1 QAb2 QAb3
DQ
(CL=3)
Precharge
(A-Bank)
Read
(A-Bank)
CAb
Read
(A-Bank)
Burst Stop
1
QAa0
QAb4 QAb5
1
QAa0
2
QAb4 QAb5
2
BS0
RAa
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ's after burst stop, it is same as the case of
RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
A43L4616
(September, 2004, Version 0.0)
32
AMIC Technology, Corp.
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
WE
DQM
DAa4
DAa3
DAa1
DAa2
DAb0 DAb1 DAb2 DAb3
DQ
Precharge
(A-Bank)
Write
(A-Bank)
CAb
Write
(A-Bank)
Burst Stop
DAa0
DAb4 DAb5
t
RDL
t
BDL
* Note 2
BS0
RAa
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of t
RDL
(=2CLK).
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
A43L4616
(September, 2004, Version 0.0)
33
AMIC Technology, Corp.
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS1
Precharge
Power-down
Exit
: Don't care
A10/AP
Active
Power-down
Entry
Row
Active
WE
Qa2
Read
Precharge
DQM
DQ
Qa0
Qa1
Precharge
Power-down
Entry
t
SS
t
SS
* Note 2
* Note 1
*Note 3
t
SS
t
SS
Ra
Ca
Ra
Active
Power-down
Exit
~~
~ ~
~ ~
~ ~
~~
~ ~
~~
~~
~~
~ ~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~ ~
~ ~
BS0
~~
~ ~
~~
~ ~
t
SHZ
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least "1CLK + t
SS
" prior to Row active command.
3. Cannot violate minimum refresh specification. (64ms)
A43L4616
(September, 2004, Version 0.0)
34
AMIC Technology, Corp.
Self Refresh Entry & Exit Cycle
* Note : TO ENTER SELF REFRESH MODE
1.
CS, RAS &
CAS
and CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 8K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0, BS1
: Don't care
A10/AP
WE
Self Refresh Exit
Auto Refresh
DQM
DQ
Self Refresh Entry
t
SS
* Note 4
* Note 1
~ ~
~ ~
~ ~
~~
~ ~
* Note 3
* Note 2
~ ~
t
SS
* Note 6
t
RC
min.
~ ~
~ ~
* Note 5
~~
~ ~
* Note 7
* Note 7
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
~~
~ ~
Hi-Z
Hi-Z
A43L4616
(September, 2004, Version 0.0)
35
AMIC Technology, Corp.
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
CKE
CS
RAS
CAS
ADDR
: Don't care
WE
Auto Refresh
New Command
DQM
DQ
MRS
~ ~
~ ~
* Note 1
~~
~ ~
Hi-Z
Hi-Z
High
High
~ ~
~ ~
t
RC
*Note 2
~ ~
~~
~ ~
~~
~ ~
Key
* Note 3
~~
~ ~
New
Command
~~
~ ~
Ra
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1.
CS, RAS ,
CAS
&
WE
activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles is required before new
RAS activation.
3. Please refer to Mode Register Set table.
A43L4616
(September, 2004, Version 0.0)
36
AMIC Technology, Corp.
Function Truth Table (Table 1)
Current
State
CS RAS
CAS
WE
BA Address
Action
Note
H X X X X
X NOP
L H H H X
X NOP
L H H L X
X ILLEGAL
2
L H L X BA
CA,
A10/AP ILLEGAL
2
L
L
H
H
BA
RA
Row Active; Latch Row Address
L L H L BA A10/PA
NOP
4
L
L
L
H
X
X
Auto Refresh or Self Refresh
5
IDLE
L
L
L
L
OP Code
Mode Register Access
5
H X X X X
X NOP
L H H H X
X NOP
L H H L X
X ILLEGAL
2
L
H
L
H
BA
CA,A10/AP Begin Read; Latch CA; Determine AP
L
H
L
L
BA
CA,A10/AP Begin Write; Latch CA; Determine AP
L L H H BA RA ILLEGAL
2
L L H L BA PA Precharge
Row
Active
L L L X X
X ILLEGAL
H X X X X
X NOP(Continue Burst to End
Row Active)
L H H H X
X NOP(Continue Burst to End
Row Active)
L H H L X
X Term burst
Row Active
L
H
L
H
BA
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
L
H
L
L
BA
CA,A10/AP Term burst; Begin Write; Latch CA; Determine AP
3
L L H H BA RA ILLEGAL
2
L
L
H
L
BA
CA,A10/AP Term Burst; Precharge timing for Reads
3
Read
L L L X X
X ILLEGAL
H X X X X
X NOP(Continue Burst to End
Row Active)
L H H H X
X NOP(Continue Burst to End
Row Active)
L H H L X
X Term burst
Row Active
L
H
L
H
BA
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
L
H
L
L
BA
CA,A10/AP Term burst; Begin Write; Latch CA; Determine AP
3
L L H H BA RA ILLEGAL
2
L
L
H
L
BA
A10/AP
Term Burst; Precharge timing for Writes
3
Write
L L L X X
X ILLEGAL
H X X X X
X NOP(Continue Burst to End
Precharge)
L H H H X
X NOP(Continue Burst to End
Precharge)
L H H L X
X ILLEGAL
L H L H BA
CA,A10/AP ILLEGAL
2
L H L L BA
CA,A10/AP ILLEGAL
2
L L H X BA RA,
PA
ILLEGAL
Read with
Auto
Precharge
L L L X X
X ILLEGAL
2
A43L4616
(September, 2004, Version 0.0)
37
AMIC Technology, Corp.
Function Truth Table (Table 1, Continued)
Current
State
CS RAS
CAS
WE
BS Address
Action
Note
H X X X X
X NOP(Continue Burst to End
Precharge)
L H H H X
X NOP(Continue Burst to End
Precharge)
L H H L X
X ILLEGAL
L H L H BA
CA,A10/AP ILLEGAL
2
L H L L BA
CA,A10/AP ILLEGAL
2
L L H X BA RA,
PA
ILLEGAL
Write with
Auto
Precharge
L L L X X
X ILLEGAL
2
H X X X X
X NOP
Idle after t
RP
L H H H X
X NOP
Idle after t
RP
L H H L X
X ILLEGAL
L H L X BA
CA,A10/AP ILLEGAL
2
L L H H BA RA ILLEGAL
2
L L H L BA A10/PA
NOP
Idle after t
RP
2
Precharge
L L L X X
X ILLEGAL
4
H X X X X
X NOP
Row Active after t
RCD
L H H H X
X NOP
Row Active after t
RCD
L H H L X
X ILLEGAL
L H L X BA
CA,A10/AP ILLEGAL
2
L L H H BA RA ILLEGAL
2
L L H L BA A10/PA
ILLEGAL
2
Row
Activating
L L L X X
X ILLEGAL
2
H X X X X
X NOP
Idle after t
RC
L H H X X
X NOP
Idle after t
RC
L H L X X
X ILLEGAL
L L H X X
X ILLEGAL
Refreshing
L L L X X
X ILLEGAL
H X X X X
X NOP
Idle after 2 clocks
L H H H H
X NOP
Idle after 2 clocks
L H H L X
X ILLEGAL
L H L X X
X ILLEGAL
Mode
Register
Accessing
L L X X X
X ILLEGAL
Abbreviations
RA = Row Address
BS = Bank Address
AP = Auto Precharge
NOP = No Operation Command
CA = Column Address
PA = Precharge All
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state: Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BS (and PA).
5. Illegal if any banks is not idle.
A43L4616
(September, 2004, Version 0.0)
38
AMIC Technology, Corp.
Function Truth Table for CKE (Table 2)
Current
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Address
Action Note
H X X X X X X INVALID
L H H X X X X Exit Self Refresh
ABI after t
RC
6
L H L H H H X Exit Self Refresh
ABI after t
RC
6
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Self
Refresh
L L X X X X X NOP(Maintain
Self
Refresh)
H X X X X X X INVALID
L H H X X X X Exit Power Down
ABI
7
L H L H H H X Exit Power Down
ABI
7
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Both
Bank
Precharge
Power
Down
L L X X X X X NOP(Maintain
Power
Down
Mode)
H H X X X X X Refer
to
Table
1
H L H X X X X Enter
Power
Down
8
H L L H H H X Enter
Power
Down
8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H
L
L
L
H
H
RA
Row (& Bank ) Active
H L L L L H X Enter
Self
Refresh
8
H L L L L L
OPCODE MRS
All
Banks
Idle
L L X X X X X NOP
H
H
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
9
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
9
Any State
Other than
Listed
Above
L L X X X X X Maintain
clock
Suspend
Abbreviations : ABI = All Banks Idle
Note: 6. After CKE's low to high transition to exit self refresh mode, a minimum of t
RC
(min) has to be elapse before issuing a
new command.
7. CKE low to high transition is asynchronous as if it restarts internal clock.
A minimum setup time "tSS + one clock" must be satisfied before any command can be issued other than exit.
8. Power-down and self refresh can be entered only when all the banks are in idle state.
9. Must be a legal command.
A43L4616
(September, 2004, Version 0.0)
39
AMIC Technology, Corp.
Ordering Information
Part No.
Cycle Time (ns)
Clock Frequency (MHz)
Access Time
Package
A43L4616V-7
7
143@ CL = 3
5.4 ns
54 TSOP (II)
A43L4616
(September, 2004, Version 0.0)
40
AMIC Technology, Corp.
Package Information
TSOP 54 (Type II) Outline Dimensions
unit: inches/mm
1
E1
E
c
54
A
1
A
2
A
D
0.1
e
D
b
L
Detail "A"
Detail "A"
27
28
Seating Plane
R1
R2
L
1
-C-
0.21 REF
0.665 REF
S
Dimensions in inches
Dimensions in mm
Symbol
Min Nom
Max Min Nom
Max
A -
-
0.047
-
-
1.20
A
1
0.002
0.004
0.006
0.05 - 0.15
A
2
0.037
0.039
0.041
0.95
1.00
1.05
b 0.012
-
0.018
0.30 - 0.45
c 0.005
-
0.008
0.12 - 0.21
D
0.875 BSC
22.22 BSC
S
0.028 REF
0.71 REF
E
0.463 BSC
11.76 BSC
E
1
0.400 BSC
10.16 BSC
e
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