Document Outline

• List of Figures
  • Figure 1-1. Block Diagram
  • Figure 3-1. Signal Groups
  • Figure 3-2. 432-EBGA Ball Assignment Diagram
  • Figure 3-3. 481-TEPBGA Ball Assignment Diagram
  • Figure 4-1. WATCHDOG Block Diagram
  • Figure 4-2. Clock Generation Block Diagram
  • Figure 4-3. Recommended Oscillator External Circuitry
  • Figure 5-1. SIO Block Diagram
  • Figure 5-2. Detailed SIO Block Diagram
  • Figure 5-3. Structure of the Standard Configuration Register File
  • Figure 5-4. Standard Configuration Registers Map
  • Figure 5-5. Recommended Oscillator External Circuitry
  • Figure 5-6. External Oscillator Connections
  • Figure 5-7. Divider Chain Control
  • Figure 5-8. Power Supply Connections
  • Figure 5-9. Typical Battery Configuration
  • Figure 5-10. Typical Battery Current: Battery Backed Power Mode @ TC = 25C
  • Figure 5-11. Typical Battery Current: Normal Operation Mode
  • Figure 5-12. Interrupt/Status Timing
  • Figure 5-13. Bit Transfer
  • Figure 5-14. Start and Stop Conditions
  • Figure 5-15. ACCESS.bus Data Transaction
  • Figure 5-16. ACCESS.bus Acknowledge Cycle
  • Figure 5-17. A Complete ACCESS.bus Data Transaction
  • Figure 5-18. UART Mode Register Bank Architecture
  • Figure 5-19. IRCP/SP3 Register Bank Architecture
  • Figure 6-1. Core Logic Module Block Diagram
  • Figure 6-2. Non-Posted Fast-PCI to ISA Access
  • Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled
  • Figure 6-4. ISA DMA Read from PCI Memory
  • Figure 6-5. ISA DMA Write to PCI Memory
  • Figure 6-6. PCI Change to Sub-ISA and Back
  • Figure 6-7. PIT Timer
  • Figure 6-8. PIC Interrupt Controllers
  • Figure 6-9. PCI and IRQ Interrupt Mapping
  • Figure 6-10. SMI Generation for NMI
  • Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
  • Figure 6-12. PRD Table Example
  • Figure 6-13. AC97 V2.0 Codec Signal Connections
  • Figure 6-14. Audio SMI Tree Example
  • Figure 6-15. Typical Setup
  • Figure 7-1. Video Processor Block Diagram
  • Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
  • Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
  • Figure 7-4. VIP Block Diagram
  • Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer
  • Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
  • Figure 7-7. Video Block Diagram
  • Figure 7-8. Horizontal Downscaler Block Diagram
  • Figure 7-9. Linear Interpolation Calculation
  • Figure 7-10. Mixer/Blender Block Diagram
  • Figure 7-11. Graphics/Video Frame with Alpha Windows
  • Figure 7-12. Color Key and Alpha Blending Logic
  • Figure 7-13. TFT Power Sequence
  • Figure 7-14. PLL Block Diagram
  • Figure 9-1. Differential Input Sensitivity for Common Mode Range
  • Figure 9-2. Drive level and Measurement Points
  • Figure 9-3. Memory Controller Drive Level and Measurement Points
  • Figure 9-4. Memory Controller Output Valid Timing Diagram
  • Figure 9-5. Read Data In Setup and Hold Timing Diagram
  • Figure 9-6. Video Input Port Timing Diagram
  • Figure 9-7. TFT Timing Diagram
  • Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram
  • Figure 9-9. ACB Start and Stop Condition Timing Diagram
  • Figure 9-10. ACB Start Condition Timing Diagram
  • Figure 9-11. ACB Data Bit Timing Diagram
  • Figure 9-12. Testing Setup for Slew Rate and Minimum Timing
  • Figure 9-13. V/I Curves for PCI Output Signals
  • Figure 9-14. PCICLK Timing and Measurement Points
  • Figure 9-15. Load Circuits for Maximum Time Measurements
  • Figure 9-16. Output Timing Measurement Conditions
  • Figure 9-17. Input Timing Measurement Conditions
  • Figure 9-18. PCI Reset Timing
  • Figure 9-19. Sub-ISA Read Operation Timing Diagram
  • Figure 9-20. Sub-ISA Write Operation Timing Diagram
  • Figure 9-21. LPC Output Timing Diagram
  • Figure 9-22. LPC Input Timing Diagram
  • Figure 9-23. IDE Reset Timing Diagram
  • Figure 9-24. Register Transfer to/from Device Timing Diagram
  • Figure 9-25. PIO Data Transfer to/from Device Timing Diagram
  • Figure 9-26. Multiword DMA Data Transfer Timing Diagram
  • Figure 9-27. Initiating an UltraDMA Data in Burst Timing Diagram
  • Figure 9-28. Sustained UltraDMA Data In Burst Timing Diagram
  • Figure 9-29. Host Pausing an UltraDMA Data In Burst Timing Diagram
  • Figure 9-30. Device Terminating an UltraDMA Data In Burst Timing Diagram
  • Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram
  • Figure 9-32. Initiating an UltraDMA Data Out Burst Timing Diagram
  • Figure 9-33. Sustained UltraDMA Data Out Burst Timing Diagram
  • Figure 9-34. Device Pausing an UltraDMA Data Out Burst Timing Diagram
  • Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram
  • Figure 9-36. Device Terminating an UltraDMA Data Out Burst Timing Diagram
  • Figure 9-37. Data Signal Rise and Fall Timing Diagram
  • Figure 9-38. Source Differential Data Jitter Timing Diagram
  • Figure 9-39. EOP Width Timing Diagram
  • Figure 9-40. Receiver Jitter Tolerance Timing Diagram
  • Figure 9-41. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
  • Figure 9-42. Fast IR (MIR and FIR) Timing Diagram
  • Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram
  • Figure 9-44. Enhanced Parallel Port Timing Diagram
  • Figure 9-45. ECP Forward Mode Timing Diagram
  • Figure 9-46. ECP Reverse Mode Timing Diagram
  • Figure 9-47. AC97 Reset Timing Diagram
  • Figure 9-48. AC97 Sync Timing Diagram
  • Figure 9-49. AC97 Clocks Diagram
  • Figure 9-50. AC97 Data TIming Diagram
  • Figure 9-51. AC97 Rise and Fall Timing Diagram
  • Figure 9-52. AC97 Low Power Mode Timing Diagram
  • Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram
  • Figure 9-54. GPWIO and ONCTL# Timing Diagram
  • Figure 9-55. Power-Up Sequencing With PWRBTN# Timing Diagram
  • Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram
  • Figure 9-57. TCK Measurement Points and Timing Diagram
  • Figure 9-58. JTAG Test Timing Diagram
  • Figure 10-1. Heatsink Example
  • Figure 10-2. 432-Terminal EBGA Package (Body Size: 40x40x1.72 mm; Pitch: 1.27 mm)
  • Figure 10-3. 481-Terminal TEPBGA Package (Body Size: 40x40x2.38 mm; Pitch: 1.27 mm)
• List of Tables
  • Table 2-1. SC3200 Memory Controller Register Summary
  • Table 2-2. SC3200 Memory Controller Registers
  • Table 3-1. Signal Definitions Legend
  • Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number
  • Table 3-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name
  • Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number
  • Table 3-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name
  • Table 3-6. Strap Options
  • Table 3-7. Two-Signal/Group Multiplexing
  • Table 3-8. Three-Signal/Group Multiplexing
  • Table 3-9. Four-Signal/Group Multiplexing
  • Table 4-1. General Configuration Block Register Summary
  • Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers
  • Table 4-3. WATCHDOG Registers
  • Table 4-4. High-Resolution Timer Registers
  • Table 4-5. Crystal Oscillator Circuit Components
  • Table 4-6. Core Clock Frequency
  • Table 4-7. Strapped Core Clock Frequency
  • Table 4-8. Clock Generator Configuration
  • Table 5-1. SIO Configuration Options
  • Table 5-2. LDN Assignments
  • Table 5-3. Standard Configuration Registers
  • Table 5-4. SIO Control and Configuration Register Map
  • Table 5-5. SIO Control and Configuration Registers
  • Table 5-6. Relevant RTC Configuration Registers
  • Table 5-7. RTC Configuration Registers
  • Table 5-8. Relevant SWC Registers
  • Table 5-9. Relevant IRCP/SP3 Registers
  • Table 5-10. IRCP/SP3 Configuration Register
  • Table 5-11. Relevant Serial Ports 1 and 2 Registers
  • Table 5-12. Serial Ports 1 and 2 Configuration Register
  • Table 5-13. Relevant ACB1 and ACB2 Registers
  • Table 5-14. ACB1 and ACB2 Configuration Register
  • Table 5-15. Relevant Parallel Port Registers
  • Table 5-16. Parallel Port Configuration Register
  • Table 5-17. Crystal Oscillator Circuit Components
  • Table 5-18. System Power States
  • Table 5-19. RTC Register Map
  • Table 5-20. RTC Registers
  • Table 5-21. Divider Chain Control / Test Selection
  • Table 5-22. Periodic Interrupt Rate Encoding
  • Table 5-23. BCD and Binary Formats
  • Table 5-24. Standard RAM Map
  • Table 5-25. Extended RAM Map
  • Table 5-26. Time Range Limits for CEIR Protocols
  • Table 5-27. Banks 0 and 1 - Common Control and Status Register Map
  • Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
  • Table 5-29. Banks 0 and 1 - Common Control and Status Registers
  • Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
  • Table 5-31. ACB Register Map
  • Table 5-32. ACB Registers
  • Table 5-33. Parallel Port Register Map for First Level Offset
  • Table 5-34. Parallel Port Register Map for Second Level Offset
  • Table 5-35. Parallel Port Bit Map for First Level Offset
  • Table 5-36. Parallel Port Bit Map for Second Level Offset
  • Table 5-37. Bank 0 Register Map
  • Table 5-38. Bank Selection Encoding
  • Table 5-39. Bank 1 Register Map
  • Table 5-40. Bank 2 Register Map
  • Table 5-41. Bank 3 Register Map
  • Table 5-42. Bank 0 Bit Map
  • Table 5-43. Bank 1 Bit Map
  • Table 5-44. Bank 2 Bit Map
  • Table 5-45. Bank 3 Bit Map
  • Table 5-46. Bank 0 Register Map
  • Table 5-47. Bank Selection Encoding
  • Table 5-48. Bank 1 Register Map
  • Table 5-49. Bank 2 Register Map
  • Table 5-50. Bank 3 Register Map
  • Table 5-51. Bank 4 Register Map
  • Table 5-52. Bank 5 Register Map
  • Table 5-53. Bank 6 Register Map
  • Table 5-54. Bank 7 Register Map
  • Table 5-55. Bank 0 Bit Map
  • Table 5-56. Bank 1 Bit Map
  • Table 5-57. Bank 2 Bit Map
  • Table 5-58. Bank 3 Bit Map
  • Table 5-59. Bank 4 Bit Map
  • Table 5-60. Bank 5 Bit Map
  • Table 5-61. Bank 6 Bit Map
  • Table 5-62. Bank 7 Bit Map
  • Table 6-1. Physical Region Descriptor Format
  • Table 6-2. UltraDMA/33 Signal Definitions
  • Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
  • Table 6-4. PIC Interrupt Mapping
  • Table 6-5. Wakeup Events Capability
  • Table 6-6. Power Planes Control Signals vs. Sleep States
  • Table 6-7. Power Planes vs. Sleep/Global States
  • Table 6-8. Power Management Events
  • Table 6-9. Device Power Management Programming Summary
  • Table 6-10. Bus Masters That Drive Specific Slots of the AC97 Interface
  • Table 6-11. Physical Region Descriptor Format
  • Table 6-12. Cycle Types
  • Table 6-13. PCI Configuration Address Register (0CF8h)
  • Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary
  • Table 6-15. F0BAR0: GPIO Support Registers Summary
  • Table 6-16. F0BAR1: LPC Support Registers Summary
  • Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
  • Table 6-18. F1BAR0: SMI Status Registers Summary
  • Table 6-19. F1BAR1: ACPI Support Registers Summary
  • Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
  • Table 6-21. F2BAR4: IDE Controller Support Registers Summary
  • Table 6-22. F3: PCI Header Registers for Audio Support Summary
  • Table 6-23. F3BAR0: Audio Support Registers Summary
  • Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
  • Table 6-25. F5BAR0: I/O Control Support Registers Summary
  • Table 6-26. PCIUSB: USB PCI Configuration Register Summary
  • Table 6-27. USB_BAR: USB Controller Registers Summary
  • Table 6-28. ISA Legacy I/O Register Summary
  • Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support
  • Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers
  • Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
  • Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support
  • Table 6-33. F1BAR0+I/O Offset: SMI Status Registers
  • Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers
  • Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
  • Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
  • Table 6-37. F3: PCI Header Registers for Audio Configuration
  • Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers
  • Table 6-39. F5: PCI Header Registers for X-Bus Expansion
  • Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
  • Table 6-41. PCIUSB: USB PCI Configuration Registers
  • Table 6-42. USB_BAR+Memory Offset: USB Controller Registers
  • Table 6-43. DMA Channel Control Registers
  • Table 6-44. DMA Page Registers
  • Table 6-45. Programmable Interval Timer Registers
  • Table 6-46. Programmable Interrupt Controller Registers
  • Table 6-47. Keyboard Controller Registers
  • Table 6-48. Real-Time Clock Registers
  • Table 6-49. Miscellaneous Registers
  • Table 7-1. Valid Mixing/Blending Configurations
  • Table 7-2. Truth Table for Alpha Blending
  • Table 7-3. F4: PCI Header Registers for Video Processor Support Summary
  • Table 7-4. F4BAR0: Video Processor Configuration Registers Summary
  • Table 7-5. F4BAR2: VIP Support Registers Summary
  • Table 7-6. F4: PCI Header Registers for Video Processor Support Registers
  • Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers
  • Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers
  • Table 8-1. JTAG Mode Instruction Support
  • Table 9-1. Electro Static Discharge (ESD)
  • Table 9-2. Absolute Maximum Ratings
  • Table 9-3. Operating Conditions
  • Table 9-4. Power Planes of External Interface Signals
  • Table 9-5. System Conditions Used to Measure SC3200 Current During On State
  • Table 9-6. DC Characteristics for On State
  • Table 9-7. DC Characteristics for Active Idle, Sleep, and Off States
  • Table 9-8. Ball Capacitance and Inductance
  • Table 9-9. Balls with PU/PD Resistors
  • Table 9-10. Buffer Types
  • Table 9-11. Default Levels for Measurement of Switching Parameters
  • Table 9-12. Memory Controller Timing Parameters
  • Table 9-13. Video Input Port Timing Parameters
  • Table 9-14. TFT Timing Parameters
  • Table 9-15. ACCESS.bus Input Timing Parameters
  • Table 9-16. ACCESS.bus Output Timing Parameters
  • Table 9-17. PCI AC Specifications
  • Table 9-18. PCI Clock Parameters
  • Table 9-19. PCI Timing Parameters
  • Table 9-20. Measurement Condition Parameters
  • Table 9-21. Sub-ISA Timing Parameters
  • Table 9-22. LPC and SERIRQ Timing Parameters
  • Table 9-23. IDE General Timing Parameters
  • Table 9-24. IDE Register Transfer to/from Device Timing Parameters
  • Table 9-25. IDE PIO Data Transfer to/from Device Timing Parameters
  • Table 9-26. IDE Multiword DMA Data Transfer Timing Parameters
  • Table 9-27. IDE UltraDMA Data Burst Timing Parameters
  • Table 9-28. USB Timing Parameters
  • Table 9-29. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters
  • Table 9-30. Fast IR Port Timing Parameters
  • Table 9-31. Standard Parallel Port Timing Parameters
  • Table 9-33. ECP Forward Mode Timing Parameters
  • Table 9-34. ECP Reverse Mode Timing Parameters
  • Table 9-35. AC Reset Timing Parameters
  • Table 9-36. AC97 Sync Timing Parameters
  • Table 9-37. AC97 Clocks Parameters
  • Table 9-38. AC97 I/O Timing Parameters
  • Table 9-39. AC97 Signal Rise and Fall Timing Parameters
  • Table 9-40. AC97 Low Power Mode Timing Parameters
  • Table 9-41. PWRBTN# Timing Parameters
  • Table 9-42. Power Management Event (GPWIO) and ONCTL# Timing Parameters
  • Table 9-43. Power-Up Sequence Using the Power Button Timing Parameters
  • Table 9-44. Power-Up Sequence Not Using the Power Button Timing Parameters
  • Table 9-45. JTAG Timing Parameters
  • Table 10-1. qJC (�C/W)
  • Table 10-2. Case-to-Ambient Thermal Resistance Example @ 85�C
  • Table A-1. Revision History
  • Table A-2. Edits to Current Revision
• AMD Geode� SC3200 Processor
  • 1.1 General Description
  • 1.2 Features
• Architecture Overview
  • 2.1 GX1 Module
    • 2.1.1 Memory Controller
    • 2.1.2 Fast-PCI Bus
    • 2.1.3 Display
  • 2.2 Video Processor Module
    • 2.2.1 GX1 Module Interface
    • 2.2.2 Video Input Port
    • 2.2.3 Core Logic Module Interface
  • 2.3 Core Logic Module
    • 2.3.1 Other Core Logic Module Interfaces
  • 2.4 Super I/O Module
  • 2.5 Clock, Timers, and Reset Logic
    • 2.5.1 Reset Logic
      • 2.5.1.1 Power-On Reset
      • 2.5.1.2 System Reset
• Signal Definitions
  • 3.1 Ball Assignments
  • 3.2 Strap Options
  • 3.3 Multiplexing Configuration
  • 3.4 Signal Descriptions
    • 3.4.1 System Interface
    • 3.4.2 Memory Interface Signals
    • 3.4.3 Video Port Interface Signals
    • 3.4.4 TFT Interface Signals
    • 3.4.5 ACCESS.bus Interface Signals
    • 3.4.6 PCI Bus Interface Signals
    • 3.4.7 Sub-ISA Interface Signals
    • 3.4.8 Low Pin Count (LPC) Bus Interface Signals
    • 3.4.9 IDE Interface Signals
    • 3.4.10 Universal Serial Bus (USB) Interface Signals
    • 3.4.11 Serial Ports (UARTs) Interface Signals
    • 3.4.12 Parallel Port Interface Signals
    • 3.4.13 Fast Infrared (IR) Port Interface Signals
    • 3.4.14 AC97 Audio Interface Signals
    • 3.4.15 Power Management Interface Signals
    • 3.4.16 GPIO Interface Signals
    • 3.4.17 Debug Monitoring Interface Signals
    • 3.4.18 JTAG Interface Signals
    • 3.4.19 Test and Measurement Interface Signals
    • 3.4.20 Power, Ground and No Connections
• General Configuration Block
  • 4.1 Configuration Block Addresses
  • 4.2 Multiplexing, Interrupt Selection, and Base Address Registers
  • 4.3 WATCHDOG
    • 4.3.1 Functional Description
      • 4.3.1.1 WATCHDOG Timer
    • 4.3.2 WATCHDOG Registers
      • 4.3.2.1 Usage Hints
  • 4.4 High-Resolution Timer
    • 4.4.1 Functional Description
    • 4.4.2 High-Resolution Timer Registers
      • 4.4.2.1 Usage Hints
  • 4.5 Clock Generators and PLLs
    • 4.5.1 27 MHz Crystal Oscillator
    • 4.5.2 GX1 Module Core Clock
    • 4.5.3 Internal Fast-PCI Clock
    • 4.5.4 SuperI/O Clocks
    • 4.5.5 Core Logic Module Clocks
    • 4.5.6 Video Processor Clocks
    • 4.5.7 Clock Registers
• SuperI/O Module
  • 5.1 Features
  • 5.2 Module Architecture
  • 5.3 Configuration Structure / Access
    • 5.3.1 Index-Data Register Pair
    • 5.3.2 Banked Logical Device Registers
    • 5.3.3 Default Configuration Setup
    • 5.3.4 Address Decoding
  • 5.4 Standard Configuration Registers
    • 5.4.1 SIO Control and Configuration Registers
    • 5.4.2 Logical Device Control and Configuration
      • 5.4.2.1 LDN 00h - Real-Time Clock
      • 5.4.2.2 LDN 01h - System Wakeup Control
      • 5.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3
      • 5.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2
      • 5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2
      • 5.4.2.6 LDN 07h - Parallel Port
  • 5.5 Real-Time Clock (RTC)
    • 5.5.1 Bus Interface
    • 5.5.2 RTC Clock Generation
      • 5.5.2.1 Internal Oscillator
      • 5.5.2.2 External Oscillator
      • 5.5.2.3 Timing Generation
      • 5.5.2.4 Timekeeping
      • 5.5.2.5 Alarms
      • 5.5.2.6 Power Supply
      • 5.5.2.7 System Power States
      • 5.5.2.8 Oscillator Activity
      • 5.5.2.9 Interrupt Handling
      • 5.5.2.10 Battery-Backed RAMs and Registers
    • 5.5.3 RTC Registers
      • 5.5.3.1 Usage Hints
    • 5.5.4 RTC General-Purpose RAM Map
  • 5.6 System Wakeup Control (SWC)
    • 5.6.1 Event Detection
      • 5.6.1.1 Audio Codec Event
      • 5.6.1.2 CEIR Address
    • 5.6.2 SWC Registers
  • 5.7 ACCESS.bus Interface
    • 5.7.1 Data Transactions
    • 5.7.2 Start and Stop Conditions
    • 5.7.3 Acknowledge (ACK) Cycle
    • 5.7.4 Acknowledge After Every Byte Rule
    • 5.7.5 Addressing Transfer Formats
    • 5.7.6 Arbitration on the Bus
    • 5.7.7 Master Mode
      • 5.7.7.1 Master Stop
    • 5.7.8 Slave Mode
    • 5.7.9 Configuration
    • 5.7.10 ACB Registers
  • 5.8 Legacy Functional Blocks
    • 5.8.1 Parallel Port
      • 5.8.1.1 Parallel Port Register and Bit Maps
    • 5.8.2 UART Functionality (SP1 and SP2)
      • 5.8.2.1 UART Mode Register Bank Overview
      • 5.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality
    • 5.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality
      • 5.8.3.1 IR/SP3 Mode Register Bank Overview
      • 5.8.3.2 IRCP/SP3 Register and Bit Maps
• Core Logic Module
  • 6.1 Feature List
  • 6.2 Module Architecture
    • 6.2.1 Fast-PCI Interface to External PCI Bus
      • 6.2.1.1 Processor Mastered Cycles
      • 6.2.1.2 External PCI Mastered Cycles
      • 6.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles
      • 6.2.1.4 External PCI Bus
      • 6.2.1.5 Bus Master Request Priority
    • 6.2.2 PSERIAL Interface
      • 6.2.2.1 Video Retrace Interrupt
    • 6.2.3 IDE Controller
      • 6.2.3.1 IDE Configuration Registers
      • 6.2.3.2 PIO Mode
      • 6.2.3.3 Bus Master Mode
      • 6.2.3.4 UltraDMA/33 Mode
    • 6.2.4 Universal Serial Bus
    • 6.2.5 Sub-ISA Bus Interface
      • 6.2.5.1 Sub-ISA Bus Cycles
      • 6.2.5.2 Sub-ISA Support of Delayed PCI Transactions
      • 6.2.5.3 Sub-ISA Bus Data Steering
      • 6.2.5.4 I/O Recovery Delays
      • 6.2.5.5 ISA DMA
      • 6.2.5.6 ROM Interface
      • 6.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing
    • 6.2.6 AT Compatibility Logic
      • 6.2.6.1 DMA Controller
      • 6.2.6.2 Programmable Interval Timer
      • 6.2.6.3 Programmable Interrupt Controller
    • 6.2.7 I/O Ports 092h and 061h System Control
      • 6.2.7.1 I/O Port 092h System Control
      • 6.2.7.2 I/O Port 061h System Control
      • 6.2.7.3 SMI Generation for NMI
    • 6.2.8 Keyboard Support
      • 6.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset
    • 6.2.9 Power Management Logic
      • 6.2.9.1 CPU States
      • 6.2.9.2 Sleep States
      • 6.2.9.3 Power Planes Control
      • 6.2.9.4 Power Management Events
      • 6.2.9.5 Usage Hints
    • 6.2.10 Power Management Programming
      • 6.2.10.1 APM Support
      • 6.2.10.2 CPU Power Management
      • 6.2.10.3 Peripheral Power Management
      • 6.2.10.4 Power Management Programming Summary
    • 6.2.11 GPIO Interface
    • 6.2.12 Integrated Audio
      • 6.2.12.1 Data Transport Hardware
      • 6.2.12.2 AC97 Codec Interface
      • 6.2.12.3 VSA Technology Support Hardware
      • 6.2.12.4 IRQ Configuration Registers
      • 6.2.12.5 LPC Interface
      • 6.2.12.6 LPC Interface Signal Definitions
      • 6.2.12.7 Cycle Types
      • 6.2.12.8 LPC Interface Support
  • 6.3 Register Descriptions
    • 6.3.1 PCI Configuration Space and Access Methods
    • 6.3.2 Register Summary
  • 6.4 Chipset Register Space
    • 6.4.1 Bridge, GPIO, and LPC Registers - Function 0
      • 6.4.1.1 GPIO Support Registers
      • 6.4.1.2 LPC Support Registers
    • 6.4.2 SMI Status and ACPI Registers - Function 1
      • 6.4.2.1 SMI Status Support Registers
      • 6.4.2.2 ACPI Support Registers
    • 6.4.3 IDE Controller Registers - Function 2
      • 6.4.3.1 IDE Controller Support Registers
    • 6.4.4 Audio Registers - Function 3
      • 6.4.4.1 Audio Support Registers
    • 6.4.5 X-Bus Expansion Interface - Function 5
      • 6.4.5.1 X-Bus Expansion Support Registers
    • 6.4.6 USB Controller Registers - PCIUSB
    • 6.4.7 ISA Legacy Register Space
• Video Processor Module
  • 7.1 Module Architecture
  • 7.2 Functional Description
    • 7.2.1 Video Input Port (VIP)
      • 7.2.1.1 Direct Video Mode
      • 7.2.1.2 Capture Video Mode
      • 7.2.1.3 Capture VBI Mode
    • 7.2.2 Video Block
      • 7.2.2.1 Video Input Formatter
      • 7.2.2.2 Horizontal Downscaler with 4-Tap Filtering
      • 7.2.2.3 Line Buffers
      • 7.2.2.4 Formatter
      • 7.2.2.5 2-Tap Vertical and Horizontal Upscalers
    • 7.2.3 Mixer/Blender Block
      • 7.2.3.1 YUV to RGB CSC in Video Data Path
      • 7.2.3.2 Gamma Correction
      • 7.2.3.3 Color/Chroma Key
      • 7.2.3.4 Color/Chroma Key and Mixer/Blender
    • 7.2.4 TFT Interface
    • 7.2.5 Integrated PLL
  • 7.3 Register Descriptions
    • 7.3.1 Register Summary
    • 7.3.2 Video Processor Registers - Function 4
      • 7.3.2.1 Video Processor Support Registers - F4BAR0
      • 7.3.2.2 VIP Support Registers - F4BAR2
• Debugging and Monitoring
  • 8.1 Testability (JTAG)
    • 8.1.1 Mandatory Instruction Support
    • 8.1.2 Optional Instruction Support
    • 8.1.3 JTAG Chain
• Electrical Specifications
  • 9.1 General Specifications
    • 9.1.1 Electro Static Discharge (ESD)
    • 9.1.2 Power/Ground Connections and Decoupling
    • 9.1.3 Absolute Maximum Ratings
    • 9.1.4 Operating Conditions
    • 9.1.5 DC Current
      • 9.1.5.1 Power State Parameter Definitions
      • 9.1.5.2 Definition and Measurement Techniques of SC3200 Current Parameters
      • 9.1.5.3 Definition of System Conditions for Measuring On Parameters
      • 9.1.5.4 DC Current Measurements
    • 9.1.6 Ball Capacitance and Inductance
    • 9.1.7 Pull-Up and Pull-Down Resistors
  • 9.2 DC Characteristics
    • 9.2.1 INAB DC Characteristics
    • 9.2.2 INBTN DC Characteristics
    • 9.2.3 INPCI DC Characteristics
    • 9.2.4 INSTRP DC Characteristics
    • 9.2.5 INT DC Characteristics
    • 9.2.6 INTS DC Characteristics
    • 9.2.7 INTS1 DC Characteristics
    • 9.2.8 INUSB DC Characteristics
    • 9.2.9 OAC97 DC Characteristics
    • 9.2.10 ODn DC Characteristics
    • 9.2.11 ODPCI DC Characteristics
    • 9.2.12 Op/n DC Characteristics
    • 9.2.13 OPCI DC Characteristics
    • 9.2.14 OUSB DC Characteristics
    • 9.2.15 TSp/n DC Characteristics
      • 9.2.15.1 Exceptions
  • 9.3 AC Characteristics
    • 9.3.1 Memory Controller Interface
    • 9.3.2 Video Port
    • 9.3.3 TFT Interface
    • 9.3.4 ACCESS.bus Interface
    • 9.3.5 PCI Bus Interface
      • 9.3.5.1 Measurement and Test Conditions
    • 9.3.6 Sub-ISA Interface
    • 9.3.7 LPC Interface
    • 9.3.8 IDE Interface
    • 9.3.9 Universal Serial Bus (USB) Interface
    • 9.3.10 Serial Port (UART)
    • 9.3.11 Fast IR Port
    • 9.3.12 Parallel Port Interface
      • 9.3.12.1 Extended Capabilities Port (ECP)
    • 9.3.13 Audio Interface (AC97)
    • 9.3.14 Power Management Interface
    • 9.3.15 Power-Up Sequencing
    • 9.3.16 JTAG Interface
• Package Specifications
  • 10.1 Thermal Characteristics
    • 10.1.1 Heatsink Considerations
  • 10.2 Physical Dimensions
• Support Documentation
  • A.1 Order Information
  • A.2 Data Book Revision History