FINAL

Publication# 11560

Rev: G Amendment/+2

Issue Date: January 1998

Am28F256

256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

High performance

-- 70 ns maximum access time

CMOS Low power consumption

-- 30 mA maximum active current

-- 100 µA maximum standby current

-- No data retention power consumption

Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts

-- 32-pin PDIP

-- 32-pin PLCC

-- 32-pin TSOP

10,000 write/erase cycles minimum

Write and erase voltage 12.0 V

Latch-up protected to 100 mA
from 1 V to V

+1 V

Flasherase

Electrical Bulk Chip-Erase

-- One second typical chip-erase

Flashrite Programming

-- 10 µs typical byte-program

-- 0.5 second typical chip program

Command register architecture for
microprocessor/microcontroller compatible
write interface

On-chip address and data latches

Advanced CMOS flash memory technology

-- Low cost single transistor memory cell

Automatic write/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as
32 Kbytes of 8 bits each. AMD's Flash memories offer
the most cost-effective and reliable read/write non-
volatile random access memory. The Am28F256 is
packaged in 32-pin PDIP, PLCC, and TSOP versions. It
is designed to be reprogrammed and erased in-system
or in standard EPROM programmers. The Am28F256
is erased when shipped from the factory.

The standard Am28F256 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F256 has separate chip enable (CE

) and

output enable (OE

) controls.

AMD's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256 uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.

AMD's Flash technology reliably stores memor y
contents even after 10,000 erase and program cycles.

The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The Am28F256
uses a 12.0V

5% V

high voltage input to perform

the Flasherase

and Flashrite

algorithms.

The highest degree of latch-up protection is achieved
with AMD's proprietar y non-epi process. Latch-up
protection is provided for stresses up to 100 milliamps
on address and data pins from 1 V to V

+1 V.

The Am28F256 is byte programmable using 10 µs
programming pulses in accordance with AMD 's
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F256 is a
half a second. The entire chip is bulk erased using
10 ms erase pulses according to AMD's Flasherase
alrogithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15-20 minutes required for EPROM
erasure using ultra-violet light are eliminated.

Am28F256

Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F256 is designed to support either WE

or CE

controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE

or CE

whichever occurs last. Data is latched on the rising edge
of WE

or CE

whichever occurs first. To simplify the fol-

lowing discussion, the WE

pin is used as the write cycle

control pin throughout the rest of this text. All setup and
hold times are with respect to the WE

signal.

AMD's Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.

BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Family Part Number

Am28F256

Speed Options (V

= 5.0 V

10%)

-70

-90

-120

-150

-200

Max Access Time (ns)

120

150

200

CE# (E#) Access (ns)

120

150

200

OE# (G#) Access (ns)

Erase

Voltage

Switch

Command

Program

Voltage

Switch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Y-Gating

262,144

Bit

Cell Matrix

11560F-1

A0A14

OE#

CE#

WE#

VSS

VCC

To Array

DQ0DQ7

Input/Output

Buffers

Data

Latch

VPP

Address

Latch

Low VCC

Detector

Program/Erase

Pulse Timer

State

Control

Am28F256

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION
Am28F256
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

AM28F256

-70

OPTIONAL PROCESSING
Blank = Standard Processing
B

= Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (40°C to +85°C)
E = Extended (55°C to +125°C)

PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION
See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F256-70

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM28F256-90

AM28F256-120

AM28F256-150

AM28F256-200

Am28F256

PIN DESCRIPTION

A0A14

ddress Inputs for memory locations. Internal latches

hold addresses during write cycles.

)

Chip Enable active low input activates the chip's control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.

DQ0DQ7

Data Inputs during memor y write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.

No Connect-corresponding pin is not connected
internally to the die.

)

Output Enable active low input gates the outputs of the
device through the data buffers dur ing memor y
read cycles. Output Enable is high during command
sequencing and program/erase operations.

Power supply for device operation. (5.0 V

5% or 10%)

Program voltage input. V

must be at high voltage in

order to write to the command register. The command
register controls all functions required to alter the
memory array contents. Memory contents cannot be
altered when V

+2 V.

Ground

)

Write Enable active low input controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the
Write Enable pulse and the appropriate data is latched
on the rising edge of the pulse. Write Enable high
inhibits writing to the device.

Am28F256

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to
manage the command register. Erase and repro-
gramming operations use a fixed 12.0 V

5% high

voltage input.

Read Only Memory

Without high V

voltage, the device functions as a

read only memor y and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt-
age is applied to the V

pin. The erase and repro-

gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.

The device's command register is written using stan-
dard microprocessor write timings. The register con-
trols an internal state machine that manages all device
operations. For system design simplification, the de-
vice is designed to support either WE# or CE# con-
trolled writes. During a system write cycle, addresses
are latched on the falling edge of WE# or CE# which-
ever occurs last. Data is latched on the rising edge of
WE# or CE# whichever occur first. To simplify the fol-
lowing discussion, the WE# pin is used as the write
cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# sig-
nal.

Overview of Erase/Program Operations

FlasheraseTM Sequence

A multiple step command sequence is required to
erase the Flash device (a two-cycle Erase command
and repeated one cycle verify commands).

Note: The Flash memory array must be completely
programmed to 0's prior to erasure. Refer to the
FlashriteTM Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to

the command register.

2. Erase: Write the Erase command (same as Setup

Erase command) to the command register again.
The second command initiates the erase operation.
The system software routines must now time-out
the erase pulse width (10 ms) prior to issuing the
Erase-verify command. An integrated stop timer
prevents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to

the command register. This command terminates
the erase operation. After the erase operation,
each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify
command. This command verifies the margin and
outputs the addressed byte in order to compare the
a r r a y d a t a w i t h F F h d a t a ( B y t e e r a s e d ) .
After successful data verification the Erase-verify
command is written again with new address infor-
mation. Each byte of the array is sequentially veri-
fied in this manner.

If data of the addressed location is not verified, the
Erase sequence is repeated until the entire array is
successfully verified or the sequence is repeated
1000 times.

Flashrite

Programming Sequence

A three step command sequence (a two-cycle Program
command and one cycle Verify command) is required
to program a byte of the Flash array. Refer to the Flash-
rite

Algorithm.

1. Program Setup: Write the Setup Program com-

mand to the command register.

2. Program: Write the Program command to the com-

mand register with the appropriate Address and
Data. The system software routines must now time-
out the program pulse width (10 µs) prior to issuing
the Program-verify command. An integrated stop
timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-

mand to the command register. This command ter-
minates the programming operation. In addition,
this command verifies the margin and outputs the
byte just programmed in order to compare the array
data with the original data programmed. After suc-
cessful data verification, the programming se-
quence is initiated again for the next byte address to
be programmed.

If data is not verified successfully, the Program se-
quence is repeated until a successful comparison is
verified or the sequence is repeated 25 times.

Data Protection

The device is designed to offer protection against acci-
dental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. The device powers up in its read only state. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences.

The device also incorporates several features to pre-
vent inadvertent write cycles resulting from V

power-

up and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up

and power-down, the device locks out write cycles for

Am28F256

< V

LKO

(see DC Characteristics section for

voltages). When V

< V

LKO

, the command register is

disabled, all inter nal program/erase circuits are
disabled, and the device resets to the read mode. The
device ignores all writes until V

> V

LKO

. The user

must ensure that the control pins are in the correct logic
state when V

> V

LKO

to prevent uninitentional writes.

Write Pulse "Glitch" Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = V

, CE#

= V

or WE# = V

. To initiate a write cycle CE# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = V

and

OE# = V

will not accept commands on the rising

edge of WE#. The internal state machine is automat-
ically reset to the read mode on power-up.

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1.

Am28F256 Device Bus Operations (Notes 7 and 8)

Legend:
X = Don't care, where Don't Care is either V

or V

levels. V

PPL

= V

+ 2 V. See DC Characteristics for voltage levels

of V

PPH

. 0 V < An < V

+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:
1. V

PPL

may be grounded, connected with a resistor to ground, or < V

+ 2.0 V. V

PPH

is the programming voltage specified for

the device. Refer to the DC characteristics. When V

= V

PPL

, memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

< 13.0 V. Minimum V

rise time and fall time (between 0 and V

voltages) is 500 ns.

4. Read operation with V

= V

PPH

may access array data or the Auto select codes.

5. With V

at high voltage, the standby current is I

+ I

(standby).

6. Refer to Table 3 for valid D

during a write operation.

7. All inputs are Don't Care unless otherwise stated, where Don't Care is either V

or V

levels. In the Auto select mode all

addresses except A

and A

must be held at V

8. If V

1.0 Volt, the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F256 has a V

rise time and fall time specification of 500 ns minimum.

Operation

CE#
(E#)

OE#
(G#)

WE#
(W#)

(Note 1)

I/O

Read-Only

Read

PPL

OUT

Standby

PPL

HIGH Z

Output Disable

PPL

HIGH Z

Auto-select Manufacturer
Code (Note 2)

PPL

(Note 3)

CODE

(01h)

Auto-select Device
Code (Note 2)

PPL

(Note 3)

CODE

(A1h)

Read/Write

Read

PPH

OUT

(Note 4)

Standby (Note 5)

PPH

HIGH Z

Output Disable

PPH

HIGH Z

Write

PPH

(Note 6)

Am28F256

READ ONLY MODE

When V

is less than V

+ 2 V, the command register

is inactive. The device can either read array or autose-
lect data, or be standby mode.

Read

The device functions as a read only memory when V

< V

+ 2 V.

The device has two control functions. Both

must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe-
cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.

Address access time t

ACC

is equal to the delay from

stable addresses to valid output data. The chip enable
access time t

is the delay from stable addresses and

stable CE# to valid data at the output pins. The output
enable access time is the delay from the falling edge of
OE# to valid data at the output pins (assuming the ad-
dresses have been stable at least t

ACC

Standby Mode

The device has two standby modes. The CMOS
standby mode (CE# input held at V

0.5 V), con-

sumes less than 100 µA of current. TTL standby mode
(CE# is held at V

) reduces the current requirements

to less than 1mA. When in the standby mode the out-
puts are in a high impedance state, independent of the
OE# input.

If the device is deselected during erasure, program-
ming, or program/erase verification, the device will
draw active current until the operation is terminated.

Output Disable

Output from the device is disabled when OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.

Auto Select

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.

The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer
and type. This mode is intended for the purpose
of automatically matching the device to be pro-
grammed with its corresponding programming algo-
r ith m. Th is mo de is f unc tio nal ove r t he en tir e
temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment
must force V

(11.5 V to 13.0 V) on address A9. Two

identifier bytes may then be sequenced from the device
outputs by toggling address A

from V

to V

. All other

address lines must be held at V

, and V

must

less than or equal to V

+ 2.0 V while using this Auto

select mode. Byte 0 (A0 = V

) represents the manufac-

turer code and byte 1 (A0 = V

) the device identifier

code. For the device these two bytes are given in Table
2 below. All identifiers for manufacturer and device
codes will exhibit odd parity with the MSB (DQ7) de-
fined as the parity bit.

Table 2.

Am28F256 Auto Select Code

Type

Code

(HEX)

Manufacturer Code

Device Code

Am28F256

ERASE, PROGRAM, AND READ MODE

When V

is equal to 12.0 V ± 5%, the command reg-

ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.

Write Operations

High voltage must be applied to the V

pin in order to

activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.

The command register does not occupy an addressable
memory location. The register is a latch that stores the
command, along with the address and data information
needed to execute the command. The register is written
by bringing WE# and CE# to V

, while OE# is at V

Addresses are latched on the falling edge of WE#, while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.

The device requires the OE# pin to be V

for write op-

erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be V

, and CE# and WE#

must be V

. If any pin is not in the correct state a write

command will not be executed.

Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the V

pin. The device operates as a read only mem-

ory. High voltage on the V

pin enables the command

register. Device operations are selected by writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.

Read Command

Memory contents can be accessed via the read com-
mand when V

is high. To read from the device, write

00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.

The command register defaults to 00h (read mode)
upon V

power-up. The 00h (Read Mode) register de-

fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V

power

transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.

Table 3.

Am28F256 Command Definitions

Notes:
1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.

EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don't care.
Addresses are latched on the falling edge of the WE# pulse.

3. RD = Data read from location RA during read operation.

EVD = Data read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.

4. Refer to the appropriate section for algorithms and timing diagrams.

Command (Note 4)

First Bus Cycle

Second Bus Cycle

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Read Memory

Write

00h/FFh

Read

Read Auto select

Write

80h or 90h

Read

00h/01h

01h/A1h

Erase Set-up/Erase Write

Write

20h

Write

20h

Erase-Verify

Write

A0h

Read

EVD

Program Setup/Program

Write

40h

Write

Program-Verify

Write

C0h

Read

PVD

Reset Write

FFh

Write

FFh

Am28F256

FLASHERASE

ERASE SEQUENCE

Erase Setup

Erase Setup is the first of a two-cycle erase command.
It is a command-only operation that stages the device
for bulk chip erase. The array contents are not altered
with this command. 20h is written to the command reg-
ister in order to perform the Erase Setup operation.

Erase

The second two-cycle erase command initiates the
bulk erase operation. You must write the Erase com-
mand (20h) again to the register. The erase operation
begins with the rising edge of the WE# pulse. The
erase operation must be terminated by writing a new
command (Erase-verify) to the register.

This two step sequence of the Setup and Erase com-
mands helps to ensure that memory contents are not
accidentally erased. Also, chip erasure can only occur
when high voltage is applied to the V

pin and all con-

trol pins are in their proper state. In absence of this high
voltage, memory contents cannot be altered. Refer to
AC Erase Characteristics and Waveforms for specific
timing parameters.

Note: The Flash memory device must be fully
programmed to 00h data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable erasure.

Erase-Verify Command

The erase operation erases all bytes of the array
in parallel. After the erase operation, all bytes must be
sequentially verified. The Erase-verify operation is initi-

ated by writing A0h to the register. The byte address to
be verified must be supplied with the command. Ad-
dresses are latched on the falling edge of the WE#
pulse or CE# pulse, whichever occurs later. The rising
edge of the WE# pulse terminates the erase operation.

Margin Verify

During the Erase-verify operation, the device applies
an int er na lly g en erat ed ma rg in vo lta ge to th e
addressed byte. Reading FFh from the addressed byte
indicates that all bits in the byte are properly erased.

Verify Next Address

You must write the Erase-verify command with the ap-
propriate address to the register prior to verification of
each address. Each new address is latched on the fall-
ing edge of WE# or CE# pulse, whichever occurs later.
The process continues for each byte in the memory
array until a byte does not return FFh data or all the
bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verification then resumes at the address that failed to
verify. Erase is complete when all bytes in the array
have been verified. The device is now ready to be pro-
grammed. At this point, the verification operation is ter-
minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase

electrical erase algorithm, illustrate how

commands and bus operations are combined to per-
form electrical erasure. Refer to AC Erase Characteris-
tics and Waveforms for specific timing parameters.

Am28F256

FLASHERASE

ELECTRICAL ERASE ALGORITHM

This Flash memory device erases the entire array in
parallel. The erase time depends on V

, temperature,

and number of erase/program cycles on the device. In
general, reprogramming time increases as the number
of erase/program cycles increases.

The Flasherase electrical erase algorithm employs an
interactive closed loop flow to simultaneously erase all
bits in the array. Erasure begins with a read of the mem-
ory contents. The device is erased when shipped from
the factory. Reading FFh data from the device would
immediately be followed by executing the Flashrite pro-
gramming algorithm with the appropriate data pattern.

Should the device be currently programmed, data other
than FFh will be returned from address locations.
Follow the Flasherase algorithm. Uniform and reliable
erasure is ensured by first programming all bits in the
device to their charged state (Data = 00h). This is
accomplished using the Flashr ite Programming

algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFh) begins at
address 0000h and continues through the array to the
la s t a d d r e s s, o r u n t i l d a t a o t h e r t h a n F F h i s
encountered. If a byte fails to verify, the device is
er as e d ag a in . W i th ea ch er as e o pe r at io n , a n
increasing number of bytes verify to the erased state.
Typically, devices are erased in less than 100 pulses
(one second). Erase efficiency may be improved by
storing the address of the last byte that fails to verify in
a register. Following the next erase operation,
verification may start at the stored address location. A
total of 1000 erase pulses are allowed per reprogram
cycle, which corresponds to approximately 10 seconds
of cumulative erase time. The entire sequence of erase
and byte verification is performed with high voltage
applied to the V

pin. Figure 1 illustrates the electrical

erase algorithm.

Table 4.

Flasherase

Electrical Erase Algorithm

Notes:
1. See AC and DC Characteristics for values of V

parameters. The V

power supply can be hard-wired to the device or

switchable. When V

is switched, V

PPL

may be ground, no connect with a resistor tied to ground, or less than V

+ 2.0 V.

2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written

with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Bus Operations

Command

Comments

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite

programming algorithm (Figure 3) for

programming.

Standby

Wait for V

Ramp to V

PPH

(Note 1)

Initialize:
Addresses
PLSCNT (Pulse count)

Write

Erase Setup

Data = 20h

Erase

Data = 20h

Standby

Duration of Erase Operation (t

WHWH2

)

Write

Erase-Verify (Note 2)

Address = Byte to Verify
Data = A0h
Stops Erase Operation

Standby

Write Recovery Time before Read = 6 µs

Read

Read byte to verify erasure

Standby

Compare output to FFh
Increment pulse count

Write

Reset

Data = FFh, reset the register for read operations

Standby

Wait for V

Ramp to V

PPL

(Note 1)

Am28F256

Figure 2.

AC Waveforms For Erase Operations

ANALYSIS OF ERASE TIMING WAVEFORM

Note: This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite

Programming algorithm.

Erase Setup/Erase

This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.

Erase-Verify

Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).

After each erase operation each byte must be verified.
The byte address to be verified must be supplied with

Addresses

Data

11559G-7

20h

Section

A0h

Data

Out

Bus Cycle

Write

Time-out

Write

Time-out

Read

Standby

Command

20h

N/A

A0h

N/A

Compare

Data

N/A

Function

Erase
Setup

Erase

(10 ms)

Erase-

Verify

Transition

(6 µs)

Erase

Verification

Proceed per

Erase

Algorithm

Am28F256

the Erase-verify command (section D). Addresses are
latched on the falling edge of the WE# pulse.

Another software timing routine (6 µs duration) must be
executed to allow for generation of internal voltages for
margin checking and read operation (section E).

During Erase-verification (section F) each address that
returns FFh data is successfully erased. Each address
of the array is sequentially verified in this manner by re-
peating sections D thru F until the entire array is veri-
fied or an address fails to verify. Should an address

location fail to verify to FFh data, erase the device
again. Repeat sections A thru F. Resume verification
(section D) with the failed address.

Each data change sequence allows the device to use
up to 1,000 erase pulses to completely erase. Typically
100 erase pulses are required.

Note: All address locations must be programmed to
00h prior to erase. This equalizes the charge on all
memory cells and ensures reliable erasure.

FLASHRITE PROGRAMMING SEQUENCE

Program Setup

The device is programmed byte by byte. Bytes may be
programmed sequentially or at random. Program Setup
is the first of a two-cycle program command. It stages
the device for byte programming. The Program Setup
operation is performed by writing 40h to the command
register.

Program

Only after the program Setup operation is completed
will the next WE# pulse initiate the active programming
operation. The appropriate address and data for pro-
gramming must be available on the second WE# pulse.
Addresses and data are internally latched on the falling
and rising edge of the WE# pulse respectively. The ris-
ing edge of WE# also begins the programming opera-
tion. You must write the Program-verify command to
terminate the programming operation. This two step
sequence of the Setup and Program commands helps
to ensure that memory contents are not accidentally
written. Also, programming can only occur when high
voltage is applied to the V

pin and all control pins are

in their proper state. In absence of this high voltage,
memory contents cannot be programmed.

Refer to AC Characteristics and Waveforms for specific
timing parameters.

Program Verify Command

Following each programming operation, the byte just
programmed must be verified.

Write C0h into the command register in order to initiate
the Program-verify operation. The rising edge of this
WE pulse terminates the programming operation. The

Program-verify operation stages the device for verifica-
tion of the last byte programmed. Addresses were pre-
viously latched. No new information is required.

Margin Verify

During the Program-verify operation, the device applies
an internally generated margin voltage to the ad-
dressed byte. A normal microprocessor read cycle out-
puts the data. A successful comparison between the
programmed byte and the true data indicates that the
byte was successfully programmed. The original pro-
grammed data should be stored for comparison. Pro-
gramming then proceeds to the next desired byte
location. Should the byte fail to verify, reprogram (refer
to Program Setup/Program). Figure 3 and Table 5 indi-
cate how instructions are combined with the bus oper-
ations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for spe-
cific timing parameters.

Flashrite

Programming Algorithm

The device Flashrite

Programming algorithm employs

an interactive closed loop flow to program data byte by
byte. Bytes may be programmed sequentially or at ran-
dom. The Flashrite

Programming algorithm uses 10 µs

programming pulses. Each operation is followed by a
byte verification to determine when the addressed byte
has been successfully programmed. The program al-
gorithm allows for up to 25 programming operations per
byte per reprogramming cycle. Most bytes verify after
the first or second pulse. The entire sequence of pro-
gramming and byte verification is performed with high
voltage applied to the V

pin. Figure 3 and Table 5 il-

lustrate the programming algorithm.

Am28F256

Table 5.

Flashrite Programming Algorithm

Notes:
1. See AC and DC Characteristics for values of V

parameters. The V

power supply can be hard-wired to the device or

switchable. When V

is switched, V

PPL

may be ground, no connect with a resistor tied to ground, or less than V

+ 2.0 V.

2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register

is written with the read command.

Bus Operations

Command

Comments

Standby

Wait for V

Ramp to V

PPH

(Note 1)

Initialize Pulse counter

Write

Program Setup

Data = 40h

Program

Valid Address/Data

Standby

Duration of Programming Operation (t

WHWH1

)

Write

Program-Verify (Note 2)

Data = C0h Stops Program Operation

Standby

Write Recovery Time before Read = 6 µs

Read

Read Byte to Verify Programming

Standby

Compare Data Output to Data Expected

Write

Reset

Data = FFh, resets the register for read operations.

Standby

Wait for V

Ramp to V

PPL

(Note 1)

Am28F256

Figure 4.

AC Waveforms for Programming Operations

ANALYSIS OF PROGRAM TIMING WAVEFORMS

Program Setup/Program

Two-cycle write commands are required for program
operations (section A and B). The first program com-
mand (40h) is a Setup command and does not affect
the array data (section A). The second program com-
mand latches address and data required for program-
ming on the falling and rising edge of WE# respectively
(section B). The rising edge of this WE# pulse (section
B) also initiates the programming pulse. The device is
programmed on a byte by byte basis either sequentially
or randomly.

The program pulse occurs in section C.

Time-Out

A software timing routine (10 µs duration) must be initi-
ated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibility
of overprogramming by limiting each time-out period of
10 µs.

Program-Verify

Upon completion of the program timing routine, the mi-
croprocessor must write the program-verify command
(C0h). This command terminates the programming op-
eration on the rising edge of the WE# pulse (section D).
The program-verify command also stages the device
for data verification (section F). Another software timing
routine (6 µs duration) must be executed to allow for

Addresses

Data

11559G-9

Data

20h

Section

A0h

Data

Out

Bus Cycle

Write

Time-out

Write

Time-out

Read

Standby

Command

40h

Program

Address,

Program Data

N/A

C0h

(Stops

Program)

N/A

Compare

Data

N/A

Function

Program

Setup

Program

Command

Latch

Address and

Data

Program

(10 µs)

Program

Verify

Transition

(6 µs)

Program

Verification

Proceed per

Programming

Algorithm

Am28F256

generation of internal voltages for margin checking and
read operations (section E).

During program-verification (section F) each byte just
programmed is read to compare array data with original
program data. When successfully verified, the next de-
sired address is programmed. Should a byte fail to ver-
ify, reprogram the byte (repeat section A thru F). Each
data change sequence allows the device to use up to
25 program pulses per byte. Typically, bytes are verified
within one or two pulses.

Algorithm Timing Delays

There are four different timing delays associated with
the Flasherase

and Flashrite

algorithms:

1. The first delay is associated with the V

rise-time

when V

first turns on. The capacitors on the V

bus cause an RC ramp. After switching on the V

the delay required is proportional to the number of
devices being erased and the 0.1 mF/device. V

must reach its final value 100 ns before commands
are executed.

2. The second delay time is the erase time pulse width

(10 ms). A software timing routine should be run by
the local microprocessor to time out the delay. The
erase operation must be terminated at the conclu-
sion of the timing routine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, write
the Erase-verify operation after each pulse.

3. A third delay time is required for each programming

pulse width (10 ms). The programming algorithm is
interactive and verifies each byte after a program
pulse. The program operation must be terminated at
the conclusion of the timing routine or prior to exe-
cuting any system interrupts that may occur during
the programming operation.

4. A fourth timing delay associated with both the

Flasherase and Flashrite algorithms is the write re-
covery time (6 ms). During this time internal circuitry
is changing voltage levels from the erase/ program
level to those used for margin verify and read oper-
ations. An attempt to read the device during this pe-
riod will result in possible false data (it may appear
the device is not properly erased or programmed).

Note: Software timing routines should be written in
machine language for each of the delays. Code written
in machine language requires knowledge of the appro-
priate microprocessor clock speed in order to accu-
rately time each delay.

Parallel Device Erasure

Many applications will use more than one Flash
memory device. Total erase time may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Therefore each
device must be verified separately. When a device is
completely erased and verified use a masking code to
prevent further erasure. The other devices will continue
to erase until verified. The masking code applied could
be the read command (00h).

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V

1.0 Volt, the voltage difference between V

and V

should not exceed 10.0 Volts. Also, the device has V

rise time and fall time specification of 500 ns minimum.

Reset Command

The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).

The Reset command must be written two consecutive
times after the setup Program command (40h). This will
reset the device to the Read mode.

Following any other Flash command write the Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the
Read mode.

The Setup Program command (40h) is the only com-
mand that requires a two sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFh data is considered null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical "1" to "0"). The second Reset
command safely aborts the programming operation
and resets the device to the Read mode.

Memory contents are not altered in any case.

This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the setup Program state or not.

Programming In-System

Am28F256

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . 65

C to +150

Plastic Packages . . . . . . . . . . . . . . . 65

C to +125

Ambient Temperature
with Power Applied . . . . . . . . . . . . . .55

C to + 125

Voltage with Respect To Ground
All pins except A9 and V

(Note 1) . 2.0 V to +7.0 V

(Note 1). . . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V

(Note 2). . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During

voltage transitions, inputs may overshoot V

to 2.0 V for

periods of up to 20 ns. Maximum DC voltage on input and
I/O pins is V

+ 0.5 V. During voltage transitions, input

and I/O pins may overshoot to V

+ 2.0 V for periods up

to 20 ns.

2. Minimum DC input voltage on A9 and V

pins is 0.5 V.

During voltage transitions, A9 and V

may overshoot

to 2.0 V for periods of up to 20 ns. Maximum DC

input voltage on A9 and V

is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time. Du-

ration of the short circuit should not be greater than one
second.

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for extended
periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices
Ambient Temperature (T

). . . . . . . . . . . .0

C to +70

Industrial (I) Devices
Ambient Temperature (T

). . . . . . . . . .40

C to +85

Extended (E) Devices
Ambient Temperature (T

). . . . . . . . .55

C to +125

Supply Voltages

. . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.6 V

Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Am28F256

DC CHARACTERISTICS over operating range unless otherwise specified

TTL/NMOS Compatible

Notes:
1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V

or V

is applied. If V

1.0 Volt,

the voltage difference between V

and V

should not exceed 10.0 Volts. Also, the Am28F256 has a V

rise time and fall

time specification of 500 ns minimum.

2. I

CC1

is tested with OE# = V

to simulate open outputs.

3. Maximum active power usage is the sum of I

and I

4. Not 100% tested.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Leakage Current

= V

Max, V

= V

or V

1.0

µA

Output Leakage Current

= V

Max, V

OUT

= V

or V

1.0

µA

CCS

Standby Current

= V

Max, CE# = V

0.2

1.0

CC1

Active Read Current

CC =

Max, CE# = V

IL,

OE# = V

OUT

= 0 mA, at 6 MHz

CC2

Programming Current

CE#

Programming in Progress (Note 4)

CC3

Erase Current

CE#

Erasure in Progress (Note 4)

PPS

Standby Current

= V

PPL

1.0

µA

PP1

Read Current

= V

PPH

200

µA

= V

PPL

1.0

PP2

Programming Current

= V

PPH

Programming in Progress (Note 4)

PP3

Erase Current

= V

PPH

Erasure in Progress (Note 4)

Input Low Voltage

0.5

0.8

Input High Voltage

2.0

+ 0.5

Output Low Voltage

= 5.8 mA, V

= V

Min

0.45

OH1

Output High Voltage

= 2.5 mA, V

= V

Min

2.4

A9 Auto Select Voltage

A9 = V

11.5

13.0

A9 Auto Select Current

A9 = V

Max, V

= V

Max

µA

PPL

during Read-Only

Operations

Note: Erase/Program are inhibited
when V

= V

PPL

0.0

+2.0

PPH

during Read/Write

Operations

11.4

12.6

LKO

Low V

Lock-out Voltage

3.2

3.7

Am28F256

DC CHARACTERISTICS

CMOS Compatible

Notes:
1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V

or V

is applied. If V

1.0 volt,

the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F256 has a V

rise time and fall

time specification of 500 ns minimum.

2. I

CC1

is tested with OE# = V

to simulate open outputs.

3. Maximum active power usage is the sum of I

and I

4. Not 100% tested.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Leakage Current

= V

Max, V

= V

or V

1.0

µA

Output Leakage Current

= V

Max, V

OUT

= V

or V

1.0

µA

CCS

Standby Current

= V

Max, CE#

= V

+ 0.5 V

100

µA

CC1

Active Read Current

= V

Max, CE# = V

IL,

OE# = V

OUT

= 0 mA, at 6 MHz

CC2

Programming Current

CE# = V

Programming in Progress (Note 4)

CC3

Erase Current

CE# = V

Erasure in Progress (Note 4)

PPS

Standby Current

= V

PPL

1.0

µA

PP1

Read Current

= V

PPH

200

µA

PP2

Programming Current

= V

PPH

Programming in Progress (Note 4)

PP3

Erase Current

= V

PPH

Erasure in Progress (Note 4)

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 V

+ 0.5

Output Low Voltage

= 5.8 mA, V

= V

Min

0.45

OH1

Output High Voltage

= 2.5 mA, V

= V

Min

0.85 V

OH2

= 100 µA, V

= V

Min

0.4

A9 Auto Select Voltage

A9 = V

11.5

13.0

A9 Auto Select Current

A9 = V

Max, V

= V

Max

µA

PPL

during Read-Only

Operations

Note: Erase/Program are inhibited
when V

= V

PPL

0.0

+ 2.0

PPH

during Read/Write

Operations

11.4

12.6

LKO

Low V

Lock-out Voltage

3.2

3.7

Am28F256

SWITCHING TEST WAVEFORMS

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics--Read Only Operation

Notes:
1. Guaranteed by design not tested.

2. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F256 Speed Options

Unit

JEDEC

Standard

-70

-90

-120

-150

-200

AVAV

Read Cycle Time (Note 2)

Min

120

150

200

ELQV

Chip Enable AccessTime

Max

120

150

200

AVQV

ACC

Address Access Time

Max

120

150

200

GLQV

Output Enable Access Time

Max

ELQX

Chip Enable to Output in Low Z
(Note 2)

Min

EHQZ

Chip Disable to Output in High Z
(Note 1)

Max

GLQX

OLZ

Output Enable to Output in Low Z
(Note 2)

Min

GHQZ

Output Disable to Output in High Z
(Note 2)

Max

AXQX

Output Hold from first of Address,
CE#, or OE# Change (Note 2)

Min

WHGL

Write Recovery Time before Read

Min

µs

VCS

Setup Time to Valid Read

(Note 2)

Min

µs

11560G-15

3 V

0 V

Input

Output

1.5 V

Test Points

AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic "1" and 0 V for a logic "0". Input pulse rise and fall times
are

10 ns.

2.4 V

0.45 V

Input

Output

Test Points

2.0 V

0.8 V

AC Testing (all speed options except -70): Inputs are driven at
2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise
and fall times are

10 ns.

Am28F256

AC Characteristics--Write/Erase/Program Operations

Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally

on the device.

3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F256 Speed Options

Unit

JEDEC

Standard

-70

-90

-120

-150

-200

AVAV

Write Cycle Time (Note 4)

Min

120

150

200

AVWL

Address Set-up Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

WHGL

Write Recovery Time
before Read

Min

µs

GHWL

Read Recovery Time
before Write

Min

µs

ELWL

Chip Enable Set-up Time

Min

WHEH

Chip Enable Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse
Width HIGH

Min

WHWH1

Duration of Programming
Operation (Note 2)

Min

µs

WHWH2

Duration of
Erase Operation (Note 2)

Min

9.5

VPEL

Setup Time to

Chip Enable LOW (Note 4)

Min

100

VCS

Set-up Time to

Chip Enable LOW (Note 4)

Min

µs

VPPR

Rise Time

90% V

PPH

(Note 4)

Min

500

VPPF

Fall Time

10% V

PPL

(Note 4)

Min

500

LKO

< V

LKO

to Reset (Note 4)

Min

100

Am28F256

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. 25

C, 12 V V

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count

(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual
device limit.

LATCHUP CHARACTERISTICS

PIN CAPACITANCE

Note: Sampled, not 100% tested. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

Comments

Min

Typ

(Note 1)

Max

(Note 2)

Unit

Chip Erase Time

sec

Excludes 00h programming prior to erasure

Chip Programming Time

0.5

sec

Excludes system-level overhead

Write/Erase Cycles

10,000

Cycles

Min

Max

Input Voltage with respect to V

on all pins except I/O pins (Including A9 and V

)

1.0 V

13.5 V

Input Voltage with respect to V

on all pins I/O pins

1.0 V

+ 1.0 V

Current

100 mA

+100 mA

Includes all pins except V

. Test conditions: V

= 5.0 V, one pin at a time.

Parameter

Symbol

Parameter Description

Test Conditions

Typ

Max

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Input Capacitance

= 0

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

Am28F256

DATA SHEET REVISION SUMMARY FOR
AM28F256

Revision G

Deleted -75, -95, and -250 speed options. Matched for-
matting to other current data sheets.

Revision G+1

Figure 3, Flashrite Programming Algorithm: Moved end
of arrow originating from Increment Address box so
that it points to the PLSCNT = 0 box, not the Write Pro-
gram Verify Command box. This is a correction to the
diagram on page 6-189 of the 1998 Flash Memory
Data Book.

Revision G+2

Programming In A PROM Programmer:

Deleted the paragraph "(Refer to the AUTO SELECT
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de-
vice in-system)."

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM28F256-120FIB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM28F256-120FIB