Publication# 22206
Rev: D Amendment/0
Issue Date: November 1999
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Am79C978
PCnetTM- Home
Single-Chip 1/10 Mbps PCI Home Networking Controller
DISTINCTIVE CHARACTERISTICS
n
Fully integrated 1 Mbps HomePNA Physical
Layer (PHY) as defined by Home Phoneline
Networking Alliance (HomePNA) specification
1.1
-- Optimized for home networking applications
over ordinary telephone wire
-- In-band control features:
Adjustable power and speed levels
32 bits of reserved in-band messaging piggy-
backed on Ethernet packet
-- Register programmable features:
Power control
Performance registers
Speed control
Major frame timing parameters programma-
ble: ISBI, AID ISBI, pulse width, inter-symbol
time
n
Fully integrated 10 Mbps PHY interface
-- Comprehensive Auto-Negotiation
implementation
-- Full-duplex capability
-- Optimized for 10BASE-T applications
n
Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
-- 32-bit glueless PCI host interface
-- Supports PCI clock frequency from DC to
33 MHz independent of network clock
-- Supports network operation with PCI clock
from 15 MHz to 33 MHz
-- High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
-- PCI draft specification revision 2.2 compliant
-- Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
-- Supports both PCI 5.0-V and 3.3-V signaling
environments
-- Plug and Play compatible
-- Supports an unlimited PCI burst length
-- Big endian and little endian byte alignments
supported
-- Implements optional PCI power management
event (PME) pin
n
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 Ethernet standard
n
Media Independent Interface (MII) for
connecting external 10/100 Mbps transceivers
-- IEEE 802.3u compliant MII
-- Intelligent Auto-PollTM external PHY status
monitor and interrupt
-- Supports both auto-negotiable and non-
auto-negotiable external PHYs
-- Supports 10BASE-T, 100BASETX/FX,
100BASET4, and 100BASET2 IEEE 802.3
compliant MII PHYs at full-duplex or half-
duplex
n
Full-duplex operation supported on the MII port
with independent Transmit (TX) and Receive
(RX) channels
n
Supports PC98 and Net PC specifications
-- Implements full OnNow features including
pattern matching and link status wake-up
events
-- Implements Magic PacketTM mode
-- Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
-- Supports PCI Bus Power Management
Interface specification revision 1.1
-- Supports Advanced Configuration and
Power Interface (ACPI) specification version
1.0
-- Supports Network Device Class Power
Management specification version 1.0a
2
Am79C978
n
Independent internal TX and RX FIFOs
-- Programmable FIFO watermarks for both TX
and RX operations
-- RX frame queuing for high latency PCI bus
host operation
-- Programmable allocation of buffer space
between RX and TX queues
n
Extensive programmable internal/external
loopback capabilities
n
EEPROM interface supports jumperless design
and provides through-chip programming
-- Supports full programmability of half-/full-
duplex operation through EEPROM mapping
-- Programmable PHY reset output pin capable
of resetting external PHY without the need
for buffering
n
Extensive programmable LED status support
n
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame
n
Includes Programmable Inter Packet Gap (IPG)
to address less network aggressive MAC
controllers
n
Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
n
IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
mode for board-level production connectivity
test
n
Software compatible with AMD's PCnetTM
Family and LANCE/C-LANCE register and
descriptor architecture
n
Very low power consumption
n
+3.3 V power supply along with 5 V tolerant I/Os
enable broad system compatibility
n
Available in 144-pin TQFP and 160-pin PQFP
packages
GENERAL DESCRIPTION
The Am79C978 controller is the first in a series of home
networking products from AMD. The Am79C978 con-
troller is fabricated in an advanced low power 3.3 V
CMOS process to provide low operating current for
power sensitive applications.
The Am79C978 controller contains an Ethernet Con-
troller based on the Am79C971 Fast Ethernet control-
ler, a physical layer device for supporting the 802.3
standard for 10BASE-T, and a physical layer device for
data networking at speeds up to 1 Mbps over ordinary
residential telephone wiring.
The integrated PCI Ethernet controller is a highly inte-
grated 32-bit full-duplex, 10/100 Mbps Ethernet con-
troller solution designed to address high-performance
system application requirements. It is a flexible bus-
mastering device that can be used in any application,
including network ready PCs. The bus master architec-
ture provides high data throughput and low CPU and
system bus utilization.
The integrated Ethernet transceiver is a physical layer
device supporting the IEEE 802.3 standards for
10BASE-T. It provides all of the PHY layer functions re-
quired to support 10 Mbps data transfer speeds.
The integrated HomePNA transceiver is a physical
layer device that enables data networking at speeds up
to 1 Mbps over common residential phone wiring re-
gardless of topology and without disrupting telephone
(POTS) service.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to the PCI local bus, simplifying the de-
sign of an Ethernet or home network node in a PC
system. The device has built-in support for both little
and big endian byte alignment. The integrated home
networking controller's advanced CMOS design allows
the bus interface to be connected to either a +5.0 V or
a +3.3 V signaling environment. A compliant IEEE
1149.1 JTAG test interface for board level testing is
also provided, as well as a NAND tree test structure for
those systems that do not support the JTAG interface.
The integrated Am79C978 home networking controller
is also compliant with the PC98 and Net PC specifica-
tions. It includes the full implementation of the Mi-
crosoft OnNow and ACPI specifications, which are
backward compatible with Magic Packet technology. It
is also compliant with the PCI Bus Power Management
Interface specification by supporting the four power
management states (D0, D1, D2, and D3), the optional
PME pin, and the necessary configuration and data
registers.
The integrated Am79C978 home networking controller
is a complete Ethernet or home network node inte-
grated into a single VLSI device. It contains a bus inter-
face unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 88023 (IEEE 802.3)
compliant Media Access Controller (MAC), a Transmit
FIFO and a large Receive FIFO, and an IEEE 802.3u
compliant MII. Both IEEE 802.3 compliant full-duplex
and half-duplex operations are supported on the MII in-
terface. 10/100 Mbps operation is supported through
the MII interface.
The integrated Am79C978 home networking controller
is register compatible with the LANCE (Am7990) and
C-LANCE (Am79C90) Ethernet controllers and all
Am79C978
3
Ethernet controllers in the PCnet Family (except
I L A C C TM ( A m 7 9 C 9 0 0 ) ) , i n c l u d i n g P C n e t - I S A
(Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II
(Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI
(Am79C970), PCnet-PCI II (Am79C970A), PCnet-
FAST (Am79C971), and PCnet-FAST+ (Am79C972).
The Buffer Management Unit supports the LANCE and
PCnet descriptor software models.
While consuming minimal network resources, AMD's
innovative any1HomeTM Link Detection Packet for
HomePNA networks provides a means to indicate to
the MAC and thus the upper layers of the system pro-
tocol that a valid network (as defined by Home Net-
working Alliance) has been detected. The Link
Detection Packet is also capable of detecting a network
failure and allows the upper layer protocol to take cor-
rective action. Thus, the Link Detection Packet ensure
strict compliance to the Microsoft PC97, PC98, and
Home PNA requirements.
The integrated Am79C978 controller supports auto-
configuration in the PCI configuration space. Additional
integrated controller configuration parameters, includ-
ing the unique IEEE physical address, can be read
from an external non-volatile memory (EEPROM) im-
mediately following system reset.
In addition, the Am79C978 controller provides pro-
grammable on-chip LED drivers for transmit, receive,
collision, link integrity, Magic Packet status, speed, ac-
tivity, power output, address match, full-duplex, or 100
Mbps status.
Am79C978
5
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CONNECTION DIAGRAM (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Magic Packet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Ethernet Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
HomePNA PHY Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BASIC FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Auto-Poll External PHY Status Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
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