TAXIchip
TM
Integrated Circuits
Transparent Asynchronous
Transmitter/Receiver Interface
Am7968/Am7969-125
Am7968/Am7969-175
Data Sheet
and
Technical Manual
1994
1994 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD
assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.
Trademarks
AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc.
TAXIchip and TAXI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Table of Contents
iii
TABLE OF CONTENTS
Am7968/Am7969 TAXIchip Integrated Circuits
Am7968/Am7969
Data Sheet
1
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Am7968/Am7969
Technical Manual
50
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Chapter 1
Introduction
50
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1.1 The Am7968 TAXI
TM
Transmitter
50
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1.2 The Am7969 TAXI Receiver
52
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Chapter 2
Using the TAXIchip Set
52
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2.1 Data and Command
52
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2.2 Operational Modes: Local, Cascade and Test
53
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Chapter 3
Data Encoding, Violation and Syncs
53
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3.1 Data Encoding
53
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3.2 Violation Logic
57
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3.3 TAXI PLL Characteristics
57
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Chapter 4
Clock Generation and Distribution
59
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4.1 TAXI Transmitter Clock Connections
59
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4.1.1 Local Mode Transmitters
60
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4.2 TAXI Receiver Clock Connections
60
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4.2.1 Cascade Mode Receivers (Am7969-125 only)
61
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Chapter 5
Interfacing with the Serial Media
61
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5.1 Very Short Link, DC Coupled
62
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5.2 Terminated, DC Coupled
63
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5.3 Terminated, AC Coupled
63
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5.4 Baseline Wander and the AC Coupling Capacitor
64
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5.5 Interfacing to Fiber Optic Transmitters/Receivers
66
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5.5.1 DC-Coupled TAXl-Fiber Optic Transceiver Interface
66
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5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface
68
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5.6 Interfacing to Coaxial Cable
68
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5.7 Interfacing to Twisted-Pair Cable
70
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Chapter 6
Board Layout Considerations
71
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6.1 Printed Circuit Board Layout
71
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6.1.1 Rules for Layout
71
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6.2 Layout using Fiber Optic Data Links
73
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AMD
Table of Contents
iv
Chapter 7
Cascade Mode Operation
74
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7.1 Transmit Cascaded Data with a Single TAXI Transmitter
76
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7.2 Receivers In Cascade Mode: Connections (Am7969-125 only)
79
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7.3 Auto-Repeat Configuration
81
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7.3.1 Receiver Connections in Auto-Repeat Configuration
81
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7.3.2 Timing Limitations of the Auto-Repeat Configuration
84
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7.4 Unbalanced Configuration (Am7968/Am7969-125 only)
85
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Chapter 8
Test Mode
86
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8.1 Transmitter Connections
87
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8.2 Receiver Connections
89
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8.3 Timing Relationships in Test Mode
89
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Appendix A
Optical Components Manufacturers
90
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Appendix B
Error Detection Efficiency
91
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Appendix C
TAXI TIPs
94
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Publication# 07370
Rev. F
Amendment /0
Issue Date: April 1994
Advanced
Micro
Devices
Am7968/Am7969
TAXIchip
TM
Integrated Circuits
(Transparent Asynchronous Xmitter-Receiver Interface)
FINAL
DISTINCTIVE CHARACTERISTICS
s
Parallel TTL bus interface
-- Eight Data and four Command Pins
-- or nine Data and three Command Pins
-- or ten Data and two Command Pins
s
Transparent synchronous serial link
-- +5 V ECL Serial I/O
-- AC or DC coupled
-- NRZI 4B/5B, 5B/6B encoding/decoding
s
Drive coaxial cable or twisted pair directly
s
Easy interface with fiber optic data links
s
32140 Mbps (417.5 Mbyte/s) data
throughput
s
Asynchronous input using STRB/ACK
s
Automatic MUX/DEMUX of Data and Command
s
Complete on-chip PLL, Crystal Oscillator
s
Single +5 V supply operation
s
28-pin PLCC or DIP or LCC
GENERAL DESCRIPTION
The Am7968 TAXIchip Transmitter and Am7969
TAXIchip Receiver Chipset is a general-purpose inter-
face for very high-speed (417.5 Mbyte/s, 40175
Mbaud serially) point-to-point communications over co-
axial or fiber-optic media. The TAXIchip set
emulates a
pseudo-parallel register. They load data into one side
and output it on the other, except in this case, the "other"
side is separated by a long serial link.
The speed of a TAXIchip system is adjustable over a
range of frequencies, with parallel bus transfer rates of
4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
high end. The flexible bus interface scheme of the
TAXIchip set accepts bytes that are either 8, 9, or
10 bits wide. Byte transfers can be Data or Command
signaling.
BLOCK DIAGRAM
Am7968
Note:
N can be 8, 9, or 10 bits; total of N + M = 12.
07370F-1
Strobe (STRB)
Acknowledge (ACK
Clock (CLK)
Data Mode Select (DMS)
Test Serial In
(TSERIN)
Test/Local Select (TLS)
Strobe &
Acknowledge
Oscillator
and
Clock Gen.
Serial Interface
Shifter
Data Encoder
Encoder Latch
Input Latch
Media
Interface
(SEROUT+) Serial Out +
(SEROUT) Serial Out
Data
Command
N
M
X1
X2
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