PRELIMINARY
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Publication# 21191
Rev: C Amendment/+2
Issue Date: March 1998
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Am29LV002
2 Megabit (256 K x 8-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
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Single power supply operation
-- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
-- Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
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High performance
-- Full voltage range: access times as fast as 100
ns
-- Regulated voltage range: access times as fast
as 90 ns
s
Ultra low power consumption (typical values at
5 MHz)
-- Automatic Sleep Mode: 200 nA
-- Standby mode: 200 nA
-- Read mode: 10 mA
-- Program/erase mode: 20 mA
s
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
-- Supports control code and data storage on a
single device
-- Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
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Top or bottom boot block configurations
available
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Embedded Algorithms
-- Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
-- Embedded Program algorithms automatically
write and verify bytes or words at specified
addresses
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Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
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Package option
-- 40-pin TSOP
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Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power supply Flash
-- Superior inadvertent write protection
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Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
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Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting
program or erase cycle completion
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Erase Suspend/Erase Resume feature
-- Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
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Hardware reset pin (RESET#)
-- Hardware method to reset the device to the read
mode
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Am29LV002
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV002 is a 2 Mbit, 3.0 Volt-only Flash
memory organized as 262,144 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This is achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
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