S3455

SONET/SDH/ATM OC-48 4-BIT TRANSCEIVER WITH CDR

January 24, 2002 / Revision A

BiCMOS LVPECL CLOCK GENERATOR

DEVICE
SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

S3455

FEATURES

· CMOS 0.18 micron technology
· Complies with Bellcore and ITU-T specifications
· On-chip high-frequency PLL for clock

generation and clock recovery

· Supports OC-48 (2488.32 Mbps) with FEC
· Reference frequency of 155.52 MHz to 166.62 MHz
· Interface to LVDS and LVCMOS logic
· 4-bit LVDS data path
· 196 FC-PBGA
· Diagnostic loopback mode
· Supports line timing
· Lock detect
· Signal detect input
· Low jitter LVDS interface
· Internal FIFO to decouple transmit clocks
· Single 1.8 V supply
· Typical power under 1.0 W
· Available in die form

APPLICATIONS

· Wavelength Division Multiplexing (WDM)

equipment

· SONET/SDH-based transmission systems
· SONET/SDH modules
· SONET/SDH test equipment
· ATM over SONET/SDH
· Section repeaters

Figure 1. System Block Diagram

SONET/SDH/ATM OC-48 4-BIT TRANSCEIVER WITH CDR

S3455

· Add Drop Multiplexers (ADM)
· Broad-band cross-connects
· Fiber optic terminators
· Fiber optic test equipment

GENERAL DESCRIPTION

The S3455 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-48
(2.488 Gbps 2.670 Gbps) interface device. The
S3455 receives an OC-48 scrambled Non-Return to
Zero (NRZ) signal and recovers the clock from the
data. The chip performs all necessary serial-to-paral-
lel and parallel-to-serial functions in conformance
with SONET/SDH transmission standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.

On-chip clock synthesis is performed by the high-
frequency Phase-Locked Loop (PLL) on the S3455
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
155.52 MHz (or 166.62 MHz) reference clock in sup-
port of existing system clocking schemes.

The low jitter LVDS interface is compliant with the bit-
error rate requirements of the Bellcore and ITU-T
standards. The S3455 is packaged in a 196 FC-
PBGA, offering designers a small package outline. The
S3455 is also available in die form.

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S3455

S3455

SONET/SDH/ATM OC-48 4-BIT TRANSCEIVER WITH CDR

January 24, 2002 / Revision A

S3455 OVERVIEW

The S3455 transceiver implements SONET/SDH seri-
alization/deserialization, and transmission functions.
The block diagram in Figure 2 shows the basic opera-
tion of the chip. This chip can be used to implement
the front end of SONET equipment, which consists
primarily of the serial transmit interface and the serial
receive interface. The chip handles all the functions of
these two elements, including parallel-to-serial and
serial-to-parallel conversion, clock generation, and
system timing. The system timing circuitry consists of
management of the data stream and clock distribution
throughout the front end. Table 1 shows the sug-
gested interface devices for the S3455.

The S3455 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:

Transmitter Operations:

1. 4-bit parallel input
2. Parallel-to-serial conversion
3. Serial output

Receiver Operations:

1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. 4-bit parallel output

Internal clocking and control functions are transpar-
ent to the user.

Table 1. Sugggested Interface Devices

S3455

SONET/SDH/ATM OC-48 4-BIT TRANSCEIVER WITH CDR

January 24, 2002 / Revision A

S3455 TRANSCEIVER
FUNCTIONAL DESCRIPTION

TRANSMITTER OPERATION

The S3455 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48 data stream. It converts 4-bit parallel data to
bit serial format at 2488.32 Mbps (or equivalent FEC
rate).

A high-frequency bit clock can be generated from a
155.52 or 166.62 MHz frequency reference by using
an integral frequency synthesizer consisting of a
Phase-Locked Loop (PLL) circuit with a divider in
the loop.

Diagnostic loopback (transmitter to receiver) and
line loopback (receiver to transmitter) is provided.
See Other Operating Modes.

Clock Synthesizer

The clock synthesizer, shown in the block diagram
in Figure 2, is a monolithic PLL that generates the
serial output clock frequency locked to the input Ref-
erence Clock (CSU-REFCLK).

The REFCLKP/N1 or REFCLKP/N2 input must be
generated from a crystal oscillator which has a fre-
quency accuracy that meets the value stated in
Table 7 in order for the Transmit Serial Clock
(TSCLK) frequency to have the same accuracy re-
quired for operation in a SONET system. The
REFCLK must meet the phase noise requirements
shown in Figure 11 to meet the jitter generation
specifications given in Table 7. Lower accuracy
crystal oscillators may be used in applications less
demanding than SONET/SDH.

The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the CSU-REFCLK input, a loop filter
which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.

The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.

Timing Generator

The timing generation function, seen in Figure 2,
provides a divide-by-4 rate version of the transmit
serial clock. This circuitry also provides an internally gen-
erated load signal, which transfers the PINP/N[3:0]
data from the FIFO to the serial shift register.

The PCLK output is a divide-by-4 rate version of the
transmit serial clock. PCLK is intended for use as a
divide-by-4 clock for upstream multiplexing and over-
head processing circuits. Using PCLK for upstream
circuits will ensure a stable frequency and phase re-
lationship between the data coming into and leaving
the S3455 device.

The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the CSU-REFCLK. The PLL in the clock
synthesizer maintains the stability of the synthesized
clock by comparing the phase of the internal clock
with that of the CSU-REFCLK.

Table 2. Reference Jitter Limits

S3455

SONET/SDH/ATM OC-48 4-BIT TRANSCEIVER WITH CDR

January 24, 2002 / Revision A

Parallel-to-Serial Converter

The parallel-to-serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PINP/N[3:0]
bus on the rising edge of PICLK. The parallel-to-serial
register is a loadable shift register which takes its paral-
lel input from the FIFO output.

An internally generated divide-by-4 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.

FIFO

A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide-
by-4 clock is used to clock out data from the FIFO.
Phase Initialization (PHINIT) and Lock Detect
(LOCKDET) are used to center or reset the FIFO.
The PHINIT and LOCKDET signals will center the
FIFO after the third PICLK pulse. This is in order to
insure that PICLK is stable. This scheme allows the
user to have an infinite PCLK to PICLK delay
through the ASIC. Once the FIFO is centered, the
PCLK to PICLK delay can have a maximum drift as
specified by Table 16.

FIFO Initialization

The FIFO can be initialized in one of the following
three ways:

1. During power up, once the PLL has locked to the

reference clock provided on the REFCLKP/N1 or
REFCLKP/N2 pins, the LOCKDET will go active
and initialize the FIFO.

2. When RSTB goes active, the entire chip is reset.

This causes the PLL to go out of lock and thus
the LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held in reset
when RSTB is active.

3. The user can also initialize the FIFO by raising

PHINIT.

During normal operation, the incoming data is passed
from the PICLK timing domain to the internally gener-
ated divide-by-4 clock domain. Although the
frequency of PICLK and the internally generated clock
are the same, their phase relationship is arbitrary. To

prevent errors caused by short setup or hold times
between the two timing domains, the timing generator
circuitry monitors the phase relationship between
PICLK and the internally generated clock. When a
potential setup or hold time violation is detected, the
phase error becomes active. When Phase Error
(PHERR) conditions occur, PHINIT should be acti-
vated to recenter the FIFO (at least 2 PCLK periods).
This can be done by connecting PHERR to PHINIT.
When realignment occurs, up to ten bytes of data will
be lost. The user can also take in the PHERR signal,
process it and send an output to PHINIT in such a
way that idle bytes are lost during the realignment
process. PHERR will go inactive when the realign-
ment is complete.

RECEIVER OPERATION

The S3455 transceiver chip provides the first stage
of the digital processing of a receive SONET STS-48
bit-serial stream. It converts the bit-serial 2.488 Gbps
(or equivalent FEC rate) data stream into a 4-bit par-
allel data format. A loopback mode is provided for
diagnostic loopback (transmitter to receiver). A line
loopback (receiver to transmitter) is also provided.

Clock Recovery

The S3455 clock recovery device performs the clock
recovery function for SONET OC-48 serial data links.
The chip extracts the clock from the serial data inputs
and provides retimed clock and data outputs. A 155.52
MHz or 166.62 MHz reference clock is used for phase
locked loop start up and proper operation under loss of
signal conditions. An integral prescaler and phase
locked loop circuit is used to multiply this reference to
the nominal bit rate.

The clock recovery generates a clock that is at the
same frequency as the incoming data bit rate at the
serial data input. The clock is phase aligned by a
PLL so that it samples the data in the center of the
data eye pattern.

The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.

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