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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
March 24, 2000 / Revision A
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3057
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock
generation
Supports OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps)
Reference frequency of 155.52 MHz
Interface to LVPECL and TTL logic
16-Bit single-ended LVPECL data path
Compact 156 TBGA package
Diagnostic loopback mode
Supports line timing
Lock Detect
Signal detect input
Low jitter LVPECL interface
Internal FIFO to decouple transmit clocks
Single 3.3V supply
Typical power 1.5 W
APPLICATIONS
Wavelength Division Multiplexing (WDM)
equipment
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
Figure 1. System Block Diagram
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
S3057
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3057 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization
SONET OC-48 (2488.32 Mbps), OC-24 (1244.16
Mbps), Gigabit Ethernet (1250 Mbps), OC-12
(622.08 Mbps) and OC-3 (155.52 Mbps) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based WDM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3057
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
155.52 MHz reference clock in support of existing
system clocking schemes.
The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3057 is packaged in a 156
TBGA, offering designers a small package outline.
S3056
Clock
Recovery
Unit
S3052
Receive
S3052
Transmit
S3057
Transmit
Serialization
S3057
Receive
Deserialization
S3056
Clock
Recovery
Unit
S3052
Receive
S3052
Transmit
S3057
Transmit
Serialization
S3057
Receive
Deserialization
2.488 Gbps
2.488 Gbps
155.52 Mbps
155.52 Mbps
2.488 Gbps
2.488 Gbps
PERFORMANCE MONITOR
PERFORMANCE MONITOR
E/O
O/E
OPTICAL FIBER
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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
March 24, 2000 / Revision A
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the opti-
cal level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
forms a single international standard for fiber inter-
connect between telephone networks of different
countries. SONET is capable of accommodating a
variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signaling
rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-
N signal is an optical carrier level-N
signal (OC-
N). The S3057 chip supports up to the OC-
48 rate (2.488 Gbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-48 consists of 144 transport overhead bytes
followed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 144 overhead and 4176 SPE
bytes is repeated nine times in each frame. Frame and
byte boundaries are detected using the A1 and A2
bytes found in the transport overhead. (See Figure 3.)
For more details on SONET operation, refer to the
Bellcore SONET Standard document.
Table 1. SONET Signal Hierarchy
Figure 2. SONET Structure
Figure 3. STS48/OC48 Frame Format
9 Rows
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
sec
s
s
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Functions
Elec.
CCITT
Optical Data Rate (Mbit/s)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
March 24, 2000 / Revision A
S3057 OVERVIEW
The S3057 transceiver implements SONET/SDH se-
rialization/deserialization, and transmission
functions. The block diagram in Figure 4 shows the
basic operation of the chip. This chip can be used to
implement the front end of SONET equipment, which
consists primarily of the serial transmit interface and
the serial receive interface. The chip handles all the
functions of these two elements, including parallel-to-
serial and serial-to-parallel conversion, clock
generation, and system timing. The system timing
circuitry consists of management of the data stream
and clock distribution throughout the front end.
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Table 2. Data Rate Select
The S3057 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user.
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Suggested Interface Devices
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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
March 24, 2000 / Revision A
Figure 4. S3057 Transceiver Functional Block Diagram
CLOCKS
LOCKDET
155MCKP/N
19MCK
PCLKP/N
PHERR
TSDP/N
TSCLKP/N
OVREF
POUT[15:0]
POCLKP/N
TIMGEN
16:1
PARALLEL
TO SERIAL
CLOCK
SYNTHESIZER
D
TXDP/N
TXCLKP/N
POCLK (Internal)
REFCLKP/N
PICLKP/N
TXDP/N
(Internal)
TXCLKP/N
(Internal)
RSCLKP/N
DLEB
SQUELCH
IVREF
RSTB
SDLVPECL
SDTTL
RSDP/N
KILLRXCLK
LLEB
PIN[15:0]
BYPASS
TESTEN
CAP2
CAP1
RLPTIME
PHINIT
D
D
D
1:16
SERIAL TO
PARALLEL
TIMGEN
R
16
2
16
RATESEL[1:0]
BYPASSCLKP/N
SLPTIME
TX
RX
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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
March 24, 2000 / Revision A
S3057 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3057 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48/STS-24/STS-12/STS-3/GBE data stream
depending on the data rate selected. It converts 16
bit parallel data to bit serial format at 2488.32/
1244.16/622.08/155.52/1250 Mbps.
A high-frequency bit clock can be generated from a
155.52 MHz frequency reference by using an inte-
gral frequency synthesizer consisting of a
phase-locked loop circuit with a divider in the loop.
Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock frequency locked to the input
Reference Clock (REFCLKP/N).
The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy
that meets the value stated in Table 8 in order for
the TSCLK frequency to have the same accuracy
required for operation in a SONET system. Lower
accuracy crystal oscillators may be used in applica-
tions less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The Timing Generation function, seen in Figure 4,
provides a divide-by-16 version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[15:0] data from
the parallel input register to the serial shift register.
The PCLK output is a divide-by-16 rate version of
transmit serial clock (divide-by-16). PCLK is intended
for use as a divide-by-16 clock for upstream multi-
plexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3057 device.
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the reference clock REFCLK. The PLL in
the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the in-
ternal clock with that of the Reference Clock
(REFCLK).
Table 3. Reference Jitter Limits
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