1
S3053
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
February 12, 1999 / Revision C
S3053
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
FEATURES
Supports 2.5 Gbit/sec data rates
Fully differential for minimum
jitter accumulation
TTL select
High speed 50
source terminated outputs
0.84 W typical power dissipation
3.3 V power supply
52 Pin TQFP/TEP
Figure 1. S3053 Block Diagram
DEVICE
SPECIFICATION
GENERAL DESCRIPTION
The S3053 is a high performance quad mux with fan
out buffers. It is designed to minimize jitter accumu-
lation by providing a high bandwidth fully differential
signal path. It can be used to switch OC-48 data
signals in Dense Wavelength Division Multiplexer
designs and other high speed serial switch designs.
The chip is designed using four 2:1 multiplexers. It
can be used to fan out and/or multiplex high speed
clock and data signals. The S3053 is compatible
with the AMCC OC-48 clock recovery, MUX/DEMUX
and Crosspoint Switch products. This allows signal
integrity to be maintained throughout the system de-
sign.
The primary AC parameter of importance is the de-
terministic jitter or data eye degradation inserted by
the crosspoint. The design minimizes jitter accumu-
lation by using high bandwidth, low skew fully differ-
ential circuits. This provides for symmetric rise and
fall delays as well as noise rejection.
SELA
INA0P
INA0N
INA1P
INA1N
OUTC0P
OUTC0N
OUTC1P
OUTC1N
MUX
A
MUX
B
MUX
C
MUX
D
SELB
SELC
SELD
OUTB0P
OUTB0N
OUTB1P
OUTB1N
IND0P
IND0N
IND1P
IND1N
0
1
0
1
0
1
0
1
2
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
S3053
February 12, 1999 / Revision C
A
L
E
S
B
L
E
S
C
L
E
S
D
L
E
S
B
T
U
O
C
T
U
O
0
0
0
0
0
A
N
I
0
A
N
I
0
0
0
1
0
A
N
I
0
A
N
I
0
0
1
0
0
A
N
I
0
D
N
I
0
0
1
1
0
A
N
I
1
D
N
I
0
1
0
0
0
D
N
I
0
A
N
I
0
1
0
1
1
D
N
I
0
A
N
I
0
1
1
0
0
D
N
I
0
D
N
I
0
1
1
1
1
D
N
I
1
D
N
I
1
0
0
0
1
A
N
I
1
A
N
I
1
0
0
1
1
A
N
I
1
A
N
I
1
0
1
0
1
A
N
I
0
D
N
I
1
0
1
1
1
A
N
I
1
D
N
I
1
1
0
0
0
D
N
I
1
A
N
I
1
1
0
1
1
D
N
I
1
A
N
I
1
1
1
0
0
D
N
I
0
D
N
I
1
1
1
1
1
D
N
I
1
D
N
I
Table 1. Truth Table
3
S3053
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
February 12, 1999 / Revision C
Figure 2. Timing Waveforms
Figure 3. Differential Voltage
INA0,1
IND0,1
OUTB0,1
OUTC0,1
T
1
V SINGLE
Single-ended
swing
V DIFF
2X Single-ended
swing
=
Programable Swing Control
An external resistor can be connected across adjacent pins, VSWx to VEEx, where x is B0, B1, C0 and C1. This
will result in a decreased Vswing for the specified output and a decrease in chip power dissipation. For example,
if a 700 Ohm resistor is used, the Vswing will decrease from its full scale swing of approximately 570mV to
250mV and that specific output will draw approximately 13mA less. All four outputs can be independently set. If
no external resistor is used, the output swing will default to its full scale value. See Figure 7.
The 700 Ohm value is only used as an example. The power concious user could use as small a resistor value as
the application can handle.
4
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
S3053
February 12, 1999 / Revision C
e
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1
B
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1
B
T
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3
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1
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1
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.
f
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4
5
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1
9
.
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B
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C
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9
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x
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C
C
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,
9
1
,
8
,
6
,
1
2
,
0
2
,
4
3
,
2
3
,
6
4
,
5
4
,
7
4
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V
3
.
3
.
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l
p
p
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S
r
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w
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0
B
W
S
V
1
B
W
S
V
0
C
W
S
V
1
C
W
S
V
g
o
l
a
n
A
I
5
1
5
2
2
2
1
.
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p
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t
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C
g
n
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w
S
e
g
a
t
l
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E
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V
,
3
1
,
7
,
1
,
6
2
,
4
1
,
1
3
,
7
2
,
5
3
,
3
3
,
0
4
,
9
3
,
8
4
,
4
4
,
2
5
.
d
n
u
o
r
G
0
B
E
E
V
1
B
E
E
V
0
C
E
E
V
1
C
E
E
V
t
u
p
t
u
O
D
N
G
6
1
4
2
3
1
1
.
1
C
,
0
C
,
1
B
,
0
B
r
o
f
d
n
u
o
r
G
Table 2. Pin Assignment and Descriptions
5
S3053
2.5 GBIT QUAD MUX WITH FAN OUT BUFFERS
February 12, 1999 / Revision C
Figure 4. S3053 Pinout Package
1
2
3
4
5
7
9
11
39
38
37
36
34
32
30
28
TOP VIEW
35
33
31
29
27
15
14
16
17
18
19
20
21
22
23
25
24
26
51
52
50
49
48
47
46
45
44
43
41
42
40
12
8
10
6
VSWC0
VEEC0
OUTC0P
OUTC0N
OUTC1N
VEEC1
VSWC1
OUTC1P
13
INA1N
VEE
INA1P
SELB
VEE
VCC
VCC
VCC
VEE
SELA
INA0N
INA0P
VEE
VSWB0
VEE
VEEB0
OUTB0P
OUTB0N
VCC
VCC
VCC
OUTB1N
OUTB1P
VSWB1
VEEB1
VEE
VEE
IND1N
IND1P
SELD
VCC
VCC
SELC
IND0N
VEE
VEE
VEE
IND0P
VEE
VEE
VEE
VEE
VCC
VCC
S3053
52 Pin TQFP/TEP
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