1
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM CLOCK RECOVERY UNIT
S3027
FEATURES
Complies with Bellcore and ITU-T
specifications for jitter tolerance, jitter transfer
and jitter generation
On-chip high frequency PLL with internal loop
filter for clock recovery
Supports clock recovery for OC-12/STM-4
(S3027A) (622.08 Mbit/s) or
OC-3/STM-1 (155.52 Mbit/s) (S3027A-1)
NRZ data
19.44 MHz reference frequency
Lock detect--monitors run length (S3027A only)
and frequency
350mW typical power dissipation
Low-jitter PECL interface
Maintains downstream clock in absence of data
inputs
Micro-power Bipolar technology
5V supply
Available in a 20 TSSOP package
GENERAL DESCRIPTION
The function of the S3027 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3027 is implemented using
AMCC's proven Phase Locked Loop (PLL) technology.
The S3027 receives either an OC-12/STM-4 or OC-3/
STM-1 scrambled NRZ signal and recovers the clock
from the data. The chip outputs a differential PECL
bit clock and retimed data. Figure 1 shows a typical
network application.
The S3027 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 2.
Figure 1. System Block Diagram
Transceiver
S3028
Controller
Controller
Transceiver
S3028
8
8
8
8
Fiber
Optic
Module
Fiber
Optic
Module
S3027
S3027
2
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Figure 2. Functional Block Diagram
SERCLKOP/N
LOCKDET
SERDATOP/N
TTLREF
BYPASS
MODE
LCKREFN
SERDATIP/N
LOOP
FILTER
VCO
CLOCK
DIVIDER
PHASE DETECTOR
LOCK
DETECTOR
SD
CAP 1,2
3
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
OVERVIEW
The S3027 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate and
clock recovery is performed on the incoming data
stream. An external crystal is required to minimize
the PLL lock time and provide a stable output clock
source in the absence of serial input data. Retimed
data and clock are output from the S3027.
CHARACTERISTICS
Performance
The S3027 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used with differential
inputs and outputs as shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in
Figure 5. The measurement condition is that the input
sinusoidal jitter up to the mask level in Figure 4 be
applied for each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 U.I. when a serial data input
with less than 14 ps (OC-12) or 56 ps (OC-3) rms
jitter is presented to the serial data inputs.
Figure 3. Clock Output to Data Transition Delay
Output Frequency
622.08 MHz
155.52 MHz
SERDATOP/N Setup Time
450 ps
2.5 ns
SERDATOP/N Hold Time
450 ps
2.5 ns
t su
t h
SERCLKOP
SERDATOP/N
Figure 4. Input Jitter Tolerance Specification
f0
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
12
10
30
300
25
250
3
10
30
300
6.5
65
Figure 5. Jitter Transfer Specification
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
OC/STS
Level
fc
(kHz)
P
(dB)
12
1,2
500
0.1
3
1,2
130
2.0
1. Bellcore Specifications: TR-NWT-000253, Issue 2,
December 1991.
2. CCITT Recommendations: G.958.
4
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
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5
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Table 1. S3027 Pin Assignment and Descriptions (Continued)
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6
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Figure 6. S3027A TSSOP Package
All dimensions are in mm.
Table 2. Clock and Data Output Control
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S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Table 4. Recommended Operating Conditions
Table 3. Absolute Maximum Ratings
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S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Table 6. TTL Input/Output DC Characteristics
1
1. These input levels provide a zeronoise immunity and should only be tested in a static, noise-free environment.
(T
A
= -40
C to +85
C, V
CC
= 5 V
5%)
Table 5. Performance Specifications
1 Guaranteed but not tested.
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9
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Table 7. PECL Input/Output DC Characteristics
(T
A
= -40
C to +85
C, V
CC
= 5 V
5%)
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R1
R1
1
F
CAP1
CAP2
Figure 7. External Loop Filter
R1 = 68
for 622.08 MBit/s operation.
R1 = 84
for 155.52 MBit/s operation.
10
S3027
SONET/SDH/ATM CLOCK RECOVERY UNIT
October 18, 1999 / Revision E
Ordering Information
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