S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

BiCMOS LVPECL CLOCK GENERATOR

DEVICE
SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

S3019

FEATURES

· Complies with Bellcore and ITU-T

specifications

· On-chip high-frequency PLLs for clock

generation and clock recovery

· Supports 155.52 Mbps (OC-3) and 622.08

Mbps (OC-12)

· Selectable reference frequencies of 19.44,

38.88, 51.84 or 77.76 MHz

· Interface to both LVPECL and TTL logic
· Simple interface with 3.3 V or 5 V Optical

modules

· Directly compatible with 3.3 V or 5 V network

interface devices

· 8-bit TTL data path
· Compact 14 mm 80 PQFP package
· Diagnostic loopback mode
· Lock detect
· Low jitter LVPECL interface
· Single 3.3 V supply

APPLICATIONS

· SONET/SDH-based transmission systems
· SONET/SDH modules
· SONET/SDH test equipment
· ATM over SONET/SDH
· Section repeaters
· Add Drop Multiplexers (ADM)
· Broad-band cross-connects
· Fiber optic terminators
· Fiber optic test equipment

Figure 1. System Block Diagram

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

S3019

GENERAL DESCRIPTION

The S3019 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbit/s) and OC-3 (155.52 Mbps) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.

On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3019
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3019 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes.

The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3019 is packaged in a
14 mm 80 PQFP, offering designers a small package
outline.

S3019

SONET/SDH

Transceiver

Network

Interface

Processor

Network

Interface

Processor

S3019

SONET/SDH

Transceiver

OTX

ORX

OTX

ORX

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

SONET OVERVIEW

Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.

The SONET standard is a layered protocol with four
separate layers defined. These are:

· Photonic
· Section
· Line
· Path

Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signal-
ing rates.

Data Rates and Signal Hierarchy

Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport

signal level-1 (STS-1). An STS-

N signal is made up

N byte-interleaved STS-1 signals. The optical

counterpart of each STS-

N signal is an optical carrier

level-

N signal (OC-N). The S3019 chip supports OC-3

and OC-12 rates (155.52 and 622.08 Mbit/s).

Frame and Byte Boundary Detection

The SONET/SDH fundamental frame format for
STS-12 consists of 36 transport overhead bytes fol-
lowed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 36 overhead and 1044 SPE bytes
is repeated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)

For more details on SONET operations, refer to the
Bellcore SONET standard document.

Elec.

ITU-T

Optical Data Rate (Mbit/s)

STS-1

OC-1

51.84

STS-3

STM-1

OC-3

155.52

STS-12

STM-4

OC-12

622.08

STS-24

STM-8

OC-24

1244.16

STS-48 STM-16

OC-48 2488.32

Table 1. SONET Signal Hierarchy

Figure 2. SONET Structure

Figure 3. STS12/OC12 Frame Format

0 bps

End Equipment

Payload to
SPE mapping

Maintenance,
protection,
switching

Optical
transmission

Scrambling,
framing

Fiber Cable

End Equipment

Section layer

Photonic layer

Line layer

Path layer

Section layer

Photonic layer

Line layer

Layer Overhead

(Embedded Ops

Channel)

Functions

576 Kbps

192 Kbps

9 Rows

12 A1

Bytes

12 A2

Bytes

A1 A1

A2 A2

Transport Overhead 36 Columns
36 x 9 = 324 bytes

Synchronous Payload Envelope 1044 Columns
1044 x 9 = 9396 bytes

125

sec

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

S3019 OVERVIEW

The S3019 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation and recovery, and
system timing. The system timing circuitry consists
of management of the data stream, framing, and
clock distribution throughout the front end.

The S3019 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:

Transmitter Operations:

1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output

AMCC CONGO (S1201) POS/ATM SONET Mapper

AMCC NILE (S1202) ATM SONET Mapper

Table 2. Suggested Interface Devices

Receiver Operations:

1. Clock and data recovery from serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output

Internal clocking and control functions are transpar-
ent to the user.

A lock detect feature is provided on the S3019,
which indicates that the PLL is locked (synchronized)
to the incoming data stream, and facilitates continu-
ous down-stream clocking in the absence of data.

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

RECEIVER OPERATION

The S3019 transceiver chip provides the first stage
of digital processing of a receive SONET STS-3 or
STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbps data stream into a 19.44 or
77.76 Mbps 8-bit parallel data format.

Clock recovery is performed on the incoming
scrambled NRZ data stream. A 19.44 or 77.76 MHz
reference clock is required for phase locked loop
start-up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit is used to multiply this reference to the
nominal bit rate.

A loopback mode is provided for diagnostic loopback
(transmitter to receiver).

S3019 TRANSCEIVER
FUNCTIONAL DESCRIPTION

TRANSMITTER OPERATION

The S3019 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12-bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbps data stream into bit
serial format at 155.52 or 622.08 Mbps.

A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.

Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes on page 7.

Clock Synthesizer

The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).

The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 9 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.

The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.

The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.

Timing Generation

The timing generation function, seen in Figure 4,
provides a byte rate version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[7:0] data from
the parallel input register to the serial shift register.

The PCLK output is a byte rate version of transmit
serial clock at 19.44 or 77.76 MHz. PCLK is intended
for use as a byte speed clock for upstream multiplex-
ing and overhead processing circuits. Using PCLK
for upstream circuits will ensure a stable frequency
and phase relationship between the data coming into
and leaving the S3019 device.

Parallel-to-Serial Converter

The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.

The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed relationship
to PCLK. If PICLK is tied to PCLK, the PIN[7:0] data
latched into the parallel register will meet the timing
specifications with respect to the load signal. If PICLK
is not tied to PCLK, the delay must meet the timing
requirements shown in Table 14.

Table 3. Reference Frequency Options

Table 4. Reference Jitter Limits

* Only valid in SLP mode.

]

[

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Lock Detect

The S3019 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the received
serial data fails the run length or frequency test, the
PLL will be forced to lock to the local reference clock.
This will maintain the correct frequency of the POCLK
output under loss of signal or loss of lock conditions. If
the serial data inputs have a run length greater than
80-bit times with no transitions, the PLL will be de-
clared out of lock. In addition, if the recovered clock
frequency deviates from the local reference clock fre-
quency by more than the specified ppm, the PLL will
also be declared out of lock. The lock detect circuit will
poll the input data stream in an attempt to reacquire
lock to data. If the recovered clock frequency is deter-
mined to be within the specified ppm and the run
length check indicates valid data, the PLL will be de-
clared in lock and the lock detect output will go active.
See Table 9.

Backup Reference Generator

The backup reference generator seen in Figure 4
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock REFCLKP/N.

Frame and Byte Boundary Detection

The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected and
OOF is no longer set High. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming
data stream (RSD or looped transmitter data). The
timing generator block takes the located byte bound-
ary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUTP/N[7:0]). The frame boundary is reported on
the Frame Pulse (FP) output when any 48-bit pattern
matching the framing pattern is detected on the in-
coming data stream. When framing pattern detection
is disabled, the byte boundary is frozen to the loca-
tion found when detection was previously enabled.
Only framing patterns aligned to the fixed byte
boundary are indicated on the FP output.

Figure 5. Clock Recovery Jitter Tolerance

25k 65k

250k

6.5k

300

0.15

1.5

Jitter Frequency (Hz)

Jitter
Amplitude
(Ul p-p)

Minimum proposed

tolerance

(TA-NWT-000253)

OC-12

OC-3

Clock Recovery

Clock recovery, as shown in the block diagram in
Figure 4, generates a clock that is at the same fre-
quency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a PLL so that it samples
the data in the center of the data eye pattern.

The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.

Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by greater than the
value specified in Table 9 with respect to
REFCLKP/N, the PLL will be declared out of lock,
and the PLL will lock to the reference clock. The
assertion of LOS will also cause an out of lock condi-
tion.

The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal. This transfer function yields the
typical capture time stated in Table 9 for random
incoming NRZ data.

The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 5.

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occurrence
of the pattern, is expected to be less than the required
250

s, even for extremely high bit error rates.

Once down-stream overhead circuitry has verified
that frame and byte synchronization are correct, the
OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern

Serial-to-Parallel Converter

The Serial to Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial-to-parallel con-
version clocked by the clock recovery block. The
second is an 8-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries as determined by the frame and
byte boundary detection block. On the falling edge of
the free running POCLK, the data in the holding reg-
ister is transferred to an output holding register
which drives POUT[7:0].

The delay through the serial-to-parallel converter
can vary from 1.5 to 3.5 byte periods (12 to 28 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of that
byte. The variation in the delay is dependent on the
alignment of the internal parallel load timing, which is
synchronized to the data byte boundaries, with respect
to the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.

(See Figures 13 through 15.)

Parity Calculation and Detection

The receiver section calculates odd parity for the
POUT[7:0] signals and provides the result at the
PAROUT pin. For example:

POUT[7:0] = 1001 1000; PAROUT = 1
POUT[7:0] = 1100 1001; PAROUT = 0

The transmitter performs parity error detection over
the PIN[7:0] data and the PARIN input. The result of
the detection is provided at the PARERR output.
Note that the PARIN should be calculated by the
same method as the receiver section PAROUT.

OTHER OPERATING MODES

Diagnostic Loopback

When the Diagnostic Loopback Enable (DLEB) input is
low, a loopback from the transmitter to the receiver
at the serial data rate can be set up for diagnostic
purposes. The differential serial output data from the
transmitter is routed to the serial-to-parallel block in
place of the normal data stream (RSD). SDPECL
must be High for diagnostic loopback.

Line Loopback

The Line Loopback circuitry consists of alternate
clock and data output drivers. For the S3019, it se-
lects the source of the data and clock which is
output on TSD and TSCLK. When the Line
Loopback Enable input (LLEB) is high, it selects
data and clock from the Parallel to Serial Converter
block. When LLEB is Low and BYPASS is inactive,
the recovered clock is used to retime the incoming
data before driving the TSDP/N output. The
TSCLKP/N output will be driven by the recovered
clock. When LLEB is Low and BYPASS is active,
the RSCLKP/N input is used to retime the incoming
data before driving the RSDP/N input.

Serial Loop Timing

In Serial Loop Timing mode (SLPTIME), the clock
synthesizer PLL of the S3019 is bypassed, and the
timing of the entire transmitter section is controlled
by the receive serial clock. This mode is entered
using the SLPTIME input.

In this mode the REFCLKP/N input is not used, and
the MODE[1:0] inputs are ignored for all transmit
functions. It should be carefully noted that the inter-
nal PLL continues to operate in this mode, and
continues as the source for the (19, 38, 51)
MHZCLK, and if these signals are being used (e.g.
as the reference for an external clock recovery de-
vice), the REFCLKP/N and MODE[1:0] inputs must
be properly driven.

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Reference Loop Timing

In reference loop timing mode, the clock synthesizer
PLL is still used as the clock source for the transmit
section. However, the parallel receive clock is used
as the reference clock for the clock synthesizer PLL.
The MODE[1:0] inputs must be in the 1,1 state for
STS-12 operation or 0,NC for STS-3 operation.

Forward Clocking

For both 77.78 MHz and 38.88 MHz reference op-
eration, the S3019 operates in the forward clocking
mode. The PLL locks the PCLK output of the trans-
mitter section to the REFCLK with a fixed and
repeatable phase relation. This allows the transmit-
ter data source to also be the timing source for the
serial clock synthesis.

The rising edge of PCLK is locked to the rising edge
of REFCLKP, with a maximum delay of 8 to 10 nsec
due to the PCLK TTL output driver.

For operation at 19.44 MHz and 51.84 MHz refer-
ences, separate timing paths are use for PLL control
and PCLK generation, and forward clocking is not
recommended.

"Squelched Clock" Operation

Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state if the optical signal is
removed or reduced below a fixed threshold. This
condition is accompanied by the expected
deassertion of the signal detect output.

The S3019 has been designed (BYPASS mode) for
operation with clock recovery devices that provide
continuous serial clock for seamless downstream
clocking in the event of optical signal loss. For op-
eration with an optical transceiver that provides the
"squelched clock" behavior as described above, the
S3019 can be operated in the "squelched clock
mode" by activating the SQUELCH pin.

In this condition, the receive serial clock RSCLKP/N
is used for all receiver timing when the SDPECL/
SDTTL inputs are in the active state. When the
SDPECL/SDTTL inputs are place in the inactive
state (usually by the deassertion of LOCKDET or
signal detect from the optical transceiver/clock re-
covery unit) the transmitter serial clock will be used
to maintain timing in the receiver section. This will
allow the POCLK to continue to run and the parallel
outputs to flush out the last received characters and
the assume the all zero state imposed at the serial
data input.

It is important to note that in this mode there will be a
random 1.6 nsec shortening or lengthening of the
POCLK cycle, resulting in an apparent phase shift in
the POCLK at the deassertion of the SD condition.
Another similar phase shift will occur when the SD
condition is reasserted.

In the normal operating mode with both BYPASS
and SQUELCH inputs inactive, there will be no
phase discontinuities at the POCLK output during
signal loss or reacquisition (assuming operation with
continuous clocking from the CRU device such as
the AMCC S3026 or S3027).

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 5. S3019 Transmitter Pin Assignment and Descriptions (Active High unless otherwise stated.)

]

[

(

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(

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S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 6. S3019 Receiver Pin Assignment and Descriptions (Active High unless otherwise stated.)

)

(

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(

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S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 6. S3019 Receiver Pin Assignment and Descriptions (Active High unless otherwise stated.)Cont'd

]

[

]

[

Table 7. S3019 Common Pin Assignment and Descriptions

8
7

(

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S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 8. S3019 Power and Ground Pin Assignments

)

(

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(

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(

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(

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S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 9. Performance Specifications

* Noise on REFCLKP/N should be less than 14 ps rms in a jitter frequency band from 12 kHz to 5 MHz.

)

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S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 11. Recommended Operating Conditions

Table 12. LVTTL Input/Output DC Characteristics

Parameter

Description

Min

Typ

Units

Conditions

VOH

Output High Voltage (TTL)
3.3V Power Supply
3.3V Power Supply

2.1
2.2

2.0

-500

Max

V
V

VCC = min, IOH = -2.4 mA

VCC = min, IOH = -.1 mA

ICC

Supply Current

300

Outputs open, VCC = VCC max

Power Dissipation

1.0

360

1.25

Outputs open, VCC = VCC max

VOL

Output Low Voltage (TTL)
3.3V Power Supply

VCC = min, IOL = 2.4 mA

VIH

VIL

IIH

IIL

Input High Voltage (TTL)

Input Low Voltage (TTL)

Input High Current (TTL)

Input Low Current (TTL)

5.5

0.8

-50

VIN = 2.4 V

VIN = 0.5 V

ESD Ratings
The S3019 is rated to the following ESD voltages based on the human body model:
1. All pins are rated at or above 1500 V except pin3, pin11, pin12 and pin25.

Table 10. Absolute Maximum Ratings

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

Table 14. Transmitter AC Timing Characteristics

Table 13. LVPECL Input/Output DC Characteristics

Table 15. Receiver AC Timing Characteristics

]

[

]

[

0
1

]

[

]

[

1. Setup and hold times are specified for an interface which directly connects the S3019 receiver parallel outputs

to the data and clock inputs on an external register.

Description

VIL

VIH

VIL

VIH

VOL

VOH
VOD

VID
IIHD
IILD

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Guaranteed Input Low Voltage
for single-ended inputs

Guaranteed Input High Voltage
for single-ended inputs

Guaranteed Input Low Voltage
for differential inputs

Guaranteed Input High Voltage
for differential inputs

termination to VCC -2 V

Differential Output Voltage

Differential Input Voltage

VID = 500 mV
VID = 500 mV

-0.500

0.390

0.200

0.500

VCC -2.000

VCC -1.225

VCC -1.441

VCC -0.570

VCC -2.000

VCC -0.700

VCC -1.750

VCC -0.450

VCC -2.000

VCC -1.500

VCC -1.210

VCC -0.670

Volts

20.000

100

-100

1.400

1.330

Output Diff. Voltage

Input Diff. Voltage

Diff. Input High Current

Diff. Input Low Current

IIH

SD Inputs have internal 24 k to
1.8 V load resistor.

Single-ended input
High Current

IIL

Single-ended input
Low Current

Parameter

Min

Typ

Max

Unit

Conditions

]

[

]

[

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

RECEIVER FRAMING

Figure 13 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF and remains enabled while OOF is
High. Both boundaries are recognized upon receipt
of the third A2 byte which is the first data byte to be
reported with the correct byte alignment on the out-
going data bus (POUT[7:0]). Concurrently, the frame
pulse is set High for one POCLK cycle.

When interfacing with a section terminating device,
the OOF input remains High for one full frame after
the first frame pulse while the section terminating
device verifies internally that the frame and byte
alignment are correct, as shown in Figure 14. Since
at least one framing pattern has been detected since
the rising edge of OOF, boundary detection is dis-
abled when OOF is set Low.

The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active
until the first FP pulse or until OOF goes Low, which-
ever occurs last. Figure 13 shows a typical OOF
timing pattern which occurs when the S3019 is con-
nected to a down stream section terminating device.
OOF remains High for one full frame after the first
FP pulse. The frame and byte boundary detection
block is active until OOF goes Low.

Figure 15 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and
deactivated by the first FP pulse.

Figure 13. Frame and Byte Boundary Detection

NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles

Figure 14. OOF Operation Timing

Figure 15. Alternate OOF Timing

Note 1

A2 (28H)

Invalid Data

Valid
Data

RECOVERED

CLOCK/

REFCLK

OOF

RSD

POUT[7:0]

POCLK

BOUNDARY DETECTION ENABLED

OOF

BOUNDARY DETECTION ENABLED

OOF

S3019

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

April 12, 2000 / Revision F

S3019 WITH DATA CLOCK SYNCHRONOUS TO
REFERENCE CLOCK

In some applications it is necessary to "forward
clock" the data in a SONET/SDH system. In this ap-
plication the reference clock from which the High
speed serial clock is synthesized and the parallel
data clock both originate from the same (usually
TTL/CMOS) clock source. This application note ex-
plains how the AMCC S3019 can be configured to
operate in this mode.

Clock Control Logic Description

The timing control logic in the S3019 automatically
generates an internal load signal which has a fixed
relationship to the reference clock. The logic takes in
to account the variation of the reference clock to the
internal load signal over temperature and voltage.

The connections required to implement the design
are shown in Figure 16. The setup and hold times for
the PICLK to the data must be met by the controller
ASIC. It is recommended that the data on the falling
edge of the output reference clock be latched in or-
der to meet the required specifications.

Possible Problems

In order to meet the jitter generation specifications
required by SONET, the jitter of the reference clock
must be minimized. It may be difficult to meet the
SONET jitter generation specifications using a refer-
ence clock input with a TTL reference source.

APPLICATION NOTE

ASIC

Data

P/N[7:0]

PICLK

REFCLK

Serial Data

S3019

Output

Reference

Clock

Output

Data

Figure 16. S3019 with Data Clocked by Reference Clock

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