1
EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
October 26, 1999
EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
DESCRIPTION
The S3031B Evaluation Board provides a flexible platform for verifying the operation of the S3031B transceiver
interface circuit. This data sheet provides information on board contents. It should be used in conjunction with
the S3031B data sheet, which contains full technical details on chip operation.
Figure 1 shows the outline of the S3031B Evaluation Board and Figure 2 shows the block diagram of how the
S3031B Evaluation Board should be connected to test equipment for BER testing. In this configuration the
S3031B is configured for use with the internal S3031B Clock Recovery Unit (CRU), using a 19.44 MHz or 38.88
MHz reference and operating at STS-3.
Figure 1. Evaluation Board Top View
AMCC
S3031B
E4/STM-1/
OC-3
ON OFF
ON OFF
RSDATIN
RSDATIP
RSDATON
RSDATOP
RSCLKON
RSCLKOP
XFMR
RXCABI
TXMONO
XFMR
LCV
RXRSTB
LOSOUT (LED)
XFMR
RXCBLO
TSDATIN
TSDATIP
TSDATON
TSDATOP
TSCLKON
TSCLKOP
REFCLK
LVTTL XTAL
OSCILATOR
SWITCH1
SWITCH2
AGND
AVCC
RINVTT
TINVTT
DGND
-V
DGND
DVCC
+V
DVCC
XFRMSTATB
XFRMSTATA
TREFCLKOUT
TXRSTB
TSTCLKEN
DLCV
POUT0
POCLK
POUT1
POUT2
POUT3
PIN0
PIN1
PIN2
PIN3
CMISEL
XFRMENA
SERDATEN
XFRMENB
LOSOPT
REFSEL
LLEB
DLEB
SERDSEL
EQUALSEL
4 x 5 Pin Header
AGND2
TESTCLK
AGND3
AGND4
AGND1
5
5
4
4
3
3
2
2
1
1
1
2
EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
October 26, 1999
Figure 2 depicts how the S3031B Evaluation board can be connected for BER measurements, and shows all of
the DIP switch settings and the level shifted ECL (LSECL) power supply requirements for use with test equip-
ment that utilizes 50
to ground termination.
Figure 2. BER Test Setup
REFCLK
S3031B RECEIVER
BER TEST SETUP
DATA DATA
CLOCK
CLOCK
EQUALSEL(OPTICAL INPUT)
'0'
SERDSEL
'1'
DLEB
'0'
LLEB
'0'
REFSEL
'1'
LOSOPT
'1'
SERDATEN
'0'
XFRMENA
'0'
XFRMENB
'0'
DLCV
'0'
TSTCLKEN
'0'
SWITCH SETTINGS
CMISEL
'0'
('0' for 38.8MHz Refclk)
('1' for CMI mode)
('1' for cable input)
EXT INPUT (155MHz)
TRIGGER OUT
CLOCK/8
HP8133A
DATA DATA
CLOCK
CLOCK
19MHz
BIAS FOR LSECL
DVCC(+5V)
DVCC(+5V)
+V(+2V)
DGND(0V)
-V(-3V)
DGND(0V)
TINVTT(0V)
RINVTT(0V)
AVCC(+5V)
AGND(0V)
J30
1
2
3
4
5
6
7
8
9
10
ON BOARD POWER TERMINAL
EXT INPUT
TSCLKOP
TSCLKON
TSDATOP
TSDATON
TSDATIN
TSDATIP
RSCLKOP
RSCLKON
RSDATOP
RSDATON
RSDATIN
RSDATIP
ERROR AND JITTER ANALYZER
DATA (CMI ENCODED) CLOCK(155MHz)
RXCABI
WG SF-60 PDH/SDH
(Needed to test CMI decoding of RXCABI data)
BERT RX
BERT TX
S3031B DEMO BOARD
TEKTRONIX 700 GENERATOR
TEKTRONIX 700 ANALYZER
RXCBLO
3
EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
October 26, 1999
Figure 3 depicts how the S3031B receiver section of the evaluation board can be connected for BER measure-
ments and jitter testing, and shows all of the DIP switch settings and the power supply requirements for use with
test equipment that utilizes 50
to -2V termination.
Figure 3. Receiver BER and Jitter Test Setup
S3031B RX EYE OPENING TEST SETUP
BIAS FOR LSECL
DVCC(+5V)
DVCC(+5V)
+V(0V)
DGND(0V)
-V(-5V)
DGND(0V)
TINVTT(-2V)
RINVTT(-2V)
AVCC(+5V)
AGND(0V)
1
2
3
4
5
6
7
8
9
10
ON BOARD POWER TERMINAL
BERT TX(155.52 MHz)
S3031B EVALUATION BOARD
RSDATIN
RSDATIP
RSDATON
RSDATOP
RSCLKON
RSCLKOP
DATA
DATA
CLOCK
2^7-1 PRBS DATA PATTERN
DATA
CLOCK
CLOCK
2^7-1 PRBS DATA PATTERN
BERT RX (155.52 MHz)
EQUALSEL(OPTICAL INPUT) '0'
SERDSEL '1'
DLEB '0'
LLEB '0'
REFSEL '1'
LOSOPT '1'
SWITCH 1
TRIGGER
MEASURE DATA EYE
SCOPE
CASCADE MICROTECH
ECL TERMINATOR
VTT= -2.45V
SERDATEN '0'
XFRMENA '0'
XFRMENB '0'
DLCV '0'
TSTCLKEN '0'
CMISEL '0'
SWITCH 2
DIPSWITCH SETTINGS
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EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
October 26, 1999
Figure 4 depicts how the S3031B Transmitter section of the Evaluation board can be connected for BER
measurements and Jitter testing, and shows all of the DIP switch settings and the power supply requirements for
use with test equipment that utilizes 50
to ground termination.
Figure 4. Transmitter BER and Jitter Test Setup
S3031B TX EYE OPENING TEST SETUP
BIAS FOR LSECL
DVCC(+5V)
DVCC(+5V)
+V(0V)
DGND(0V)
-V(-5V)
DGND(0V)
TINVTT(-2V)
RINVTT(-2V)
AVCC(+5V)
AGND(0V)
1
2
3
4
5
6
7
8
9
10
ON BOARD POWER TERMINAL
BERT TX(155.52 MHz)
S3031B EVALUATION BOARD
TSDATIN
TSDATIP
TSDATON
TSDATOP
TSCLKON
TSCLKOP
DATA
DATA
CLOCK
2^7-1 PRBS DATA PATTERN
DATA
CLOCK
CLOCK
2^7-1 PRBS DATA PATTERN
BERT RX (155.52 MHz)
EQUALSEL(OPTICAL INPUT) '0'
SERDSEL '1'
DLEB '0'
LLEB '0'
REFSEL '1'
LOSOPT '1'
SWITCH 1
TRIGGER
MEASURE DATA EYE
SCOPE
CASCADE MICROTECH
ECL TERMINATOR
VTT= -2.45V
SERDATEN '0'
XFRMENA '0'
XFRMENB '0'
DLCV '0'
TSTCLKEN '0'
CMISEL '0'
SWITCH 2
DIPSWITCH SETTINGS
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EV3031B
E4/STM-1/OC-3 ATM EVALUATION BOARD
October 26, 1999
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3031B Evaluation Board can
be configured with ECL, PECL and level shifted (LSECL) I/O so that the board can be configured to operate with
different types of standard test equipment. Figures 5 through 7 demonstrate the different types of input and
output waveforms that the S3031B Evaluation Board can output with the different voltage settings of VCC and
VEE as per Table 1. Note that the TTL I/O's voltage level will change to non-standard levels when the S3031B
Evaluation Board is powered by the different voltage.
Figure 5.
Figure 6.
VCC = 0V
-0.8V
-1.3V
-1.8V
Termination = 50
to -2V
LVECL
VEE = -5V +/- 5%
Termination = 50
to GND
LSECL
VCC = +2V
+1.2V
+0.7V
+0.2V
VEE = -3V +/- 5%
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