Altera Corporation

ACEX 1K

Programmable Logic Device Family

June 2001, ver. 3.1

Data Sheet

A-DS-ACEX-3.1

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Features...

Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device

Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions

Dual-port capability with up to 16-bit width per embedded array
block (EAB)

Logic array for general logic functions

High density

10,000 to 100,000 typical gates (see

Table 1

)

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)

Cost-efficient programmable architecture for high-volume
applications

Cost-optimized process

Low cost solution for high-performance communications
applications

System-level features

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

Low power consumption

Bidirectional I/O performance (setup time [

] and clock-to-

output delay [

]) up to 250 MHz

Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG)

PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 MHz or 66 MHz

Table 1. ACEX

1K Device Features

Feature

EP1K10

EP1K30

EP1K50

EP1K100

Typical gates

10,000

30,000

50,000

100,000

Maximum system gates

56,000

119,000

199,000

257,000

Logic elements (LEs)

576

1,728

2,880

4,992

EABs

Total RAM bits

12,288

24,576

40,960

49,152

Maximum user I/O pins

136

171

249

333

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

...and More
Features

-1 speed grade devices are compliant with

PCI Local Bus

Specification, Revision 2.2

for 5.0-V operation

Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.

Operate with a 2.5-V internal supply voltage

In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port

ClockLock

and ClockBoost

options for reduced clock delay,

clock skew, and clock multiplication

Built-in, low-skew clock distribution trees

100

functional testing of all devices; test vectors or scan chains

are not required

Pull-up on I/O pins before and during configuration

Flexible interconnect

FastTrack

Interconnect continuous routing structure for fast,

predictable interconnect delays

Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)

Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)

Tri-state emulation that implements internal tri-state buses

Up to six global clock signals and four global clear signals

Powerful I/O pins

Individual tri-state output enable control for each pin

Open-drain option on each I/O pin

Programmable output slew-rate control to reduce switching
noise

Clamp to V

CCIO

user-selectable on a pin-by-pin basis

Supports hot-socketing

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations

Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGA

packages (see

Tables 2

and

)

Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic

Notes:

(1)

ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.

(2)

Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.

(3)

This option is supported with a 256-pin FineLine BGA package. By using SameFrame

pin migration, all FineLine

BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine
BGA packages.

Table 2. ACEX 1K Package Options & I/O Pin Count

Notes (1)

(2)

Device

100-Pin TQFP

144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

484-Pin

FineLine BGA

EP1K10

120

136

(3)

EP1K30

102

147

171

(3)

EP1K50

102

147

186

249

EP1K100

147

186

333

Table 3. ACEX 1K Package Sizes

Device

100-Pin TQFP

144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

484-Pin

FineLine BGA

Pitch (mm)

0.50

1.0

Area (mm

)

256

484

936

289

529

Length

width

(mm

mm)

30.6

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

General
Description

Altera

ACEX 1K devices provide a die-efficient, low-cost architecture by

combining look-up table (LUT) architecture with EABs. LUT-based logic
provides optimized performance and efficiency for data-path, register
intensive, mathematical, or digital signal processing (DSP) designs, while
EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO)
functions. These elements make ACEX 1K suitable for complex logic
functions and memory functions such as digital signal processing, wide
data-path manipulation, data transformation and microcontrollers, as
required in high-performance communications applications. Based on
reconfigurable CMOS SRAM elements, the ACEX 1K architecture
incorporates all features necessary to implement common gate array
megafunctions, along with a high pin count to enable an effective interface
with system components. The advanced process and the low voltage
requirement of the 2.5-V core allow ACEX 1K devices to meet the
requirements of low-cost, high-volume applications ranging from DSL
modems to low-cost switches.

The ability to reconfigure ACEX 1K devices enables complete testing prior
to shipment and allows the designer to focus on simulation and design
verification. ACEX 1K device reconfigurability eliminates inventory
management for gate array designs and test vector generation for fault
coverage.

Table 4

shows ACEX 1K device performance for some common designs.

All performance results were obtained with Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.

Notes:

(1)

This application uses combinatorial inputs and outputs.

(2)

This application uses registered inputs and outputs.

Table 4. ACEX 1K Device Performance

Application

Resources

Used

Performance

LEs

EABs

Speed Grade

Units

-1

-2

-3

16-bit loadable counter

285

232

185

MHz

16-bit accumulator

285

232

185

MHz

16-to-1 multiplexer

(1)

3.5

4.5

6.6

16-bit multiplier with 3-stage pipeline

(2)

592

156

131

MHz

256

16 RAM read cycle speed

(2)

278

196

143

MHz

256

16 RAM write cycle speed

(2)

185

143

111

MHz

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Table 5

shows ACEX 1K device performance for more complex designs.

These designs are available as Altera MegaCore

functions.

Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.

ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlaster

, ByteBlasterMV

, or BitBlaster

download cables.

After an ACEX 1K device has been configured, it can be reconfigured in-
circuit by resetting the device and loading new data. Because
reconfiguration requires less than 40 ms, real-time changes can be made
during system operation.

ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it

by writing to a virtual

memory location, simplifying device reconfiguration.

Table 5. ACEX 1K Device Performance for Complex Designs

Application

LEs

Used

Performance

Speed Grade

Units

-1

-2

-3

16-bit, 8-tap parallel finite impulse response (FIR)
filter

597

192

156

116

MSPS

8-bit, 512-point Fast Fourier transform (FFT)
function

1,854

23.4

28.7

38.9

113

MHz

a16450

universal asynchronous

receiver/transmitter (UART)

342

20.5

MHz

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

For more information on the configuration of ACEX 1K devices, see the
following documents:

Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data
Sheet

MasterBlaster Serial/USB Communications Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

BitBlaster Serial Download Cable Data Sheet

ACEX 1K devices are supported by Altera development systems, which
are integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools.

The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains, which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development system includes DesignWare
functions that are optimized for the ACEX 1K device architecture.

The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.

For more information, see the

MAX+PLUS II Programmable Logic

Development System & Software Data Sheet

and the

Quartus Programmable

Logic Development System & Software Data Sheet

Functional
Description

Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.

The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input LUT, a
programmable flipflop, and dedicated signal paths for carry and cascade
functions. The eight LEs can be used to create medium-sized blocks of
logic--such as 8-bit counters, address decoders, or state machines--or
combined across LABs to create larger logic blocks. Each LAB represents
about 96 usable logic gates.

Signal interconnections within ACEX 1K devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 1.1 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1

shows a block diagram of the ACEX 1K device architecture. Each

group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 1. ACEX 1K Device Block Diagram

ACEX 1K devices provide six dedicated inputs that drive the flipflops'
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.

I/O Element
(IOE)

Logic Array
Block (LAB)

Row
Interconnect

IOE

Local Interconnect

IOE

Logic Element (LE)

Column
Interconnect

IOE

EAB

Logic
Array

IOE

Embedded Array Block (EAB)

Embedded Array

IOE

Logic Array

IOE

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Embedded Array Block

The EAB is a flexible block of RAM, with registers on the input and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.

Logic functions are implemented by programming the EAB with a read-
only pattern during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performance advantage that is further enhanced by the fast access
times of EABs. The large capacity of EABs enables designers to implement
complex functions in a single logic level without the routing delays
associated with linked LEs or field-programmable gate array (FPGA)
RAM blocks. For example, a single EAB can implement any function with
8 inputs and 16 outputs. Parameterized functions, such as LPM functions,
can take advantage of the EAB automatically.

The ACEX 1K enhanced EAB supports dual-port RAM. The dual-port
structure is ideal for FIFO buffers with one or two clocks. The ACEX 1K
EAB can also support up to 16-bit-wide RAM blocks. The ACEX 1K EAB
can act in dual-port or single-port mode. When in dual-port mode,
separate clocks may be used for EAB read and write sections, allowing the
EAB to be written and read at different rates. It also has separate
synchronous clock enable signals for the EAB read and write sections,
which allow independent control of these sections.

The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous reads or writes.

Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see

Figure 2

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 2. ACEX 1K Device in Dual-Port RAM Mode

Note (1)

Notes:

(1)

All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.

(2)

EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.

The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in

Figure 3

. The

ACEX 1K EAB can also be used in a single-port mode (see

Figure 4

Column Interconnect

EAB Local
Interconnect (2)

Dedicated Clocks

ENA

data[ ]

rdaddress[ ]

wraddress[ ]

RAM/ROM

256

× 16

512

× 8

1,024

× 4

2,048

× 2

Data In

Read Address

Write Address

Read Enable

Write Enable

Data Out

4, 8, 16, 32

outclocken

inclocken

inclock

outclock

ENA

Write

Pulse

Generator

rden

wren

Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.

Row Interconnect

4, 8

Dedicated Inputs &
Global Signals

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ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 3. ACEX 1K EAB in Dual-Port RAM Mode

Figure 4. ACEX 1K Device in Single-Port RAM Mode

Note:

(1)

EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.

Port A

Port B

address_a[]

address_b[]

data_a[]

data_b[]

we_a

we_b

clkena_a

clkena_b

Clock A

Clock B

Column Interconnect

EAB Local
Interconnect (1)

Dedicated Inputs
& Global Signals

RAM/ROM

256

× 16

512

× 8

1,024

× 4

2,048

× 2

Data In

Address

Write Enable

Data Out

4, 8, 16, 32

8, 4, 2, 1

8, 9, 10, 11

Row Interconnect

Dedicated
Clocks

4, 8

Chip-Wide
Reset

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB's synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB's self-timed RAM must only meet the setup
and hold time specifications of the global clock.

When used as RAM, each EAB can be configured in any of the following
sizes: 256

16; 512

8; 1,024

4; or 2,048

Figure 5

shows the ACEX 1K

EAB memory configurations.

Figure 5. ACEX 1K EAB Memory Configurations

Larger blocks of RAM are created by combining multiple EABs. For
example, two 256

16 RAM blocks can be combined to form a 256

block, and two 512

8 RAM blocks can be combined to form a

512

16 block.

Figure 6

shows examples of multiple EAB combination.

Figure 6. Examples of Combining ACEX 1K EABs

256

× 16

512

× 8

1,024

× 4

2,048

× 2

512

× 8

512

× 8

256

× 16

256

× 16

256

× 32

512

× 16

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera software automatically combines EABs
to meet a designer's RAM specifications.

EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.

An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see

Figures 2

and

). The column interconnect, which is adjacent

to the EAB, has twice as many channels as other columns in the device.

Logic Array Block

An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.

Figure 7

shows the ACEX 1K LAB.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 7. ACEX 1K LAB

Notes:

(1)

EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row; EP1K100
devices have 26.

(2)

EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels; EP1K100 devices have 34.

Carry-In &
Cascade-In

LE1

LE8

LE2

LE3

LE4

LE5

LE6

LE7

Column
Interconnect

Row Interconnect

(1)

LAB Local
Interconnect (2)

Column-to-Row
Interconnect

Carry-Out &
Cascade-Out

LAB Control
Signals

See Figure 13
for details.

Dedicated Inputs &

Global Signals

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ACEX 1K Programmable Logic Device Family Data Sheet

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Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as
clocks, the other two can be used for clear/preset control. The LAB clocks
can be driven by the dedicated clock input pins, global signals, I/O
signals, or internal signals via the LAB local interconnect. The LAB preset
and clear control signals can be driven by the global signals, I/O signals,
or internal signals via the LAB local interconnect. The global control
signals are typically used for global clock, clear, or preset signals because
they provide asynchronous control with very low skew across the device.
If logic is required on a control signal, it can be generated in one or more
LEs in any LAB and driven into the local interconnect of the target LAB.
In addition, the global control signals can be generated from LE outputs.

Logic Element

The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure.

Figure 8

shows the ACEX 1K LE.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 8. ACEX 1K Logic Element

The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT's
output drives the LE's output.

The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.

The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
speed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.

To LAB Local
Interconnect

Carry-In

Clock

Select

Carry-Out

Look-Up

Table

(LUT)

Clear/

Preset

Logic

Carry

Chain

Cascade

Chain

Cascade-In

Cascade-Out

To FastTrack
Interconnect

Programmable
Register

PRN

CLRN

ENA

data1
data2
data3
data4

labctrl1
labctrl2

labctrl4

labctrl3

Chip-Wide

Reset

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ACEX 1K Programmable Logic Device Family Data Sheet

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Carry Chain

The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
ACEX 1K architecture to efficiently implement high-speed counters,
adders, and comparators of arbitrary width. Carry chain logic can be
created automatically by the compiler during design processing, or
manually by the designer during design entry. Parameterized functions,
such as LPM and DesignWare functions, automatically take advantage of
carry chains.

Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from odd-
numbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EP1K50 device, the carry chain stops at the eighteenth LAB, and a
new carry chain begins at the nineteenth LAB.

Figure 9

shows how an n-bit full adder can be implemented in n + 1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.

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ACEX 1K Programmable Logic Device Family Data Sheet

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Cascade Chain

With the cascade chain, the ACEX 1K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan's inversion) to connect the outputs of
adjacent LEs. With a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the compiler during design
processing, or manually by the designer during design entry.

Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EP1K50 device, the cascade
chain stops at the eighteenth LAB, and a new one begins at the nineteenth
LAB). This break is due to the EAB's placement in the middle of the row.

Figure 10

shows how the cascade function can connect adjacent LEs to

form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is 1.3 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, decoding a 16-bit address
requires 3.1 ns.

Figure 10. ACEX 1K Cascade Chain Operation

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

n 1)..(4n 4)]

d[3..0]

d[7..4]

LE1

LE2

LUT

AND Cascade Chain

OR Cascade Chain

d[(4

n 1)..(4n 4)]

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

LE Operating Modes

The ACEX 1K LE can operate in the following four modes:

Normal mode

Arithmetic mode

Up/down counter mode

Clearable counter mode

Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE--the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE--are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.

The architecture provides a synchronous clock enable to the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.

Figure 11

shows the ACEX 1K LE operating modes.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 11. ACEX 1K LE Operating Modes

ENA

PRN

CLRN

4-Input

LUT

Carry-In

Cascade-Out

Cascade-In

LE-Out to FastTrack
Interconnect

LE-Out to Local
Interconnect

ENA

Normal Mode

PRN

CLRN

Cascade-Out

LE-Out

Cascade-In

3-Input

LUT

Carry-In

3-Input

LUT

Carry-Out

Arithmetic Mode

Up/Down Counter Mode

PRN

CLRN

3-Input

LUT

Carry-In

Cascade-In

LE-Out

3-Input

LUT

Carry-Out

Cascade-Out

Clearable Counter Mode

PRN

CLRN

3-Input

LUT

Carry-In

LE-Out

3-Input

LUT

Carry-Out

Cascade-Out

ENA

data1

data4

data3

data2

data1

data2

data1 (ena)

data2 (u/d)

data4 (nload)

data3 (data)

data1 (ena)

data2 (nclr)

data4 (nload)

data3 (data)

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Normal Mode

The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The compiler automatically selects the carry-
in or the DATA3 signal as one of the inputs to the LUT. The LUT output can
be combined with the cascade-in signal to form a cascade chain through
the cascade-out signal. Either the register or the LUT can be used to drive
both the local interconnect and the FastTrack Interconnect routing
structure at the same time.

The LUT and the register in the LE can be used independently (register
packing). To support register packing, the LE has two outputs; one drives
the local interconnect, and the other drives the FastTrack Interconnect
routing structure. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.

Arithmetic Mode

The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a 3-input function; the other generates a carry output. As shown
in

Figure 11

the first LUT uses the carry-in signal and two data inputs

from the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three signals:
a

, b, and carry-in. The second LUT uses the same three signals to generate

a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports simultaneous use of the cascade chain.

Up/Down Counter Mode

The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Two 3-input LUTs are used; one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals without using the LUT resources.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Clearable Counter Mode

The clearable counter mode is similar to the up/down counter mode, but
it supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used; one generates the counter data, and
the other generates the fast carry bit. Synchronous loading is provided by
a 2-to-1 multiplexer. The output of this multiplexer is AND

ed with a

synchronous clear signal.

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers' output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register's clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1

implements an asynchronous load. The data to be loaded is

driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.

During compilation, the compiler automatically selects the best control
signal implementation. Because the clear and preset functions are active-
low, the Compiler automatically assigns a logic high to an unused clear or
preset.

The clear and preset logic is implemented in one of the following six
modes chosen during design entry:

Asynchronous clear

Asynchronous preset

Asynchronous clear and preset

Asynchronous load with clear

Asynchronous load with preset

Asynchronous load without clear or preset

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.

Figure 12

shows examples

of how to setup the preset and clear inputs for the desired functionality.

Figure 12. ACEX 1K LE Clear & Preset Modes

Asynchronous Clear

Asynchronous Preset

Asynchronous Preset & Clear

Asynchronous Load without Clear or Preset

labctrl1

(Asynchronous

Load)

PRN

CLRN

NOT

labctrl1

(Asynchronous

Load)

Asynchronous Load with Clear

labctrl2

(Clear)

PRN

CLRN

NOT

(Asynchronous

Load)

Asynchronous Load with Preset

NOT

PRN

CLRN

labctrl1 or

labctrl2

PRN

CLRN

VCC

Chip-Wide Reset

PRN

CLRN

PRN

CLRN

VCC

Chip-Wide

Reset

Chip-Wide Reset

data3

(Data)

labctrl1

labctrl2

(Preset)

data3

(Data)

data3

(Data)

labctrl1 or

labctrl2

labctrl1

labctrl2

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Asynchronous Clear

The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode,
the preset signal is tied to VCC to deactivate it.

Asynchronous Preset

An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
register's input and output. Inversion control is available for the inputs to
both LEs and IOEs. Therefore, if a register is preset by only one of the two
LABCTRL

signals, the DATA3 input is not needed and can be used for one of

the LE operating modes.

Asynchronous Preset & Clear

When implementing asynchronous clear and preset, LABCTRL1 controls
the preset, and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.

Asynchronous Load with Clear

When implementing an asynchronous load in conjunction with the clear,
LABCTRL1

implements the asynchronous load of DATA3 by controlling the

register preset and clear. LABCTRL2 implements the clear by controlling
the register clear; LABCTRL2 does not have to feed the preset circuits.

Asynchronous Load with Preset

When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register's output.

Asynchronous Load without Preset or Clear

When implementing an asynchronous load without preset or clear,
LABCTRL1

implements the asynchronous load of DATA3 by controlling the

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

FastTrack Interconnect Routing Structure

In the ACEX 1K architecture, connections between LEs, EABs, and device
I/O pins are provided by the FastTrack Interconnect routing structure,
which is a series of continuous horizontal and vertical routing channels
that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.

The FastTrack Interconnect routing structure consists of row and column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins and feed other LABs in the row. The column interconnect routes
signals between rows and can drive I/O pins.

Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channels. These four signals feed dual 4-to-1 multiplexers that connect to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnect.

Each column of LABs or EABs is served by a dedicated column
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can then drive I/O pins or another row's interconnect to route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.

Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resources to be used more efficiently.

Figure 13

shows the ACEX 1K LAB.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the row. The EAB can be driven by the half-length channels in the left half
of the row and by the full-length channels. The EAB drives out to the full-
length channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.

Table 6

summarizes the FastTrack Interconnect routing structure

resources available in each ACEX 1K device.

In addition to general-purpose I/O pins, ACEX 1K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output-enable and clock-enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.

Figure 14

shows the interconnection of adjacent LABs and EABs, with

row, column, and local interconnects, as well as the associated cascade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3.

Table 6. ACEX 1K FastTrack Interconnect Resources

Device

Rows

Channels per

Row

Columns

Channels per

Column

EP1K10

144

EP1K30

216

EP1K50

216

EP1K100

312

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 14. ACEX 1K Interconnect Resources

I/O Element

An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. The compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate. For bidirectional
registered I/O implementation, the output register should be in the IOE
and the data input and output enable registers should be LE registers
placed adjacent to the bidirectional pin.

Figure 15

shows the bidirectional

I/O registers.

I/O Element (IOE)

Row
Interconnect

IOE

Column
Interconnect

LAB

See Figure 17

for details.

See Figure 16

for details.

LAB

IOE

Cascade &

To LAB B4

To LAB A4

To LAB B5

To LAB A5

IOE

Carry Chains

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 15. ACEX 1K Bidirectional I/O Registers

VCC

OE[7..0]

CLK[1..0]

ENA[5..0]

CLRN[1..0]

Peripheral

Control Bus

CLRN

ENA

VCC

2 Dedicated

Clock Inputs

Slew-Rate

Control

Open-Drain

Output

Chip-Wide

Output Enable

CLK[3..2]

VCC

Chip-Wide

Reset

Programmable Delay

4 Dedicated

Inputs

Row and Column

Interconnect

VCC

CLRN

ENA

Chip-Wide

Reset

CLRN

ENA

Chip-Wide

Reset

VCC

Input Register

Output Register

OE Register

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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On all ACEX 1K devices, the input path from the I/O pad to the FastTrack
Interconnect has a programmable delay element that can be used to
guarantee a zero hold time. Depending on the placement of the IOE
relative to what it is driving, the designer may choose to turn on the
programmable delay to ensure a zero hold time or turn it off to minimize
setup time. This feature is used to reduce setup time for complex pin-to-
register paths (e.g., PCI designs).

Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices and provides up to 12 peripheral control signals that
can be allocated as follows:

Up to eight output enable signals

Up to six clock enable signals

Up to two clock signals

Up to two clear signals

If more than six clock-enable or eight output-enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chip-
wide reset signal resets all IOE registers, overriding any other control
signals.

When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock, and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on an LAB-by-LAB basis.

The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.

When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.

Table 7

lists the sources for each peripheral control signal and shows how

the output enable, clock enable, clock, and clear signals share
12 peripheral control signals.

Table 7

also shows the rows that can drive

global signals.

Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.

The chip-wide output enable pin is an active-low pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.

Table 7. Peripheral Bus Sources for ACEX Devices

Peripheral Control Signal

EP1K10

EP1K30

EP1K50

EP1K100

OE0

Row A

OE1

Row A

Row B

Row C

OE2

Row B

Row C

Row D

Row E

OE3

Row B

Row D

Row F

Row L

OE4

Row C

Row E

Row H

Row I

OE5

Row C

Row F

Row J

Row K

CLKENA0

/CLK0/GLOBAL0

Row A

Row F

CLKENA1

/OE6/GLOBAL1

Row A

Row B

Row C

Row D

CLKENA2

/CLR0

Row B

Row C

Row E

Row B

CLKENA3

/OE7/GLOBAL2

Row B

Row D

Row G

Row H

CLKENA4

/CLR1

Row C

Row E

Row I

Row J

CLKENA5

/CLK1/GLOBAL3

Row C

Row F

Row J

Row G

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ACEX 1K Programmable Logic Device Family Data Sheet

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Row-to-IOE Connections

When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see

Figure 16

Figure 16. ACEX 1K Row-to-IOE Connections

Note (1)

Note:
(1)

The values for m and n are shown in

Table 8

lists the ACEX 1K row-to-IOE interconnect resources.

Each IOE is driven by an

m-to-1 multiplexer.

Each IOE can drive two
row channels.

IOE8

IOE1

Row FastTrack

Interconnect

Table 8. ACEX 1K Row-to-IOE Interconnect Resources

Device

Channels per Row (n)

Row Channels per Pin (m)

EP1K10

144

EP1K30

216

EP1K50

216

EP1K100

312

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Column-to-IOE Connections

When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column channels via a multiplexer. The set of column channels is different
for each IOE (see

Figure 17

Figure 17. ACEX 1K Column-to-IOE Connections

Note (1)

Note:
(1)

The values for m and n are shown in

Table 9

lists the ACEX 1K column-to-IOE interconnect resources.

Table 9. ACEX 1K Column-to-IOE Interconnect Resources

Device

Channels per Column (n)

Column Channels per Pin (m)

EP1K10

EP1K30

EP1K50

EP1K100

Each IOE is driven by
a m-to-1 multiplexer

Each IOE can drive two
column channels.

Column
Interconnect

IOE1

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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SameFrame
Pin-Outs

ACEX 1K devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EP1K10 device in a 256-pin
FineLine BGA package to an EP1K100 device in a 484-pin FineLine BGA
package.

The Altera software provides support to design PCBs with SameFrame
pin-out devices. Devices can be defined for present and future use. The
Altera software generates pin-outs describing how to lay out a board that
takes advantage of this migration.

Figure 18

shows an example of

SameFrame pin-out.

Figure 18. SameFrame Pin-Out Example

Table 10

shows the ACEX 1K device/package combinations that support

SameFrame pin-outs for ACEX 1K devices. All FineLine BGA packages
support SameFrame pin-outs, providing the flexibility to migrate not only
from device to device within the same package, but also from one package
to another. The I/O count will vary from device to device.

Designed for 484-Pin FineLine BGA Package

Printed Circuit Board

256-Pin FineLine BGA Package

(Reduced I/O Count or

Logic Requirements)

484-Pin FineLine BGA Package

(Increased I/O Count or

Logic Requirements)

256-Pin

FineLine

BGA

484-Pin

FineLine

BGA

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

For more information, search for "SameFrame" in MAX+PLUS II Help.

Note:
(1)

This option is supported with a 256-pin FineLine BGA package and SameFrame
migration.

ClockLock &
ClockBoost
Features

To support high-speed designs, -1 and -2 speed grade ACEX 1K devices
offer ClockLock and ClockBoost circuitry containing a phase-locked loop
(PLL) that is used to increase design speed and reduce resource usage.
The ClockLock circuitry uses a synchronizing PLL that reduces the clock
delay and skew within a device. This reduction minimizes clock-to-
output and setup times while maintaining zero hold times. The
ClockBoost circuitry, which provides a clock multiplier, allows the
designer to enhance device area efficiency by sharing resources within the
device. The ClockBoost feature allows the designer to distribute a low-
speed clock and multiply that clock on-device. Combined, the ClockLock
and ClockBoost features provide significant improvements in system
performance and bandwidth.

The ClockLock and ClockBoost features in ACEX 1K devices are enabled
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the device pins.

The ClockLock and ClockBoost circuitry lock onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.

The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the
device.

Table 10. ACEX 1K SameFrame Pin-Out Support

Device

256-Pin

FineLine

BGA

484-Pin

FineLine

BGA

EP1K10

(1)

EP1K30

(1)

EP1K50

EP1K100

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ACEX 1K Programmable Logic Device Family Data Sheet

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For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.

ClockLock & ClockBoost Timing Parameters

For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.

Figure 19

shows the incoming and generated clock

specifications.

Figure 19. Specifications for the Incoming & Generated Clocks

Note (1)

Note:
(1)

The t

parameter refers to the nominal input clock period; the t

parameter refers to the nominal output clock

period.

Input
Clock

ClockLock
Generated
Clock

CLK1

INDUTY

CLKDEV

INCLKSTB

JITTER

OUTDUTY

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Tables 11

and

summarize the ClockLock and ClockBoost parameters

for -1 and -2 speed-grade devices, respectively.

Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input rise time

Input fall time

INDUTY

Input duty cycle

CLK1

Input clock frequency (ClockBoost clock
multiplication factor equals 1)

180

MHz

CLK2

Input clock frequency (ClockBoost clock
multiplication factor equals 2)

MHz

CLKDEV

Input deviation from user specification in the
Altera software

(1)

25,000

(2)

PPM

INCLKSTB

Input clock stability (measured between
adjacent clocks)

100

LOCK

Time required for ClockLock or ClockBoost
to acquire lock

(3)

JITTER

Jitter on ClockLock or ClockBoost-
generated clock

(4)

INCLKSTB

<100

250

(4)

INCLKSTB

< 50

200

(4)

OUTDUTY

Duty cycle for ClockLock or ClockBoost-
generated clock

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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Notes to tables:
(1)

To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
f

CLKDEV

parameter specifies how much the incoming clock can differ from the specified frequency during device

operation. Simulation does not reflect this parameter.

(2)

Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.

(3)

During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t

LOCK

value is less than the time required for configuration.

(4)

The t

JITTER

specification is measured under long-term observation. The maximum value for t

JITTER

is 200 ps if

INCLKSTB

is lower than 50 ps.

I/O
Configuration

This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/O interface is controlled by connecting
V

CCIO

to a different voltage than V

CCINT

. Its effect can be simulated in the

Altera software via the Global Project Device Options dialog box (Assign
menu).

Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Input rise time

Input fall time

INDUTY

Input duty cycle

CLK1

Input clock frequency (ClockBoost clock
multiplication factor equals 1)

MHz

CLK2

Input clock frequency (ClockBoost clock
multiplication factor equals 2)

MHz

CLKDEV

Input deviation from user specification in
the software

(1)

25,000

PPM

INCLKSTB

Input clock stability (measured between
adjacent clocks)

100

LOCK

Time required for ClockLock or ClockBoost
to acquire lock

(3)

JITTER

Jitter on ClockLock or ClockBoost-
generated clock

(4)

INCLKSTB

< 100

250

(4)

INCLKSTB

< 50

200

(4)

OUTDUTY

Duty cycle for ClockLock or ClockBoost-
generated clock

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

PCI Pull-Up Clamping Diode Option

ACEX 1K devices have a pull-up clamping diode on every I/O, dedicated
input, and dedicated clock pin. PCI clamping diodes clamp the signal to
the V

CCIO

value and are required for 3.3-V PCI compliance. Clamping

diodes can also be used to limit overshoot in other systems.

Clamping diodes are controlled on a pin-by-pin basis. When V

CCIO

3.3 V, a pin that has the clamping diode option turned on can be driven by
a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When V

CCIO

is 2.5 V, a pin

that has the clamping diode option turned on can be driven by a 2.5-V
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can
be activated for a subset of pins, which allows a device to bridge between
a 3.3-V PCI bus and a 5.0-V device.

Slew-Rate Control

The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast
slew rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew rate
pin-by-pin or assign a default slew rate to all pins on a device-wide basis.
The slow slew rate setting affects only the falling edge of the output.

Open-Drain Output Option

ACEX 1K devices provide an optional open-drain output (electrically
equivalent to open-collector output) for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.

MultiVolt I/O Interface

The ACEX 1K device architecture supports the MultiVolt I/O interface
feature, which allows ACEX 1K devices in all packages to interface with
systems of differing supply voltages. These devices have one set of V

pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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The VCCINT pins must always be connected to a 2.5-V power supply. With
a 2.5-V V

CCINT

level, input voltages are compatible with 2.5-V, 3.3-V, and

5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or 3.3-V
power supply, depending on the output requirements. When the VCCIO
pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with V

CCIO

levels higher

than 3.0 V achieve a faster timing delay of t

OD2

instead of t

OD1

Table 13

summarizes ACEX 1K MultiVolt I/O support.

Notes:
(1)

The PCI clamping diode must be disabled on an input which is driven with a
voltage higher than V

CCIO

(2)

When V

CCIO

= 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V

tolerant inputs.

Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a higher
V

than LVTTL. When the open-drain pin is active, it will drive low.

When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby
meeting the CMOS V

requirement. The open-drain pin will only drive

low or tri-state; it will never drive high. The rise time is dependent on the
value of the pull-up resistor and load impedance. The I

current

specification should be considered when selecting a pull-up resistor.

Power
Sequencing &
Hot-Socketing

Because ACEX 1K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The V

CCIO

and V

CCINT

power planes can be powered in any

order.

Signals can be driven into ACEX 1K devices before and during power up
without damaging the device. Additionally, ACEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.

Table 13. ACEX 1K MultiVolt I/O Support

CCIO

(V)

Input Signal (V)

Output Signal (V)

2.5

3.3

5.0

2.5

3.3

5.0

2.5

(1)

3.3

(1)

(2)

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support

All ACEX 1K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be
configured using the JTAG pins through the ByteBlasterMV or BitBlaster
download cable, or via hardware that uses the Jam

Standard Test and

Programming Language (STAPL), JEDEC standard JESD-71. JTAG
boundary-scan testing can be performed before or after configuration, but
not during configuration. ACEX 1K devices support the JTAG
instructions shown in

Table 14

The instruction register length of ACEX 1K devices is 10 bits. The
USERCODE register length in ACEX 1K devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined.

Tables 15

and

show the boundary-scan register length and device IDCODE information
for ACEX 1K devices.

Table 14. ACEX 1K JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD

Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation and permits an initial data pattern to be output at the device
pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDI and TDO pins, allowing the BST data
to pass synchronously through a selected device to adjacent devices during normal
operation.

USERCODE

Selects the user electronic signature (USERCODE) register and places it between the

TDI

and TDO pins, allowing the USERCODE to be serially shifted out of TDO.

IDCODE

Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.

ICR Instructions

These instructions are used when configuring an ACEX 1K device via JTAG ports using
a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.

Table 15. ACEX 1K Boundary-Scan Register Length

Device

Boundary-Scan Register Length

EP1K10

438

EP1K30

690

EP1K50

798

EP1K100

1,050

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Notes to tables:
(1)

The most significant bit (MSB) is on the left.

(2)

The least significant bit (LSB) for all JTAG IDCODEs is 1.

ACEX 1K devices include weak pull-up resistors on the JTAG pins.

For more information, see the following documents:

Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)

ByteBlasterMV Parallel Port Download Cable Data Sheet

BitBlaster Serial Download Cable Data Sheet

Jam Programming & Test Language Specification

Figure 20

shows the timing requirements for the JTAG signals.

Table 16. 32-Bit IDCODE for ACEX 1K Devices

Note (1)

Device

IDCODE (32 Bits)

Version

(4 Bits)

Part Number (16 Bits)

Manufacturer's

Identity (11 Bits)

1 (1 Bit)

(2)

EP1K10

0001

0001 0000 0001 0000

00001101110

EP1K30

0001

0001 0000 0011 0000

00001101110

EP1K50

0001

0001 0000 0101 0000

00001101110

EP1K100

0010

0000 0001 0000 0000

00001101110

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 20. ACEX 1K JTAG Waveforms

Table 17

shows the timing parameters and values for ACEX 1K devices.

TDO

TCK

JPZX

JPCO

JPH

JPXZ

JCP

JPSU

JCL

JCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

JSZX

JSSU

JSH

JSCO

JSXZ

Table 17. ACEX 1K JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

JCP

TCK

clock period

100

JCH

TCK

clock high time

JCL

TCK

clock low time

JPSU

JTAG port setup time

JPH

JTAG port hold time

JPCO

JTAG port clock to output

JPZX

JTAG port high impedance to valid output

JPXZ

JTAG port valid output to high impedance

JSSU

Capture register setup time

JSH

Capture register hold time

JSCO

Update register clock to output

JSZX

Update register high impedance to valid output

JSXZ

Update register valid output to high impedance

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Generic Testing

Each ACEX 1K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for ACEX 1K
devices are made under conditions equivalent to those shown in

Figure 21

. Multiple test patterns can be used to configure devices during

all stages of the production flow.

Figure 21. ACEX 1K AC Test Conditions

Operating
Conditions

Tables 18

through

provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V ACEX 1K devices.

To Test
System

C1 (includes
JIG capacitance)

Device input
rise and fall
times < 3 ns

Device
Output

703

8.06 k

[481 ]

VCCIO

Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V devices
or outputs. Numbers without brackets are
for 3.3-V devices or outputs.

Table 18. ACEX 1K Device Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

CCINT

Supply voltage

With respect to ground

(2)

0.5

3.6

CCIO

0.5

4.6

DC input voltage

2.0

5.75

OUT

DC output current, per pin

STG

Storage temperature

No bias

150

AMB

Ambient temperature

Under bias

135

Junction temperature

PQFP, TQFP, and BGA packages, under
bias

135

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 19. ACEX 1K Device Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

CCINT

Supply voltage for internal logic
and input buffers

(3)

(4)

2.375

(2.375)

2.625

(2.625)

CCIO

Supply voltage for output buffers,
3.3-V operation

(3)

(4)

3.00 (3.00)

3.60 (3.60)

Supply voltage for output buffers,
2.5-V operation

(3)

(4)

2.375

(2.375)

2.625

(2.625)

Input voltage

(2)

(5)

0.5

5.75

Output voltage

CCIO

Ambient temperature

For commercial use

For industrial use

Operating temperature

For commercial use

For industrial use

100

Input rise time

Input fall time

Table 20. ACEX 1K Device DC Operating Conditions (Part 1 of 2)

Notes (6)

(7)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High-level input voltage

1.7,

0.5

× V

CCIO

(8)

5.75

Low-level input voltage

0.5

0.8,

0.3

× V

CCIO

(8)

3.3-V high-level TTL output
voltage

= 8 mA DC,

CCIO

= 3.00 V

(9)

2.4

3.3-V high-level CMOS output
voltage

= 0.1 mA DC,

CCIO

= 3.00 V

(9)

CCIO

0.2

3.3-V high-level PCI output
voltage

= 0.5 mA DC,

CCIO

= 3.00 to 3.60 V

(9)

0.9

×V

CCIO

2.5-V high-level output voltage I

= 0.1 mA DC,

CCIO

= 2.375 V

(9)

2.1

= 1 mA DC,

CCIO

= 2.375 V

(9)

2.0

= 2 mA DC,

CCIO

= 2.375 V

(9)

1.7

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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3.3-V low-level TTL output
voltage

= 12 mA DC,

CCIO

= 3.00 V

(10)

0.45

3.3-V low-level CMOS output
voltage

= 0.1 mA DC,

CCIO

= 3.00 V

(10)

0.2

3.3-V low-level PCI output
voltage

= 1.5 mA DC,

CCIO

= 3.00 to 3.60 V

(10)

0.1

× V

CCIO

2.5-V low-level output voltage I

= 0.1 mA DC,

CCIO

= 2.375 V

(10)

0.2

= 1 mA DC,

CCIO

= 2.375 V

(10)

0.4

= 2 mA DC,

CCIO

= 2.375 V

(10)

0.7

Input pin leakage current

= 5.3 to 0.3 V

(11)

Tri-stated I/O pin leakage
current

= 5.3 to 0.3 V

(11)

CC0

supply current (standby)

= ground, no load,

no toggling inputs

= ground, no load,

no toggling inputs

(12)

CONF

Value of I/O pin pull-up
resistor before and during
configuration

CCIO

= 3.0 V

(13)

CCIO

= 2.375 V

(13)

Table 20. ACEX 1K Device DC Operating Conditions (Part 2 of 2)

Notes (6)

(7)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Notes to tables:
(1)

See the

Operating Requirements for Altera Devices Data Sheet

(2)

Minimum DC input voltage is 0.5 V. During transitions, the inputs may undershoot to 2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.

(3)

Numbers in parentheses are for industrial-temperature-range devices.

(4)

Maximum V

rise time is 100 ms, and V

must rise monotonically.

(5)

All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V

CCINT

and V

CCIO

are

powered.

(6)

Typical values are for T

= 25

° C, V

CCINT

= 2.5 V, and V

CCIO

= 2.5 V or 3.3 V.

(7)

These values are specified under the ACEX 1K Recommended Operating Conditions shown in Table 19 on page 46.

(8)

The ACEX 1K input buffers are compatible with 2.5-V, 3.3-V (LVTTL and LVCMOS), and 5.0-V TTL and CMOS
signals. Additionally, the input buffers are 3.3-V PCI compliant when V

CCIO

and V

CCINT

meet the relationship

shown in

Figure 22

(9)

The I

parameter refers to high-level TTL, PCI, or CMOS output current.

(10) The I

parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins

as well as output pins.

(11) This value is specified for normal device operation. The value may vary during power-up.
(12) This parameter applies to -1 speed grade commercial temperature devices and -2 speed grade industrial

temperature devices.

(13) Pin pull-up resistance values will be lower if the pin is driven higher than V

CCIO

by an external source.

(14) Capacitance is sample-tested only.

Table 21. ACEX 1K Device Capacitance

Note (14)

Symbol

Parameter

Conditions

Min

Max

Unit

Input capacitance

= 0 V, f = 1.0 MHz

INCLK

Input capacitance on
dedicated clock pin

= 0 V, f = 1.0 MHz

OUT

Output capacitance

OUT

= 0 V, f = 1.0 MHz

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 22

shows the required relationship between V

CCIO

and V

CCINT

satisfy 3.3-V PCI compliance.

Figure 22. Relationship between V

CCIO

& V

CCINT

for 3.3-V PCI Compliance

Figure 23

shows the typical output drive characteristics of ACEX 1K

devices with 3.3-V and 2.5-V V

CCIO

. The output driver is compliant to the

3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIO

pins are

connected to 3.3 V). ACEX 1K devices with a -1 speed grade also comply
with the drive strength requirements of the PCI Local Bus Specification,
Revision 2.2

(when VCCINT pins are powered with a minimum supply of

2.375 V, and VCCIO

pins are connected to 3.3 V). Therefore, these devices

can be used in open 5.0-V PCI systems.

3.0

3.1

3.3

CCIO

3.6

2.3

2.5

2.7

CCINT

(V)

(V)

PCI-Compliant Region

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 23. Output Drive Characteristics of ACEX 1K Devices

Timing Model

The continuous, high-performance FastTrack Interconnect routing
resources ensure accurate simulation and timing analysis as well as
predictable performance. This predictable performance contrasts with
that of FPGAs, which use a segmented connection scheme and, therefore,
have an unpredictable performance.

Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:

LE register clock-to-output delay (t

)

Interconnect delay (t

SAMEROW

)

LE look-up table delay (t

LUT

)

LE register setup time (t

)

The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.

Timing simulation and delay prediction are available with the simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.

Output Voltage (V)

CCINT

= 2.5

CCIO

= 2.5

Room Temperature

CCINT

= 2.5

CCIO

= 3.3

Room Temperature

Output Voltage (V)

Typical I
Output
Current (mA)

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 24

shows the overall timing model, which maps the possible paths

to and from the various elements of the ACEX 1K device.

Figure 24. ACEX 1K Device Timing Model

Figures 25

through

show the delays that correspond to various paths

and functions within the LE, IOE, EAB, and bidirectional timing models.

Figure 25. ACEX 1K Device LE Timing Model

Dedicated

Clock/Input

Interconnect

I/O Element

Logic

Element

Embedded Array

Block

CGENR

COMB

PRE

CLR

Delays

LUT Delay

LUT

RLUT

CLUT

Carry Chain

Delay

Carry-In

Cascade-In

Data-Out

CGEN

CICO

Packed Register

Delay

PACKED

Delay

Data-In

Control-In

CASC

Cascade-Out

Carry-Out

LABCARRY

LABCASC

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 26. ACEX 1K Device IOE Timing Model

Figure 27. ACEX 1K Device EAB Timing Model

Data-In

I/O Register

Delays

IOCO

IOCOMB

IOSU

IOH

IOCLR

Output Data

Delay

IOD

I/O Element

Contol Delay

IOC

Input Register Delay

INREG

Output
Delays

OD1

OD2

OD3

ZX1

ZX2

ZX3

I/O Register

Feedback Delay

IOFD

Input Delay

INCOMB

Clock Enable

Clear

Data Feedback
into FastTrack
Interconnect

Clock

Output Enable

EAB Data Input

Delays

EABDATA1

EABDATA2

Data-In

Write Enable

Input Delays

EABWE1

EABWE2

EAB Clock

Delay

EABCLK

Input Register

Delays

EABCO

EABBYPASS

EABSU

EABH

EABCH

EABCL

EABRE1

EABRE2

RAM/ROM

Block Delays

RASU

RAH

WDSU

WDH

WASU

WAH

Output Register

Delays

EABCO

EABBYPASS

EABSU

EABH

EABCH

EABCL

EABOUT

Address

Input Register

Clock

Output Register

Clock

Data-Out

EAB Output

Delay

Read Enable

Input Delays

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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Figure 28. Synchronous Bidirectional Pin External Timing Model

Tables 29

and

show the asynchronous and synchronous timing

waveforms, respectively, for the EAB macroparameters in

Table 24

Figure 29. EAB Asynchronous Timing Waveforms

PRN

CLRN

PRN

CLRN

PRN

CLRN

Dedicated
Clock

Bidirectional
Pin

Output Register

INSUBIDIR

OUTCOBIDIR

XZBIDIR

ZXBIDIR

INHBIDIR

OE Register

Input Register

EAB Asynchronous Write

EAB Asynchronous Read

EABRCCOMB

EABAA

Address

Data-Out

din1

dout2

EABDD

din1

din0

EABWCCOMB

EABWASU

EABWAH

EABWDH

EABWDSU

EABWP

din0

Data-In

Address

Data-Out

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 30. EAB Synchronous Timing Waveforms

Tables 22

through

describe the ACEX 1K device internal timing

parameters.

CLK

EAB Synchronous Read

EABDATASU

EABRCREG

EABDATACO

EABDATAH

CLK

dout0

din1

din2

din3

din2

EABWESU

EABWCREG

EABWEH

EABDATACO

din3

din2

din1

EABDATAH

EABDATASU

EAB Synchronous Write (EAB Output Registers Used)

dout1

Address

Data-Out

Address

Data-Out

Data-In

Table 22. LE Timing Microparameters (Part 1 of 2)

Note (1)

Symbol

Parameter

Conditions

LUT

LUT delay for data-in

CLUT

LUT delay for carry-in

RLUT

LUT delay for LE register feedback

PACKED

Data-in to packed register delay

LE register enable delay

CICO

Carry-in to carry-out delay

CGEN

Data-in to carry-out delay

CGENR

LE register feedback to carry-out delay

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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CASC

Cascade-in to cascade-out delay

LE register control signal delay

LE register clock-to-output delay

COMB

Combinatorial delay

LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load

LE register hold time for data and enable signals after clock

PRE

LE register preset delay

CLR

LE register clear delay

Minimum clock high time from clock pin

Minimum clock low time from clock pin

Table 23. IOE Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

IOD

IOE data delay

IOC

IOE register control signal delay

IOCO

IOE register clock-to-output delay

IOCOMB

IOE combinatorial delay

IOSU

IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear

IOH

IOE register hold time for data and enable signals after clock

IOCLR

IOE register clear time

OD1

Output buffer and pad delay, slow slew rate = off, V

CCIO

= 3.3 V

C1 = 35 pF

(2)

OD2

Output buffer and pad delay, slow slew rate = off, V

CCIO

= 2.5 V

C1 = 35 pF

(3)

OD3

Output buffer and pad delay, slow slew rate = on

C1 = 35 pF

(4)

IOE output buffer disable delay

ZX1

IOE output buffer enable delay, slow slew rate = off, V

CCIO

= 3.3 V

C1 = 35 pF

(2)

ZX2

IOE output buffer enable delay, slow slew rate = off, V

CCIO

= 2.5 V

C1 = 35 pF

(3)

ZX3

IOE output buffer enable delay, slow slew rate = on

C1 = 35 pF

(4)

INREG

IOE input pad and buffer to IOE register delay

IOFD

IOE register feedback delay

INCOMB

IOE input pad and buffer to FastTrack Interconnect delay

Table 22. LE Timing Microparameters (Part 2 of 2)

Note (1)

Symbol

Parameter

Conditions

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 24. EAB Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

EABDATA1

Data or address delay to EAB for combinatorial input

EABDATA2

Data or address delay to EAB for registered input

EABWE1

Write enable delay to EAB for combinatorial input

EABWE2

Write enable delay to EAB for registered input

EABRE1

Read enable delay to EAB for combinatorial input

EABRE2

Read enable delay to EAB for registered input

EABCLK

EAB register clock delay

EABCO

EAB register clock-to-output delay

EABBYPASS

Bypass register delay

EABSU

EAB register setup time before clock

EABH

EAB register hold time after clock

EABCLR

EAB register asynchronous clear time to output delay

Address access delay (including the read enable to output delay)

Write pulse width

Read pulse width

WDSU

Data setup time before falling edge of write pulse

(5)

WDH

Data hold time after falling edge of write pulse

(5)

WASU

Address setup time before rising edge of write pulse

(5)

WAH

Address hold time after falling edge of write pulse

(5)

RASU

Address setup time before rising edge of read pulse

RAH

Address hold time after falling edge of read pulse

Write enable to data output valid delay

Data-in to data-out valid delay

EABOUT

Data-out delay

EABCH

Clock high time

EABCL

Clock low time

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Table 25. EAB Timing Macroparameters

Notes (1)

(6)

Symbol

Parameter

Conditions

EABAA

EAB address access delay

EABRCCOMB

EAB asynchronous read cycle time

EABRCREG

EAB synchronous read cycle time

EABWP

EAB write pulse width

EABWCCOMB

EAB asynchronous write cycle time

EABWCREG

EAB synchronous write cycle time

EABDD

EAB data-in to data-out valid delay

EABDATACO

EAB clock-to-output delay when using output registers

EABDATASU

EAB data/address setup time before clock when using input register

EABDATAH

EAB data/address hold time after clock when using input register

EABWESU

EAB WE setup time before clock when using input register

EABWEH

EAB WE hold time after clock when using input register

EABWDSU

EAB data setup time before falling edge of write pulse when not using input
registers

EABWDH

EAB data hold time after falling edge of write pulse when not using input
registers

EABWASU

EAB address setup time before rising edge of write pulse when not using
input registers

EABWAH

EAB address hold time after falling edge of write pulse when not using input
registers

EABWO

EAB write enable to data output valid delay

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Notes to tables:
(1)

Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.

(2)

Operating conditions: V

CCIO

= 3.3 V ± 10% for commercial or industrial use in ACEX 1K devices

(3)

Operating conditions: V

CCIO

= 2.5 V ± 5% for commercial or industrial use in ACEX 1K devices.

(4)

Operating conditions: V

CCIO

= 2.5 V or 3.3 V.

(5)

Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.

(6)

EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.

(7)

These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.

Table 26. Interconnect Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

DIN2IOE

Delay from dedicated input pin to IOE control input

(7)

DIN2LE

Delay from dedicated input pin to LE or EAB control input

(7)

DIN2DATA

Delay from dedicated input or clock to LE or EAB data

(7)

DCLK2IOE

Delay from dedicated clock pin to IOE clock

(7)

DCLK2LE

Delay from dedicated clock pin to LE or EAB clock

(7)

SAMELAB

Routing delay for an LE driving another LE in the same LAB

(7)

SAMEROW

Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row

(7)

SAMECOLUMN

Routing delay for an LE driving an IOE in the same column

(7)

DIFFROW

Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row

(7)

TWOROWS

Routing delay for a row IOE or EAB driving an LE or EAB in a different row

(7)

LEPERIPH

Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus

(7)

LABCARRY

Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB

LABCASC

Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Tables 27

through

describe the ACEX 1K external timing parameters

and their symbols.

Notes to tables:
(1)

External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.

(2)

Contact Altera Applications for test circuit specifications and test conditions.

(3)

These timing parameters are sample-tested only.

(4)

This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.

Table 27. External Reference Timing Parameters

Note (1)

Symbol

Parameter

Conditions

DRR

(2)

Table 28. External Timing Parameters

Symbol

Parameter

Conditions

INSU

Setup time with global clock at IOE register

(3)

INH

Hold time with global clock at IOE register

(3)

OUTCO

Clock-to-output delay with global clock at IOE register

(3)

PCISU

Setup time with global clock for registers used in PCI designs

(3)

(4)

PCIH

Hold time with global clock for registers used in PCI designs

(3)

(4)

PCICO

Clock-to-output delay with global clock for registers used in PCI designs

(3)

(4)

Table 29. External Bidirectional Timing Parameters

Note (3)

Symbol

Parameter

Conditions

INSUBIDIR

Setup time for bidirectional pins with global clock at same-row or same-
column LE register

INHBIDIR

Hold time for bidirectional pins with global clock at same-row or same-column
LE register

OUTCOBIDIR

Clock-to-output delay for bidirectional pins with global clock at IOE register

CI = 35 pF

XZBIDIR

Synchronous IOE output buffer disable delay

CI = 35 pF

ZXBIDIR

Synchronous IOE output buffer enable delay, slow slew rate = off

CI = 35 pF

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Tables 30

through

show EP1K10 device internal and external timing

parameters. All timing specifications for EP1K10 are preliminary.

Table 30. EP1K10 Device LE Timing Microparameters

Notes (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

LUT

0.7

0.8

1.1

CLUT

0.5

0.6

0.8

RLUT

0.6

0.7

1.0

PACKED

0.4

0.5

0.9

1.0

1.3

CICO

0.1

0.2

CGEN

0.4

0.5

0.7

CGENR

0.1

0.2

CASC

0.7

0.9

1.1

1.3

1.7

0.5

0.7

0.9

COMB

0.4

0.5

0.7

0.8

1.0

0.9

1.0

1.1

PRE

0.8

1.0

1.4

CLR

0.9

1.0

1.4

2.0

2.5

2.0

2.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Table 31. EP1K10 Device IOE Timing Microparameters

Note (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

IOD

2.6

3.1

4.0

IOC

0.3

0.4

0.5

IOCO

0.9

1.0

1.4

IOCOMB

0.0

IOSU

1.3

1.5

2.0

IOH

0.9

1.0

1.4

IOCLR

1.1

1.3

1.7

OD1

3.1

3.7

4.1

OD2

2.6

3.3

3.9

OD3

5.8

6.9

8.3

3.8

4.5

5.9

ZX1

3.8

4.5

5.9

ZX2

3.3

4.1

5.7

ZX3

6.5

7.7

10.1

INREG

3.7

4.3

5.7

IOFD

0.9

1.0

1.4

INCOMB

1.9

2.3

3.0

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 32. EP1K10 Device EAB Internal Microparameters

Note (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABDATA1

1.8

1.9

EABDATA2

0.6

0.7

EABWE1

1.2

EABWE2

0.4

EABRE1

0.9

EABRE2

0.4

EABCLK

0.0

EABCO

0.3

EABBYPASS

0.5

0.6

EABSU

1.0

EABH

0.5

0.4

EABCLR

0.3

3.4

3.6

2.7

2.8

1.0

WDSU

1.0

WDH

0.1

WASU

1.8

1.9

WAH

1.9

2.0

RASU

3.1

3.5

RAH

0.2

2.7

2.8

2.7

2.8

EABOUT

0.5

0.6

EABCH

1.5

2.0

EABCL

2.7

2.8

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Table 33. EP1K10 Device EAB Internal Timing Macroparameters

Note (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABAA

6.7

7.3

EABRCCOMB

6.7

7.3

EABRCREG

4.7

4.9

EABWP

2.7

2.8

EABWCCOMB

6.4

6.7

EABWCREG

7.4

7.6

EABDD

6.0

6.5

EABDATACO

0.8

0.9

EABDATASU

1.6

1.7

EABDATAH

0.0

EABWESU

1.4

EABWEH

0.1

0.0

EABWDSU

1.6

1.7

EABWDH

0.0

EABWASU

3.1

3.4

EABWAH

0.6

0.5

EABWO

5.4

5.8

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 34. EP1K10 Device Interconnect Timing Microparameters

Note (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DIN2IOE

2.3

2.7

3.6

DIN2LE

0.8

1.1

1.4

DIN2DATA

1.1

1.4

1.8

DCLK2IOE

2.3

2.7

3.6

DCLK2LE

0.8

1.1

1.4

SAMELAB

0.1

0.2

SAMEROW

1.8

2.1

2.9

SAMECOLUMN

0.3

0.4

0.7

DIFFROW

2.1

2.5

3.6

TWOROWS

3.9

4.6

6.5

LEPERIPH

3.3

3.7

4.8

LABCARRY

0.3

0.4

0.5

LABCASC

0.9

1.0

1.4

Table 35. EP1K10 External Timing Parameters

Note (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DRR

7.5

9.5

12.5

INSU

(3)

(4)

2.4

2.7

3.6

INH

(3)

(4)

0.0

OUTCO

(3)

(4)

2.0

6.6

2.0

7.8

2.0

9.6

INSU

(5)

(4)

1.4

1.7

INH

(5)

(4)

0.5

5.1

0.5

6.4

OUTCO

(5)

(4)

0.0

PCISU

(4)

3.0

4.2

6.4

PCIH

(4)

0.0

PCICO

(4)

2.0

6.0

2.0

7.5

2.0

10.2

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Notes to tables:
(1)

All timing parameters are described in

Tables 22

through

in this data sheet.

(2)

This timing information is preliminary.

(3)

This parameter is measured without the use of the ClockLock or ClockBoost circuits.

(4)

These parameters are specified by characterization.

(5)

This parameter is measured with the use of the ClockLock or ClockBoost circuits.

Tables 37

through

show EP1K30 device internal and external timing

parameters.

Table 36. EP1K10 External Bidirectional Timing Parameters

Notes (1)

(2)

(4)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

INSUBIDIR

(3)

2.2

2.3

3.2

INHBIDIR

(3)

0.0

OUTCOBIDIR

(3)

2.0

6.6

2.0

7.8

2.0

9.6

XZBIDIR

(3)

8.8

11.2

14.0

ZXBIDIR

(3)

8.8

11.2

14.0

INSUBIDIR

(5)

3.1

3.3

INHBIDIR

(5)

0.0

OUTCOBIDIR

(5)

0.5

5.1

0.5

6.4

XZBIDIR

(5)

7.3

9.2

ZXBIDIR

(5)

7.3

9.2

Table 37. EP1K30 Device LE Timing Microparameters (Part 1 of 2)

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

LUT

0.7

0.8

1.1

CLUT

0.5

0.6

0.8

RLUT

0.6

0.7

1.0

PACKED

0.3

0.4

0.5

0.6

0.8

1.0

CICO

0.1

0.2

CGEN

0.4

0.5

0.7

CGENR

0.1

0.2

CASC

0.6

0.8

1.0

0.0

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

0.3

0.4

0.5

COMB

0.4

0.6

0.4

0.6

0.7

1.0

1.3

PRE

0.8

0.9

1.2

CLR

0.8

0.9

1.2

2.0

2.5

2.0

2.5

Table 38. EP1K30 Device IOE Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

IOD

2.4

2.8

3.8

IOC

0.3

0.4

0.5

IOCO

1.0

1.1

1.6

IOCOMB

0.0

IOSU

1.2

1.4

1.9

IOH

0.3

0.4

0.5

IOCLR

1.0

1.1

1.6

OD1

1.9

2.3

3.0

OD2

1.4

1.8

2.5

OD3

4.4

5.2

7.0

2.7

3.1

4.3

ZX1

2.7

3.1

4.3

ZX2

2.2

2.6

3.8

ZX3

5.2

6.0

8.3

INREG

3.4

4.1

5.5

IOFD

0.8

1.3

2.4

INCOMB

0.8

1.3

2.4

Table 37. EP1K30 Device LE Timing Microparameters (Part 2 of 2)

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Table 39. EP1K30 Device EAB Internal Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABDATA1

1.7

2.0

2.3

EABDATA1

0.6

0.7

0.8

EABWE1

1.1

1.3

1.4

EABWE2

0.4

0.5

EABRE1

0.8

0.9

1.0

EABRE2

0.4

0.5

EABCLK

0.0

EABCO

0.3

0.4

EABBYPASS

0.5

0.6

0.7

EABSU

0.9

1.0

1.2

EABH

0.4

0.5

EABCLR

0.3

3.2

3.8

4.4

2.5

2.9

3.3

0.9

1.1

1.2

WDSU

0.9

1.0

1.1

WDH

0.1

WASU

1.7

2.0

2.3

WAH

1.8

2.1

2.4

RASU

3.1

3.7

4.2

RAH

0.2

2.5

2.9

3.3

2.5

2.9

3.3

EABOUT

0.5

0.6

0.7

EABCH

1.5

2.0

2.3

EABCL

2.5

2.9

3.3

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 40. EP1K30 Device EAB Internal Timing Macroparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABAA

6.4

7.6

8.8

EABRCOMB

6.4

7.6

8.8

EABRCREG

4.4

5.1

6.0

EABWP

2.5

2.9

3.3

EABWCOMB

6.0

7.0

8.0

EABWCREG

6.8

7.8

9.0

EABDD

5.7

6.7

7.7

EABDATACO

0.8

0.9

1.1

EABDATASU

1.5

1.7

2.0

EABDATAH

0.0

EABWESU

1.3

1.4

1.7

EABWEH

0.0

EABWDSU

1.5

1.7

2.0

EABWDH

0.0

EABWASU

3.0

3.6

4.3

EABWAH

0.5

0.4

EABWO

5.1

6.0

6.8

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Table 41. EP1K30 Device Interconnect Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DIN2IOE

1.8

2.4

2.9

DIN2LE

1.5

1.8

2.4

DIN2DATA

1.5

1.8

2.2

DCLK2IOE

2.2

2.6

3.0

DCLK2LE

1.5

1.8

2.4

SAMELAB

0.1

0.2

0.3

SAMEROW

2.0

2.4

2.7

SAMECOLUMN

0.7

1.0

0.8

DIFFROW

2.7

3.4

3.5

TWOROWS

4.7

5.8

6.2

LEPERIPH

2.7

3.4

3.8

LABCARRY

0.3

0.4

0.5

LABCASC

0.8

1.1

Table 42. EP1K30 External Timing Parameters

Notes (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DRR

8.0

9.5

12.5

INSU

(3)

2.1

2.5

3.9

INH

(3)

0.0

OUTCO

(3)

2.0

4.9

2.0

5.9

2.0

7.6

INSU

(4)

1.1

1.5

INH

(4)

0.0

OUTCO

(4)

0.5

3.9

0.5

4.9

PCISU

3.0

4.2

PCIH

0.0

PCICO

2.0

6.0

2.0

7.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Notes to tables:
(1)

All timing parameters are described in

Tables 22

through

in this data sheet.

(2)

These parameters are specified by characterization.

(3)

This parameter is measured without the use of the ClockLock or ClockBoost circuits.

(4)

This parameter is measured with the use of the ClockLock or ClockBoost circuits.

Tables 44

through

show EP1K50 device external timing parameters.

Table 43. EP1K30 External Bidirectional Timing Parameters

Notes (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

INSUBIDIR

(3)

2.8

3.9

5.2

INHBIDIR

(3)

0.0

INSUBIDIR

(4)

3.8

4.9

INHBIDIR

(4)

0.0

OUTCOBIDIR

(3)

2.0

4.9

2.0

5.9

2.0

7.6

XZBIDIR

(3)

6.1

7.5

9.7

ZXBIDIR

(3)

6.1

7.5

9.7

OUTCOBIDIR

(4)

0.5

3.9

0.5

4.9

XZBIDIR

(4)

5.1

6.5

ZXBIDIR

(4)

5.1

6.5

Table 44. EP1K50 Device LE Timing Microparameters (Part 1 of 2)

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

LUT

0.6

0.8

1.1

CLUT

0.5

0.6

0.8

RLUT

0.6

0.7

0.9

PACKED

0.2

0.3

0.4

0.6

0.7

0.9

CICO

0.1

CGEN

0.4

0.5

0.6

CGENR

0.1

CASC

0.5

0.8

1.0

0.5

0.6

0.8

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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ools

0.6

0.7

COMB

0.3

0.4

0.5

0.6

0.7

0.5

0.6

0.8

PRE

0.4

0.5

0.7

CLR

0.8

1.0

1.2

2.0

2.5

3.0

2.0

2.5

3.0

Table 45. EP1K50 Device IOE Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

IOD

1.3

1.9

IOC

0.3

0.4

IOCO

1.7

2.1

2.6

IOCOMB

0.5

0.6

0.8

IOSU

0.8

1.0

1.3

IOH

0.4

0.5

0.6

IOCLR

0.2

0.4

OD1

1.2

1.9

OD2

0.7

0.8

1.7

OD3

2.7

3.0

4.3

4.7

5.7

7.5

ZX1

4.7

5.7

7.5

ZX2

4.2

5.3

7.3

ZX3

6.2

7.5

9.9

INREG

3.5

4.2

5.6

IOFD

1.1

1.3

1.8

INCOMB

1.1

1.3

1.8

Table 44. EP1K50 Device LE Timing Microparameters (Part 2 of 2)

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 46. EP1K50 Device EAB Internal Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABDATA1

1.7

2.4

3.2

EABDATA2

0.4

0.6

0.8

EABWE1

1.0

1.4

1.9

EABWE2

0.0

EABRE1

0.0

EABRE2

0.4

0.6

0.8

EABCLK

0.0

EABCO

0.8

1.1

1.5

EABBYPASS

0.0

EABSU

0.7

1.0

1.3

EABH

0.4

0.6

0.8

EABCLR

0.8

1.1

1.5

2.0

2.8

3.8

2.0

2.8

3.8

1.0

1.4

1.9

WDSU

0.5

0.7

0.9

WDH

0.1

0.2

WASU

1.0

1.4

1.9

WAH

1.5

2.1

2.9

RASU

1.5

2.1

2.8

RAH

0.1

0.2

2.1

2.9

4.0

2.1

2.9

4.0

EABOUT

0.0

EABCH

1.5

2.0

2.5

EABCL

1.5

2.0

2.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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ools

Table 47. EP1K50 Device EAB Internal Timing Macroparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABAA

3.7

5.2

7.0

EABRCCOMB

3.7

5.2

7.0

EABRCREG

3.5

4.9

6.6

EABWP

2.0

2.8

3.8

EABWCCOMB

4.5

6.3

8.6

EABWCREG

5.6

7.8

10.6

EABDD

3.8

5.3

7.2

EABDATACO

0.8

1.1

1.5

EABDATASU

1.1

1.6

2.1

EABDATAH

0.0

EABWESU

0.7

1.0

1.3

EABWEH

0.4

0.6

0.8

EABWDSU

1.2

1.7

2.2

EABWDH

0.0

EABWASU

1.6

2.3

3.0

EABWAH

0.9

1.2

1.8

EABWO

3.1

4.3

5.9

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 48. EP1K50 Device Interconnect Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DIN2IOE

3.1

3.7

4.6

DIN2LE

1.7

2.1

2.7

DIN2DATA

2.7

3.1

5.1

DCLK2IOE

1.6

1.9

2.6

DCLK2LE

1.7

2.1

2.7

SAMELAB

0.1

0.2

SAMEROW

1.5

1.7

2.4

SAMECOLUMN

1.0

1.3

2.1

DIFFROW

2.5

3.0

4.5

TWOROWS

4.0

4.7

6.9

LEPERIPH

2.6

2.9

3.4

LABCARRY

0.1

0.2

LABCASC

0.8

1.0

1.3

Table 49. EP1K50 External Timing Parameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DRR

8.0

9.5

12.5

INSU

(2)

2.4

2.9

3.9

INH

(2)

0.0

OUTCO

(2)

2.0

4.3

2.0

5.2

2.0

7.3

INSU

(3)

2.4

2.9

INH

(3)

0.0

OUTCO

(3)

0.5

3.3

0.5

4.1

PCISU

2.4

2.9

PCIH

0.0

PCICO

2.0

6.0

2.0

7.7

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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ools

Notes to tables:
(1)

All timing parameters are described in

Tables 22

through

(2)

This parameter is measured without use of the ClockLock or ClockBoost circuits.

(3)

This parameter is measured with use of the ClockLock or ClockBoost circuits

Table 50. EP1K50 External Bidirectional Timing Parameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

INSUBIDIR

(2)

2.7

3.2

4.3

INHBIDIR

(2)

0.0

INSUBIDIR

(3)

3.7

4.2

INHBIDIR

(3)

0.0

OUTCOBIDIR

(2)

2.0

4.5

2.0

5.2

2.0

7.3

XZBIDIR

(2)

6.8

7.8

10.1

ZXBIDIR

(2)

6.8

7.8

10.1

OUTCOBIDIR

(3)

0.5

3.5

0.5

4.2

XZBIDIR

(3)

6.8

8.4

ZXBIDIR

(3)

6.8

8.4

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Tables 51

through

show EP1K100 device internal and external timing

parameters.

Table 51. EP1K100 Device LE Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

LUT

0.7

1.0

1.5

CLUT

0.5

0.7

0.9

RLUT

0.6

0.8

1.1

PACKED

0.3

0.4

0.5

0.2

0.3

CICO

0.1

0.2

CGEN

0.4

0.5

0.7

CGENR

0.1

0.2

CASC

0.6

0.9

1.2

0.8

1.0

1.4

0.6

0.8

1.1

COMB

0.4

0.5

0.7

0.4

0.6

0.7

0.5

0.7

0.9

PRE

0.8

1.0

1.4

CLR

0.8

1.0

1.4

1.5

2.0

2.5

1.5

2.0

2.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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ools

Table 52. EP1K100 Device IOE Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

IOD

1.7

2.0

2.6

IOC

0.0

IOCO

1.4

1.6

2.1

IOCOMB

0.5

0.7

0.9

IOSU

0.8

1.0

1.3

IOH

0.7

0.9

1.2

IOCLR

0.5

0.7

0.9

OD1

3.0

4.2

5.6

OD2

3.0

4.2

5.6

OD3

4.0

5.5

7.3

3.5

4.6

6.1

ZX1

3.5

4.6

6.1

ZX2

3.5

4.6

6.1

ZX3

4.5

5.9

7.8

INREG

2.0

2.6

3.5

IOFD

0.5

0.8

1.2

INCOMB

0.5

0.8

1.2

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 53. EP1K100 Device EAB Internal Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABDATA1

1.5

2.0

2.6

EABDATA1

0.0

EABWE1

1.5

2.0

2.6

EABWE2

0.3

0.4

0.5

EABRE1

0.3

0.4

0.5

EABRE2

0.0

EABCLK

0.0

EABCO

0.3

0.4

0.5

EABBYPASS

0.1

0.2

EABSU

0.8

1.0

1.4

EABH

0.1

0.2

EABCLR

0.3

0.4

0.5

4.0

5.1

6.6

2.7

3.5

4.7

1.0

1.3

1.7

WDSU

1.0

1.3

1.7

WDH

0.2

0.3

WASU

1.6

2.1

2.8

WAH

1.6

2.1

2.8

RASU

3.0

3.9

5.2

RAH

0.1

0.2

1.5

2.0

2.6

1.5

2.0

2.6

EABOUT

0.2

0.3

EABCH

1.5

2.0

2.5

EABCL

2.7

3.5

4.7

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

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ools

Table 54. EP1K100 Device EAB Internal Timing Macroparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

EABAA

5.9

7.6

9.9

EABRCOMB

5.9

7.6

9.9

EABRCREG

5.1

6.5

8.5

EABWP

2.7

3.5

4.7

EABWCOMB

5.9

7.7

10.3

EABWCREG

5.4

7.0

9.4

EABDD

3.4

4.5

5.9

EABDATACO

0.5

0.7

0.8

EABDATASU

0.8

1.0

1.4

EABDATAH

0.1

0.2

EABWESU

1.1

1.4

1.9

EABWEH

0.0

EABWDSU

1.0

1.3

1.7

EABWDH

0.2

0.3

EABWASU

4.1

5.2

6.8

EABWAH

0.0

EABWO

3.4

4.5

5.9

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 55. EP1K100 Device Interconnect Timing Microparameters

Note (1)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DIN2IOE

3.1

3.6

4.4

DIN2LE

0.3

0.4

0.5

DIN2DATA

1.6

1.8

2.0

DCLK2IOE

0.8

1.1

1.4

DCLK2LE

0.3

0.4

0.5

SAMELAB

0.1

0.2

SAMEROW

1.5

2.5

3.4

SAMECOLUMN

0.4

1.0

1.6

DIFFROW

1.9

3.5

5.0

TWOROWS

3.4

6.0

8.4

LEPERIPH

4.3

5.4

6.5

LABCARRY

0.5

0.7

0.9

LABCASC

0.8

1.0

1.4

Table 56. EP1K100 External Timing Parameters

Notes (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

DRR

9.0

12.0

16.0

INSU

(3)

2.0

2.5

3.3

INH

(3)

0.0

OUTCO

(3)

2.0

5.2

2.0

6.9

2.0

9.1

INSU

(4)

2.0

2.2

INH

(4)

0.0

OUTCO

(4)

0.5

3.0

0.5

4.6

PCISU

3.0

6.2

PCIH

0.0

PCICO

2.0

6.0

2.0

6.9

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Development

T
ools

Notes to tables:
(1)

All timing parameters are described in

Tables 22

through

in this data sheet.

(2)

These parameters are specified by characterization.

(3)

This parameter is measured without the use of the ClockLock or ClockBoost circuits.

(4)

This parameter is measured with the use of the ClockLock or ClockBoost circuits.

Power
Consumption

The supply power (P) for ACEX 1K devices can be calculated with the
following equation:

P = P

INT

+ P

= (I

CCSTANDBY

+ I

CCACTIVE)

× V

+ P

The I

CCACTIVE

value depends on the switching frequency and the

application logic. This value is calculated based on the amount of current
that each LE typically consumes. The P

value, which depends on the

device output load characteristics and switching frequency, can be
calculated using the guidelines given in

Application Note 74 (Evaluating

Power for Altera Devices).

Compared to the rest of the device, the embedded array
consumes a negligible amount of power. Therefore, the
embedded array can be ignored when calculating supply
current.

Table 57. EP1K100 External Bidirectional Timing Parameters

Notes (1)

(2)

Symbol

Speed Grade

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

INSUBIDIR

(3)

1.7

2.5

3.3

INHBIDIR

(3)

0.0

INSUBIDIR

(4)

2.0

2.8

INHBIDIR

(4)

0.0

OUTCOBIDIR

(3)

2.0

5.2

2.0

6.9

2.0

9.1

XZBIDIR

(3)

5.6

7.5

10.1

ZXBIDIR

(3)

5.6

7.5

10.1

OUTCOBIDIR

(4)

0.5

3.0

0.5

4.6

XZBIDIR

(4)

4.6

6.5

ZXBIDIR

(4)

4.6

6.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

The I

CCACTIVE

value can be calculated with the following equation:

CCACTIVE

= K

× f

MAX

× N × tog

(

µA)

Where:

MAX

= Maximum operating frequency in MHz

= Total number of LEs used in the device

tog

= Average percent of LEs toggling at each clock

(typically 12.5%)

K =

Constant

Table 58

provides the constant (K) values for ACEX 1K devices.

This supply power calculation provides an I

estimate based on typical

conditions with no output load. The actual I

should be verified during

operation because this measurement is sensitive to the actual pattern in
the device and the environmental operating conditions.

To better reflect actual designs, the power model (and the constant K in
the power calculation equations) for continuous interconnect ACEX 1K
devices assumes that LEs drive FastTrack Interconnect channels. In
contrast, the power model of segmented FPGAs assumes that all LEs
drive only one short interconnect segment. This assumption may lead to
inaccurate results when compared to measured power consumption for
actual designs in segmented FPGAs.

Figure 31

shows the relationship between the current and operating

frequency of ACEX 1K devices. For information on other ACEX 1K
devices, contact Altera Applications at (800) 800-EPLD.

Table 58. ACEX 1K Constant Values

Device

K Value

EP1K10

4.5

EP1K30

4.5

EP1K50

4.5

EP1K100

4.5

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

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ools

Figure 31. ACEX 1K I

CCACTIVE

vs. Operating Frequency

Configuration &
Operation

The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.

Operating Modes

The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as V

rises, the device initiates a

Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50

µs.

When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.

Frequency (MHz)

300

200

100

EP1K100

Supply

Current (mA)

Frequency (MHz)

Supply

Current (mA)

100

EP1K30

Frequency (MHz)

Supply

Current (mA)

200

150

100

EP1K50

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device. Before and during configuration, all I/O pins (except dedicated
inputs, clock, or configuration pins) are pulled high by a weak pull-up
resistor. Together, the configuration and initialization processes are called
command mode; normal device operation is called user mode.

SRAM configuration elements allow ACEX 1K devices to be reconfigured
in-circuit by loading new configuration data into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loading different configuration data, re-initializing the
device, and resuming user-mode operation. The entire reconfiguration
process requires less than 40 ms and can be used to reconfigure an entire
system dynamically. In-field upgrades can be performed by distributing
new configuration files.

Configuration Schemes

The configuration data for an ACEX 1K device can be loaded with one of
five configuration schemes (see

Table 59

), chosen on the basis of the target

application. An EPC16, EPC2, EPC1, or EPC1441 configuration device,
intelligent controller, or the JTAG port can be used to control the
configuration of a ACEX 1K device, allowing automatic configuration on
system power-up.

Multiple ACEX 1K devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FLEX 10KE, ACEX 1K,
and FLEX 6000 devices can be configured in the same serial chain.

Device Pin-
Outs

See the Altera web site (http://www.altera.com) or the Altera Digital
Library

for pin-out information.

Table 59. Data Sources for ACEX 1K Configuration

Configuration Scheme

Data Source

Configuration device

EPC16, EPC2, EPC1, or EPC1441 configuration device

Passive serial (PS)

BitBlaster or ByteBlasterMV download cables, or serial data
source

Passive parallel asynchronous (PPA)

Parallel data source

Passive parallel synchronous (PPS)

Parallel data source

JTAG

BitBlaster or ByteBlasterMV download cables, or
microprocessor with a Jam STAPL File or JBC File

Altera, ACEX, ACEX 1K, APEX, APEX 20K, APEX 20KE, BitBlaster, ByteBlaster, ByteBlasterMV, ClockBoost,
ClockLock, EP1K10, EP1K30, EP1K50, EP1K100, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE,
Jam, MasterBlaster, MAX, MAX+PLUS, MAX+PLUS II, MegaCore, MultiVolt, and SameFrame are trademarks
and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the
trademarks of other organizations for their respective products or services mentioned in this document. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights,
and copyrights. Altera warrants performance of its semiconductor products to current specifications in
accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application
or use of any information, product, or service described herein except as expressly agreed
to in writing by Altera Corporation. Altera customers are advised to obtain the latest
version of device specifications before relying on any published information and before
placing orders for products or services.

101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Marketing:

(408) 544-7104

Literature Services:

(888) 3-ALTERA
lit_req@altera.com

ACEX 1K Programmable Logic Device Family Data Sheet

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