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September 2005
ASM5P2304B
rev 0.5
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V Zero Delay Buffer
Features
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer "ASM5P2304B
Configurations Table".
Input frequency range: 4MHz to 20MHz
Multiple
low-skew
outputs.
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of four outputs.
Less than 200pS Cycle-to-Cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8-pin 150 mil SOIC
Package.
3.3V
operation.
Advanced 0.35 CMOS technology.
Industrial temperature available
.
Functional Description
ASM5P2304B is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks in PC,
workstation, datacom, telecom and other high-performance
applications. It is available in an 8 pin package. The part
has an on-chip PLL, which locks to an input clock,
presented on the REF pin. The PLL feedback is required to
be driven to FBK pin, and can be obtained from one of the
outputs. The input-to-output propagation delay is
guaranteed to be less than 250pS, and the output-to-output
skew is guaranteed to be less than 200pS.
The ASM5P2304B has two banks of two outputs each.
Multiple ASM5P2304B devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
The ASM5P2304B is available in two different
configurations (Refer "ASM5P2304B Configurations Table).
The ASM5P2304B-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304B-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster. The ASM5P2304B-2 allows the user to
obtain REF and 1/2X or 2X frequencies on each output
bank. The exact configuration and output frequencies
depend on which output drives the feedback pin.
Block Diagram
/2
PLL
CLKA1
FBK
CLKA2
CLKB1
CLKB2
REF
Extra Divider (-2)
September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
2 of 13
Notice: The information in this document is subject to change without notice.
ASM5P2304B Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2304B-1
Bank A or Bank B
Reference
Reference
ASM5P2304B-1H
Bank A or Bank B
Reference
Reference
ASM5P2304B-2
Bank A
Reference
Reference /2
ASM5P2304B-2
Bank B
2 X Reference
Reference
ASM5P2304B-2H
Bank A
Reference
Reference /2
ASM5P2304B-2H
Bank B
2 X Reference
Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
To close the feedback loop of the ASM5P2304B, the FBK
pin can be driven from any of the four available output pins.
The output driving the FBK pin will be driving a total load of
7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph. For applications requiring zero input-
output delay, all outputs including the one providing
feedback should be equally loaded. If input-output delay
adjustments are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be sure to
load outputs equally.
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
0
-500
-1000
-1500
500
1000
1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF-Inp
u
t to CL
KA/CLKB Delay (
p
S)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
3 of 13
Notice: The information in this document is subject to change without notice.
CLKB1
1
2
3
4
5
6
7
8
ASM5P2304B
REF
CLKA1
CLKA2
GND
CLKB2
V
DD
FBK
Pin Configuration
Pin Description for ASM5P2304B
Pin #
Pin Name
Description
1 REF
1
Input reference frequency, 5V tolerant input
2 CLKA1
2
Buffered clock output, bank A
3 CLKA2
2
Buffered clock output, bank A
4 GND
Ground
5 CLKB1
2
Buffered clock output, bank B
6 CLKB2
2
Buffered clock output, bank B
7 V
DD
3.3V
supply
8
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
4 of 13
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
-0.5
+7.0
V
DC Input Voltage (Except REF)
-0.5
V
DD
+ 0.5
V
DC Input Voltage (REF)
-0.5
7
V
Storage Temperature
-65
+150
C
Max. Soldering Temperature (10 sec)
260
C
Junction Temperature
150
C
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2000 V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
V
DD
Supply
Voltage
3.0
3.6
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
L
Load Capacitance, from 4MHz to 20MHz
30
pF
C
IN
Input
Capacitance
3
7
pF
Electrical Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
V
IL
Input LOW Voltage
0.8
V
V
IH
Input HIGH Voltage
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
50.0
A
I
IH
Input HIGH Current
V
IN
= V
DD
100.0
A
V
OL
Output LOW Voltage
4
I
OL
= 8mA (-1, -2)
I
OH
= 12mA (-1H, -2H)
0.4
V
V
OH
Output HIGH Voltage
4
I
OL
= -8mA (-1, -2)
I
OH
= -12mA (-1H, -2H)
2.4
V
I
DD
Supply Current
Unloaded outputs, 20MHz REF (-1,-1H, -2,-2H)
10
mA
Note:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
September 2005
ASM5P2304B
rev 0.5
3.3V Zero Delay Buffer
5 of 13
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
1/t
1
Output Frequency
30pF load, -1,-1H,-2, -2H devices
4
20
MHz
Duty Cycle
5
= (t
2
/ t
1
) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, F
OUT
= 20MHz
30pF load
40.0 50.0 60.0
%
Duty Cycle
5
= (t
2
/ t
1
) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, F
OUT
= <20MHz
15pF load
45.0 50.0 55.0
%
t
3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
2.20
nS
t
3
Output Rise Time
5
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
1.50
nS
t
3
Output Rise Time
5
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
1.50
nS
t
4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
2.20
nS
t
4
Output Fall Time
5
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
1.50
nS
t
4
Output Fall Time
5
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
nS
Output-to-output skew on same bank
(-1, -2)
All outputs equally loaded
200
Output-to-output skew (-1H, -2H)
All outputs equally loaded
200
Output bank A -to- output bank B skew
(-1, -2H)
All outputs equally loaded
200
t
5
Output bank A to output bank b skew
(-2)
All outputs equally loaded
400
pS
t
6
Delay, REF Rising Edge to FBK Rising
Edge
5
Measured at V
DD
/2
0
250
pS
t
7
Device-to-Device
Skew
5
Measured at V
DD
/2 on the FBK pins of
the device
0
500
pS
t
8
Output Slew Rate
5
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/nS
Measured at 20MHz, loaded outputs,
15pF load
175
Measured at 20MHz, loaded outputs,
30pF load
200
t
J
Cycle-to-cycle jitter
5
(-1, -1H, -2H)
Measured at 20MHz, loaded outputs,
15pF load
100
pS
Measured at 20MHz, loaded outputs,
30pF load
400
t
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