www.docs.chipfind.ru
August 2004
ASM4SSTVF16859
rev 2.0
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
DDR 13-Bit to 26-Bit Registered Buffer
Features
Differential clock signals.
Meets SSTL_2 class II specifications on
outputs.
Low voltage operation: V
DD
= 2.3V to 2.7V.
Available in 64-pin TSSOP, 64-pin TVSOP,
and 56-pin VFQFN packages.
Product Description
The ASM4SSTVF16859 is a universal 13/26 bit
register
(D F/F based), designed for 2.3V to 2.7V
V
DD
operation. The device supports SSTL_2 I/O
levels, and is fully compliant with the JEDEC JC40,
JC42.5 DDR I specifications covering PC1600, PC
2100, PC2700, and PC3200 operational ranges ( DDR
400
200 MHz ). 13/26 bits refers to 2Q outputs for
each D input - designed for use in Stacked Registered
(stacked
Memory
Devices),
Buffered
DIMM
applications.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB).
The positive edge of CLK is used to trigger the data
transfer, and CLKB is used to maintain sufficient noise
margins, whereas RESETB input is designed and
intended for use at power-up.
The ASM4SSTVF16859 supports a low power standby
mode of operation. A logic level low at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic low state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Note that RESETB should be supported with a
LVCMOS level at a valid state since VREF may not be
stable during power-up.
To ensure that outputs are at a defined logic state before a
stable clock has been supplied, RESETB must be held at a
logic low level during power-up.
In the JEDEC defined Registered DDR DIMM application,
RESETB is specified to be asynchronous with respect to
CLK/CLKB; therefore, no timing relationship can be
guaranteed between the two signals. When entering a
low-power standby state, the register will be cleared and
the outputs will be driven to a logic low level quickly
relative to the time to disable the differential input
receivers. This ensures there are no "glitches" on any
output. However, when coming out of low power standby
mode, the register will become active quickly relative to the
time taken to enable the differential input receivers. When
the data inputs are at a logic level low and the clock is
stable during the low-to-high transition of RESETB until the
input receivers are fully enabled, the design ensures that
the outputs will remain at a logic low level.
Applications
JEDEC and Non-JEDEC DDR Memory Modules
Stacked or Planar configurations.
Supports PC1600 - PC2100 - PC2700 - PC3200
DDR 400 compliant (200MHz+).
SSTL_2 I/O.
Provides a complete support solution for JEDEC
JC42.5 DIMMs' when used with the ASM5CVF857
Zero Delay Buffer.
August
2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
1 of 16
Block Diagram
CLK
CLKB
RESETB
D1
VREF
R
CLK
D1
Q1A
Q1B
To 12 other channels
ASM4SSTVF16859
August
2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
2 of 16
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESETB
GND
CLKB
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
A
S
M
4
S
S
T
V
F
1
6
8
5
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
ASM4SSTVF16859
64-pin TSSOP
6.10 mm body, 0.50 mm pitch
56-pin VFQFN (MLF2)
August
2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
3 of 16
Pin Descriptions
64-pin TSSOP
Pin #
Pin Name
Type
Description
1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16,
17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
31, 32
Q (13:1)
O
Data output.
7, 15, 26, 34, 39, 43, 50, 54, 58, 63
GND
P
Ground to entire chip.
6, 18, 27, 33, 38, 47, 59, 64
VDDQ
P
Output supply voltage, 2.5V nominal.
35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57,
61, 62
D(13:1)
I
Data input.
48
CLK
I
Positive master clock input.
49
CLKB
I
Negative master clock input.
37, 46, 60
VDD
P
Core supply voltage, 2.5V nominal.
51
RESETB
I
Rest Active low.
45
VREF
I
Input reference voltage, 1.25V nominal.
56-pin MLF2
Pin #
Pin Name
Type
Description
1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16,
18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56
Q (13:1)
O
Data output.
37, 48
GND
P
Ground to entire chip.
9, 17, 23, 27, 34, 44, 49, 55
VDDQ
P
Output supply voltage, 2.5V nominal.
24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47
D(13:1)
I
Data input.
35
CLK
I
Positive master clock input.
36
CLKB
I
Negative master clock input.
26, 33, 45
VDD
P
Core supply voltage, 2.5V nominal.
38
RESETB
I
Rest Active low.
32
VREF
I
Input reference voltage, 1.25V nominal.
-
Center Pad
P
Ground (VFQFN package only)
August
2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
4 of 16
Truth Table
Inputs
Q Outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H
H
H
H
L
L
H
L or H
L or H
X
Q
0
2
Note:
1. H=Hig
h signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don't care
2. Output level before the indicated steady state input conditions were established.
1
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Storage Temperature
-65
+150
C
Supply Voltage
-0.5
3.6
V
Input Voltage
1
-0.5
V
DD
+ 0.5
V
Output Voltage
1,2
-0.5
V
DD
+ 0.5
V
Input Clamp Current
50
mA
Output Clamp Current
50
mA
Continuous Output Current
50
mA
VDD, VDDQ or GND current/pin
100
mA
Package Thermal Impedance
3
55
C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
0
> V
DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods
can affect device reliability.
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